Created
March 8, 2023 13:34
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LSFR Verilog Implementation example
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module lfsr( | |
input clk, | |
input rst, | |
output reg [3:0] rand_out, | |
output reg [3:0] LED | |
); | |
reg [3:0] lfsr_reg; | |
always @(posedge clk or posedge rst) begin | |
if (rst) begin | |
lfsr_reg <= 4'b0001; // set initial value of LFSR | |
end else begin | |
lfsr_reg <= {lfsr_reg[2:0], lfsr_reg[3] ^ lfsr_reg[2]}; | |
// feedback taps at bits 3 and 2, shift left | |
end | |
end | |
assign rand_out = lfsr_reg; | |
assign LED = lfsr_reg; | |
endmodule |
Author
DanielChuDC
commented
Mar 8, 2023
module lfsr (
output reg [3:0] LED,
input clk,
input rst
);
reg [3:0] lfsr_reg;
wire feedback;
assign feedback = ~(lfsr_reg[3] ^ lfsr_reg[2]);
always @(posedge clk, posedge rst) begin
if (rst) begin
lfsr_reg <= 4'b0001; // set initial value of LFSR
LED <= lfsr_reg; // update LED output
end else begin
lfsr_reg <= {lfsr_reg[2:0], feedback}; // update LFSR
LED <= lfsr_reg; // update LED output
end
end
endmodule
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