Skip to content

Instantly share code, notes, and snippets.

@DanielG

DanielG/yosys-grom-test.log

Created August 22, 2023 16:13
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save DanielG/084cf786c57afc4050dd5f874bee7869 to your computer and use it in GitHub Desktop.
Save DanielG/084cf786c57afc4050dd5f874bee7869 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
yosys-grom-test.log
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.32+51 (git sha1 4e4504735, gcc 13.2.0-2 -fPIC -Os)
-- Executing script file `grom.ys' --
1. Executing Verilog-2005 frontend: grom_computer.v
Parsing Verilog input from `grom_computer.v' to AST representation.
Generating RTLIL representation for module `\grom_computer'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: grom_cpu.v
Parsing Verilog input from `grom_cpu.v' to AST representation.
Generating RTLIL representation for module `\grom_cpu'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: alu.v
Parsing Verilog input from `alu.v' to AST representation.
Generating RTLIL representation for module `\alu'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: ram_memory.v
Parsing Verilog input from `ram_memory.v' to AST representation.
Generating RTLIL representation for module `\ram_memory'.
Successfully finished Verilog frontend.
5. Executing PREP pass.
5.1. Executing HIERARCHY pass (managing design hierarchy).
5.1.1. Analyzing design hierarchy..
Top module: \grom_computer
Used module: \ram_memory
Used module: \grom_cpu
Used module: \alu
5.1.2. Analyzing design hierarchy..
Top module: \grom_computer
Used module: \ram_memory
Used module: \grom_cpu
Used module: \alu
Removed 0 unused modules.
5.2. Executing PROC pass (convert processes to netlists).
5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$ram_memory.v:34$173 in module ram_memory.
Removed 1 dead cases from process $proc$alu.v:34$144 in module alu.
Marked 1 switch rules as full_case in process $proc$alu.v:34$144 in module alu.
Removed 6 dead cases from process $proc$grom_cpu.v:56$17 in module grom_cpu.
Marked 15 switch rules as full_case in process $proc$grom_cpu.v:56$17 in module grom_cpu.
Removed a total of 7 dead cases.
5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 44 assignments to connections.
5.2.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\grom_cpu.$proc$grom_cpu.v:40$143'.
Set init value: \state = 5'00000
5.2.5. Executing PROC_ARST pass (detect async resets in processes).
5.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~21 debug messages>
5.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ram_memory.$proc$ram_memory.v:0$197'.
Creating decoders for process `\ram_memory.$proc$ram_memory.v:34$173'.
1/4: $1$memwr$\store$ram_memory.v:36$172_EN[7:0]$179
2/4: $1$memwr$\store$ram_memory.v:36$172_DATA[7:0]$178
3/4: $1$memwr$\store$ram_memory.v:36$172_ADDR[11:0]$177
4/4: $0\data_out[7:0]
Creating decoders for process `\alu.$proc$alu.v:34$144'.
1/1: $1\tmp[8:0]
Creating decoders for process `\grom_cpu.$proc$grom_cpu.v:40$143'.
Creating decoders for process `\grom_cpu.$proc$grom_cpu.v:56$17'.
1/77: $4$memwr$\R$grom_cpu.v:641$14_EN[7:0]$136
2/77: $4$memwr$\R$grom_cpu.v:641$14_DATA[7:0]$135
3/77: $4$memwr$\R$grom_cpu.v:641$14_ADDR[1:0]$134
4/77: $6\jump[0:0]
5/77: $5\jump[0:0]
6/77: $4\jump[0:0]
7/77: $3\jump[0:0]
8/77: $3$memwr$\R$grom_cpu.v:641$14_EN[7:0]$116
9/77: $3$memwr$\R$grom_cpu.v:641$14_DATA[7:0]$115
10/77: $3$memwr$\R$grom_cpu.v:641$14_ADDR[1:0]$114
11/77: $5$mem2bits$\R$grom_cpu.v:305$12[7:0]$106
12/77: $5$mem2bits$\R$grom_cpu.v:312$13[7:0]$107
13/77: $4$memwr$\R$grom_cpu.v:120$11_EN[7:0]$82
14/77: $4$memwr$\R$grom_cpu.v:120$11_DATA[7:0]$81
15/77: $4$memwr$\R$grom_cpu.v:120$11_ADDR[1:0]$80
16/77: $4$mem2bits$\R$grom_cpu.v:312$13[7:0]$84
17/77: $4$mem2bits$\R$grom_cpu.v:305$12[7:0]$83
18/77: $3$mem2bits$\R$grom_cpu.v:312$13[7:0]$78
19/77: $3$mem2bits$\R$grom_cpu.v:305$12[7:0]$77
20/77: $3$memwr$\R$grom_cpu.v:120$11_EN[7:0]$76
21/77: $3$memwr$\R$grom_cpu.v:120$11_DATA[7:0]$75
22/77: $3$memwr$\R$grom_cpu.v:120$11_ADDR[1:0]$74
23/77: $2$memwr$\R$grom_cpu.v:75$10_EN[7:0]$57
24/77: $2$memwr$\R$grom_cpu.v:74$9_EN[7:0]$56
25/77: $2$memwr$\R$grom_cpu.v:73$8_EN[7:0]$55
26/77: $2$memwr$\R$grom_cpu.v:72$7_EN[7:0]$54
27/77: $2$memwr$\R$grom_cpu.v:693$16_EN[7:0]$71
28/77: $2$memwr$\R$grom_cpu.v:693$16_DATA[7:0]$70
29/77: $2$memwr$\R$grom_cpu.v:693$16_ADDR[1:0]$69
30/77: $2$memwr$\R$grom_cpu.v:683$15_EN[7:0]$68
31/77: $2$memwr$\R$grom_cpu.v:683$15_DATA[7:0]$67
32/77: $2$memwr$\R$grom_cpu.v:683$15_ADDR[1:0]$66
33/77: $2$memwr$\R$grom_cpu.v:641$14_EN[7:0]$65
34/77: $2$memwr$\R$grom_cpu.v:641$14_DATA[7:0]$64
35/77: $2$memwr$\R$grom_cpu.v:641$14_ADDR[1:0]$63
36/77: $2$mem2bits$\R$grom_cpu.v:312$13[7:0]$62
37/77: $2$mem2bits$\R$grom_cpu.v:305$12[7:0]$61
38/77: $2$memwr$\R$grom_cpu.v:120$11_EN[7:0]$60
39/77: $2$memwr$\R$grom_cpu.v:120$11_DATA[7:0]$59
40/77: $2$memwr$\R$grom_cpu.v:120$11_ADDR[1:0]$58
41/77: $2\jump[0:0]
42/77: $0\state[4:0]
43/77: $1$memwr$\R$grom_cpu.v:693$16_EN[7:0]$53
44/77: $1$memwr$\R$grom_cpu.v:693$16_DATA[7:0]$52
45/77: $1$memwr$\R$grom_cpu.v:693$16_ADDR[1:0]$51
46/77: $1$memwr$\R$grom_cpu.v:683$15_EN[7:0]$50
47/77: $1$memwr$\R$grom_cpu.v:683$15_DATA[7:0]$49
48/77: $1$memwr$\R$grom_cpu.v:683$15_ADDR[1:0]$48
49/77: $1$memwr$\R$grom_cpu.v:641$14_EN[7:0]$47
50/77: $1$memwr$\R$grom_cpu.v:641$14_DATA[7:0]$46
51/77: $1$memwr$\R$grom_cpu.v:641$14_ADDR[1:0]$45
52/77: $1$mem2bits$\R$grom_cpu.v:312$13[7:0]$44
53/77: $1$mem2bits$\R$grom_cpu.v:305$12[7:0]$43
54/77: $1$memwr$\R$grom_cpu.v:120$11_EN[7:0]$42
55/77: $1$memwr$\R$grom_cpu.v:120$11_DATA[7:0]$41
56/77: $1$memwr$\R$grom_cpu.v:120$11_ADDR[1:0]$40
57/77: $1$memwr$\R$grom_cpu.v:75$10_EN[7:0]$39
58/77: $1$memwr$\R$grom_cpu.v:74$9_EN[7:0]$38
59/77: $1$memwr$\R$grom_cpu.v:73$8_EN[7:0]$37
60/77: $1$memwr$\R$grom_cpu.v:72$7_EN[7:0]$36
61/77: $1\jump[0:0]
62/77: $0\RESULT_REG[1:0]
63/77: $0\alu_op[3:0]
64/77: $0\alu_b[7:0]
65/77: $0\alu_a[7:0]
66/77: $0\FUTURE_PC[11:0]
67/77: $0\SP[11:0]
68/77: $0\DS[3:0]
69/77: $0\CS[3:0]
70/77: $0\VALUE[7:0]
71/77: $0\IR[7:0]
72/77: $0\PC[11:0]
73/77: $0\data_out[7:0]
74/77: $0\ioreq[0:0]
75/77: $0\we[0:0]
76/77: $0\addr[11:0]
77/77: $0\hlt[0:0]
Creating decoders for process `\grom_computer.$proc$grom_computer.v:21$3'.
1/1: $0\display_out[7:0]
5.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:13$156_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:14$157_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:15$158_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:16$159_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:17$160_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:18$161_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:19$162_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:20$163_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:21$164_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:22$165_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:23$166_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:24$167_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:27$168_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:28$169_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:29$170_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
No latch inferred for signal `\ram_memory.$memwr$\store$ram_memory.v:31$171_EN' from process `\ram_memory.$proc$ram_memory.v:0$197'.
5.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ram_memory.\data_out' using process `\ram_memory.$proc$ram_memory.v:34$173'.
created $dff cell `$procdff$1841' with positive edge clock.
Creating register for signal `\ram_memory.$memwr$\store$ram_memory.v:36$172_ADDR' using process `\ram_memory.$proc$ram_memory.v:34$173'.
created $dff cell `$procdff$1842' with positive edge clock.
Creating register for signal `\ram_memory.$memwr$\store$ram_memory.v:36$172_DATA' using process `\ram_memory.$proc$ram_memory.v:34$173'.
created $dff cell `$procdff$1843' with positive edge clock.
Creating register for signal `\ram_memory.$memwr$\store$ram_memory.v:36$172_EN' using process `\ram_memory.$proc$ram_memory.v:34$173'.
created $dff cell `$procdff$1844' with positive edge clock.
Creating register for signal `\alu.\result' using process `\alu.$proc$alu.v:34$144'.
created $dff cell `$procdff$1845' with positive edge clock.
Creating register for signal `\alu.\CF' using process `\alu.$proc$alu.v:34$144'.
created $dff cell `$procdff$1846' with positive edge clock.
Creating register for signal `\alu.\ZF' using process `\alu.$proc$alu.v:34$144'.
created $dff cell `$procdff$1847' with positive edge clock.
Creating register for signal `\alu.\SF' using process `\alu.$proc$alu.v:34$144'.
created $dff cell `$procdff$1848' with positive edge clock.
Creating register for signal `\alu.\tmp' using process `\alu.$proc$alu.v:34$144'.
created $dff cell `$procdff$1849' with positive edge clock.
Creating register for signal `\grom_cpu.\hlt' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1850' with positive edge clock.
Creating register for signal `\grom_cpu.\addr' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1851' with positive edge clock.
Creating register for signal `\grom_cpu.\we' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1852' with positive edge clock.
Creating register for signal `\grom_cpu.\ioreq' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1853' with positive edge clock.
Creating register for signal `\grom_cpu.\data_out' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1854' with positive edge clock.
Creating register for signal `\grom_cpu.\PC' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1855' with positive edge clock.
Creating register for signal `\grom_cpu.\IR' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1856' with positive edge clock.
Creating register for signal `\grom_cpu.\VALUE' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1857' with positive edge clock.
Creating register for signal `\grom_cpu.\CS' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1858' with positive edge clock.
Creating register for signal `\grom_cpu.\DS' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1859' with positive edge clock.
Creating register for signal `\grom_cpu.\SP' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1860' with positive edge clock.
Creating register for signal `\grom_cpu.\FUTURE_PC' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1861' with positive edge clock.
Creating register for signal `\grom_cpu.\state' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1862' with positive edge clock.
Creating register for signal `\grom_cpu.\alu_a' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1863' with positive edge clock.
Creating register for signal `\grom_cpu.\alu_b' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1864' with positive edge clock.
Creating register for signal `\grom_cpu.\alu_op' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1865' with positive edge clock.
Creating register for signal `\grom_cpu.\RESULT_REG' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1866' with positive edge clock.
Creating register for signal `\grom_cpu.\jump' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1867' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:72$7_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1868' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:73$8_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1869' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:74$9_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1870' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:75$10_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1871' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:120$11_ADDR' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1872' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:120$11_DATA' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1873' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:120$11_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1874' with positive edge clock.
Creating register for signal `\grom_cpu.$mem2bits$\R$grom_cpu.v:305$12' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1875' with positive edge clock.
Creating register for signal `\grom_cpu.$mem2bits$\R$grom_cpu.v:312$13' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1876' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:641$14_ADDR' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1877' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:641$14_DATA' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1878' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:641$14_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1879' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:683$15_ADDR' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1880' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:683$15_DATA' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1881' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:683$15_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1882' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:693$16_ADDR' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1883' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:693$16_DATA' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1884' with positive edge clock.
Creating register for signal `\grom_cpu.$memwr$\R$grom_cpu.v:693$16_EN' using process `\grom_cpu.$proc$grom_cpu.v:56$17'.
created $dff cell `$procdff$1885' with positive edge clock.
Creating register for signal `\grom_computer.\display_out' using process `\grom_computer.$proc$grom_computer.v:21$3'.
created $dff cell `$procdff$1886' with positive edge clock.
5.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
5.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `ram_memory.$proc$ram_memory.v:0$197'.
Found and cleaned up 1 empty switch in `\ram_memory.$proc$ram_memory.v:34$173'.
Removing empty process `ram_memory.$proc$ram_memory.v:34$173'.
Found and cleaned up 1 empty switch in `\alu.$proc$alu.v:34$144'.
Removing empty process `alu.$proc$alu.v:34$144'.
Removing empty process `grom_cpu.$proc$grom_cpu.v:40$143'.
Found and cleaned up 18 empty switches in `\grom_cpu.$proc$grom_cpu.v:56$17'.
Removing empty process `grom_cpu.$proc$grom_cpu.v:56$17'.
Found and cleaned up 1 empty switch in `\grom_computer.$proc$grom_computer.v:21$3'.
Removing empty process `grom_computer.$proc$grom_computer.v:21$3'.
Cleaned up 21 empty switches.
5.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module ram_memory.
Optimizing module alu.
<suppressed ~2 debug messages>
Optimizing module grom_cpu.
<suppressed ~81 debug messages>
Optimizing module grom_computer.
<suppressed ~2 debug messages>
5.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module ram_memory.
Optimizing module alu.
Optimizing module grom_cpu.
Optimizing module grom_computer.
5.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ram_memory..
Finding unused cells or wires in module \alu..
Finding unused cells or wires in module \grom_cpu..
Finding unused cells or wires in module \grom_computer..
Removed 112 unused cells and 401 unused wires.
<suppressed ~118 debug messages>
5.5. Executing CHECK pass (checking for obvious problems).
Checking module alu...
Checking module grom_computer...
Checking module grom_cpu...
Checking module ram_memory...
Found and reported 0 problems.
5.6. Executing OPT pass (performing simple optimizations).
5.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module alu.
Optimizing module grom_computer.
Optimizing module grom_cpu.
Optimizing module ram_memory.
5.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\alu'.
<suppressed ~6 debug messages>
Finding identical cells in module `\grom_computer'.
Finding identical cells in module `\grom_cpu'.
<suppressed ~789 debug messages>
Finding identical cells in module `\ram_memory'.
Removed a total of 265 cells.
5.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \alu..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \grom_computer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \grom_cpu..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 1/2 on $mux $procmux$1007.
dead port 1/2 on $mux $procmux$1023.
dead port 1/2 on $mux $procmux$1039.
dead port 1/2 on $mux $procmux$1096.
dead port 1/2 on $mux $procmux$1115.
dead port 2/2 on $mux $procmux$259.
dead port 2/2 on $mux $procmux$261.
dead port 1/2 on $mux $procmux$264.
dead port 2/2 on $mux $procmux$282.
dead port 2/2 on $mux $procmux$284.
dead port 1/2 on $mux $procmux$1134.
dead port 1/2 on $mux $procmux$287.
dead port 2/2 on $mux $procmux$305.
dead port 2/2 on $mux $procmux$307.
dead port 1/2 on $mux $procmux$310.
dead port 2/2 on $mux $procmux$459.
dead port 1/2 on $mux $procmux$462.
dead port 2/2 on $mux $procmux$477.
dead port 1/2 on $mux $procmux$480.
dead port 2/2 on $mux $procmux$495.
dead port 1/2 on $mux $procmux$498.
dead port 1/2 on $mux $procmux$582.
dead port 2/2 on $mux $procmux$584.
dead port 1/2 on $mux $procmux$587.
dead port 1/2 on $mux $procmux$613.
dead port 2/2 on $mux $procmux$615.
dead port 1/2 on $mux $procmux$618.
dead port 1/2 on $mux $procmux$644.
dead port 2/2 on $mux $procmux$646.
dead port 1/2 on $mux $procmux$649.
dead port 2/2 on $mux $procmux$774.
dead port 1/2 on $mux $procmux$777.
dead port 2/2 on $mux $procmux$796.
dead port 1/2 on $mux $procmux$799.
dead port 2/2 on $mux $procmux$818.
dead port 1/2 on $mux $procmux$821.
dead port 1/2 on $mux $procmux$844.
dead port 1/2 on $mux $procmux$867.
dead port 1/2 on $mux $procmux$890.
dead port 1/2 on $mux $procmux$913.
dead port 1/2 on $mux $procmux$925.
dead port 1/2 on $mux $procmux$937.
dead port 1/2 on $mux $procmux$949.
dead port 1/2 on $mux $procmux$963.
dead port 1/2 on $mux $procmux$977.
dead port 1/2 on $mux $procmux$991.
Running muxtree optimizer on module \ram_memory..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 46 multiplexer ports.
<suppressed ~41 debug messages>
5.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \alu.
New ctrl vector for $pmux cell $procmux$226: { $procmux$242_CMP $procmux$241_CMP $procmux$240_CMP $procmux$239_CMP $procmux$238_CMP $procmux$237_CMP $procmux$236_CMP $procmux$235_CMP $procmux$233_CMP $auto$opt_reduce.cc:134:opt_pmux$1897 $procmux$231_CMP $procmux$230_CMP $procmux$229_CMP $procmux$228_CMP $procmux$227_CMP }
Optimizing cells in module \alu.
Optimizing cells in module \grom_computer.
Optimizing cells in module \grom_cpu.
New ctrl vector for $pmux cell $procmux$1663: { $procmux$1181_CMP $auto$opt_reduce.cc:134:opt_pmux$1901 $auto$opt_reduce.cc:134:opt_pmux$1899 $procmux$1167_CMP }
New ctrl vector for $pmux cell $procmux$1683: $auto$opt_reduce.cc:134:opt_pmux$1903
New ctrl vector for $pmux cell $procmux$1687: { $procmux$1175_CMP $auto$opt_reduce.cc:134:opt_pmux$1905 $procmux$1167_CMP }
New ctrl vector for $pmux cell $procmux$1706: { $procmux$1094_CMP $procmux$1005_CMP $procmux$1158_CMP $auto$opt_reduce.cc:134:opt_pmux$1907 }
New ctrl vector for $pmux cell $procmux$1715: { $procmux$1181_CMP $auto$opt_reduce.cc:134:opt_pmux$1911 $auto$opt_reduce.cc:134:opt_pmux$1909 $procmux$1167_CMP }
New ctrl vector for $pmux cell $procmux$1299: { $auto$opt_reduce.cc:134:opt_pmux$1913 $procmux$1176_CMP $procmux$1175_CMP $procmux$1174_CMP }
New ctrl vector for $pmux cell $procmux$1735: $auto$opt_reduce.cc:134:opt_pmux$1915
New ctrl vector for $pmux cell $procmux$1340: { $procmux$1165_CMP $auto$opt_reduce.cc:134:opt_pmux$1917 $procmux$1162_CMP }
New ctrl vector for $pmux cell $procmux$1765: $auto$opt_reduce.cc:134:opt_pmux$1919
New ctrl vector for $pmux cell $procmux$1768: { $procmux$1181_CMP $procmux$1178_CMP $procmux$1177_CMP $auto$opt_reduce.cc:134:opt_pmux$1921 $procmux$1167_CMP }
New ctrl vector for $pmux cell $procmux$1374: { $auto$opt_reduce.cc:134:opt_pmux$1923 $procmux$1176_CMP }
New ctrl vector for $pmux cell $procmux$1788: $auto$opt_reduce.cc:134:opt_pmux$1925
New ctrl vector for $pmux cell $procmux$1406: { $auto$opt_reduce.cc:134:opt_pmux$1927 $procmux$1176_CMP $procmux$1175_CMP }
New ctrl vector for $pmux cell $procmux$254: { $procmux$1165_CMP $auto$opt_reduce.cc:134:opt_pmux$1929 }
New ctrl vector for $pmux cell $procmux$1185: { $procmux$1170_CMP $auto$opt_reduce.cc:134:opt_pmux$1931 }
New ctrl vector for $pmux cell $procmux$1153: { $procmux$1216_CMP $procmux$1215_CMP $procmux$1214_CMP $procmux$1094_CMP $procmux$1184_CMP $procmux$1183_CMP $procmux$1005_CMP $procmux$1160_CMP $procmux$1159_CMP $procmux$1157_CMP $procmux$1156_CMP $procmux$1155_CMP $auto$opt_reduce.cc:134:opt_pmux$1933 }
New ctrl vector for $pmux cell $procmux$1453: $auto$opt_reduce.cc:134:opt_pmux$1935
New ctrl vector for $pmux cell $procmux$1161: { $procmux$1164_CMP $auto$opt_reduce.cc:134:opt_pmux$1937 }
New ctrl vector for $pmux cell $procmux$450: { $auto$opt_reduce.cc:134:opt_pmux$1939 $procmux$1167_CMP }
New ctrl vector for $pmux cell $procmux$1190: { $auto$opt_reduce.cc:134:opt_pmux$1941 $procmux$1162_CMP }
New ctrl vector for $pmux cell $procmux$1166: { $procmux$1177_CMP $procmux$1175_CMP $auto$opt_reduce.cc:134:opt_pmux$1943 $procmux$1173_CMP $procmux$1167_CMP }
Consolidated identical input bits for $pmux cell $procmux$572:
Old ports: A=8'x, B=64'1111111100000000000000000000000000000000000000000000000000000000, Y=$procmux$572_Y
New ports: A=1'x, B=8'10000000, Y=$procmux$572_Y [0]
New connections: $procmux$572_Y [7:1] = { $procmux$572_Y [0] $procmux$572_Y [0] $procmux$572_Y [0] $procmux$572_Y [0] $procmux$572_Y [0] $procmux$572_Y [0] $procmux$572_Y [0] }
New ctrl vector for $pmux cell $procmux$572: { $procmux$1181_CMP $auto$opt_reduce.cc:134:opt_pmux$1945 }
New ctrl vector for $pmux cell $procmux$1168: $auto$opt_reduce.cc:134:opt_pmux$1947
New ctrl vector for $pmux cell $procmux$1195: { $auto$opt_reduce.cc:134:opt_pmux$1951 $procmux$1176_CMP $procmux$1175_CMP $procmux$1174_CMP $auto$opt_reduce.cc:134:opt_pmux$1949 $procmux$1167_CMP }
Consolidated identical input bits for $mux cell $procmux$841:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$841_Y
New ports: A=1'0, B=1'1, Y=$procmux$841_Y [0]
New connections: $procmux$841_Y [7:1] = { $procmux$841_Y [0] $procmux$841_Y [0] $procmux$841_Y [0] $procmux$841_Y [0] $procmux$841_Y [0] $procmux$841_Y [0] $procmux$841_Y [0] }
Consolidated identical input bits for $mux cell $procmux$864:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$864_Y
New ports: A=1'0, B=1'1, Y=$procmux$864_Y [0]
New connections: $procmux$864_Y [7:1] = { $procmux$864_Y [0] $procmux$864_Y [0] $procmux$864_Y [0] $procmux$864_Y [0] $procmux$864_Y [0] $procmux$864_Y [0] $procmux$864_Y [0] }
Consolidated identical input bits for $mux cell $procmux$887:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$887_Y
New ports: A=1'0, B=1'1, Y=$procmux$887_Y [0]
New connections: $procmux$887_Y [7:1] = { $procmux$887_Y [0] $procmux$887_Y [0] $procmux$887_Y [0] $procmux$887_Y [0] $procmux$887_Y [0] $procmux$887_Y [0] $procmux$887_Y [0] }
Consolidated identical input bits for $mux cell $procmux$910:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$910_Y
New ports: A=1'0, B=1'1, Y=$procmux$910_Y [0]
New connections: $procmux$910_Y [7:1] = { $procmux$910_Y [0] $procmux$910_Y [0] $procmux$910_Y [0] $procmux$910_Y [0] $procmux$910_Y [0] $procmux$910_Y [0] $procmux$910_Y [0] }
Consolidated identical input bits for $mux cell $procmux$922:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$922_Y
New ports: A=1'0, B=1'1, Y=$procmux$922_Y [0]
New connections: $procmux$922_Y [7:1] = { $procmux$922_Y [0] $procmux$922_Y [0] $procmux$922_Y [0] $procmux$922_Y [0] $procmux$922_Y [0] $procmux$922_Y [0] $procmux$922_Y [0] }
New ctrl vector for $pmux cell $procmux$1656: { $procmux$1094_CMP $procmux$1005_CMP $auto$opt_reduce.cc:134:opt_pmux$1953 }
Consolidated identical input bits for $mux cell $procmux$960:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$960_Y
New ports: A=1'0, B=1'1, Y=$procmux$960_Y [0]
New connections: $procmux$960_Y [7:1] = { $procmux$960_Y [0] $procmux$960_Y [0] $procmux$960_Y [0] $procmux$960_Y [0] $procmux$960_Y [0] $procmux$960_Y [0] $procmux$960_Y [0] }
New ctrl vector for $pmux cell $procmux$1660: $auto$opt_reduce.cc:134:opt_pmux$1955
Optimizing cells in module \grom_cpu.
Consolidated identical input bits for $mux cell $procmux$1221:
Old ports: A=$2$memwr$\R$grom_cpu.v:693$16_EN[7:0]$71, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35
New ports: A=$procmux$922_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0]
New connections: $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [7:1] = { $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] $0$memwr$\R$grom_cpu.v:693$16_EN[7:0]$35 [0] }
Consolidated identical input bits for $mux cell $procmux$1230:
Old ports: A=$2$memwr$\R$grom_cpu.v:683$15_EN[7:0]$68, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32
New ports: A=$procmux$960_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0]
New connections: $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [7:1] = { $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] $0$memwr$\R$grom_cpu.v:683$15_EN[7:0]$32 [0] }
Consolidated identical input bits for $mux cell $procmux$1263:
Old ports: A=$2$memwr$\R$grom_cpu.v:75$10_EN[7:0]$57, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21
New ports: A=$procmux$841_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0]
New connections: $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [7:1] = { $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] $0$memwr$\R$grom_cpu.v:75$10_EN[7:0]$21 [0] }
Consolidated identical input bits for $mux cell $procmux$1266:
Old ports: A=$2$memwr$\R$grom_cpu.v:74$9_EN[7:0]$56, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20
New ports: A=$procmux$864_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0]
New connections: $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [7:1] = { $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] $0$memwr$\R$grom_cpu.v:74$9_EN[7:0]$20 [0] }
Consolidated identical input bits for $mux cell $procmux$1269:
Old ports: A=$2$memwr$\R$grom_cpu.v:73$8_EN[7:0]$55, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19
New ports: A=$procmux$887_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0]
New connections: $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [7:1] = { $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] $0$memwr$\R$grom_cpu.v:73$8_EN[7:0]$19 [0] }
Consolidated identical input bits for $mux cell $procmux$1272:
Old ports: A=$2$memwr$\R$grom_cpu.v:72$7_EN[7:0]$54, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18
New ports: A=$procmux$910_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0]
New connections: $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [7:1] = { $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] $0$memwr$\R$grom_cpu.v:72$7_EN[7:0]$18 [0] }
Consolidated identical input bits for $mux cell $procmux$772:
Old ports: A=$4$memwr$\R$grom_cpu.v:120$11_EN[7:0]$82, B=8'00000000, Y=$procmux$772_Y
New ports: A=$procmux$572_Y [0], B=1'0, Y=$procmux$772_Y [0]
New connections: $procmux$772_Y [7:1] = { $procmux$772_Y [0] $procmux$772_Y [0] $procmux$772_Y [0] $procmux$772_Y [0] $procmux$772_Y [0] $procmux$772_Y [0] $procmux$772_Y [0] }
Optimizing cells in module \grom_cpu.
Consolidated identical input bits for $mux cell $procmux$1093:
Old ports: A=8'00000000, B=$3$memwr$\R$grom_cpu.v:120$11_EN[7:0]$76, Y=$procmux$1093_Y
New ports: A=1'0, B=$procmux$772_Y [0], Y=$procmux$1093_Y [0]
New connections: $procmux$1093_Y [7:1] = { $procmux$1093_Y [0] $procmux$1093_Y [0] $procmux$1093_Y [0] $procmux$1093_Y [0] $procmux$1093_Y [0] $procmux$1093_Y [0] $procmux$1093_Y [0] }
Optimizing cells in module \grom_cpu.
Consolidated identical input bits for $mux cell $procmux$1254:
Old ports: A=$2$memwr$\R$grom_cpu.v:120$11_EN[7:0]$60, B=8'00000000, Y=$0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24
New ports: A=$procmux$1093_Y [0], B=1'0, Y=$0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0]
New connections: $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [7:1] = { $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] $0$memwr$\R$grom_cpu.v:120$11_EN[7:0]$24 [0] }
Optimizing cells in module \grom_cpu.
Optimizing cells in module \ram_memory.
Consolidated identical input bits for $mux cell $procmux$215:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176
New ports: A=1'0, B=1'1, Y=$0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0]
New connections: $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [7:1] = { $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] $0$memwr$\store$ram_memory.v:36$172_EN[7:0]$176 [0] }
Optimizing cells in module \ram_memory.
Performed a total of 44 changes.
5.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\alu'.
Finding identical cells in module `\grom_computer'.
Finding identical cells in module `\grom_cpu'.
<suppressed ~51 debug messages>
Finding identical cells in module `\ram_memory'.
Removed a total of 17 cells.
5.6.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \alu..
Finding unused cells or wires in module \grom_computer..
Finding unused cells or wires in module \grom_cpu..
Finding unused cells or wires in module \ram_memory..
Removed 0 unused cells and 328 unused wires.
<suppressed ~2 debug messages>
5.6.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module alu.
Optimizing module grom_computer.
Optimizing module grom_cpu.
Optimizing module ram_memory.
5.6.8. Rerunning OPT passes. (Maybe there is more to do..)
5.6.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \alu..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \grom_computer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \grom_cpu..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \ram_memory..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~39 debug messages>
5.6.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \alu.
Optimizing cells in module \grom_computer.
Optimizing cells in module \grom_cpu.
Optimizing cells in module \ram_memory.
Performed a total of 0 changes.
5.6.11. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\alu'.
Finding identical cells in module `\grom_computer'.
Finding identical cells in module `\grom_cpu'.
Finding identical cells in module `\ram_memory'.
Removed a total of 0 cells.
5.6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \alu..
Finding unused cells or wires in module \grom_computer..
Finding unused cells or wires in module \grom_cpu..
Finding unused cells or wires in module \ram_memory..
5.6.13. Executing OPT_EXPR pass (perform const folding).
Optimizing module alu.
Optimizing module grom_computer.
Optimizing module grom_cpu.
Optimizing module ram_memory.
5.6.14. Finished OPT passes. (There is nothing left to do.)
5.7. Executing WREDUCE pass (reducing word size of cells).
Removed top 8 bits (of 9) from port B of cell alu.$add$alu.v:42$148 ($add).
Removed top 8 bits (of 9) from port B of cell alu.$sub$alu.v:44$150 ($sub).
Removed top 1 bits (of 4) from port B of cell alu.$procmux$235_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell alu.$procmux$236_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell alu.$procmux$237_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell alu.$procmux$238_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell alu.$procmux$239_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell alu.$procmux$240_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell alu.$procmux$241_CMP0 ($eq).
Removed top 30 address bits (of 32) from memory init port grom_cpu.$auto$proc_memwr.cc:45:proc_memwr$1888 (R).
Removed top 30 address bits (of 32) from memory init port grom_cpu.$auto$proc_memwr.cc:45:proc_memwr$1889 (R).
Removed top 30 address bits (of 32) from memory init port grom_cpu.$auto$proc_memwr.cc:45:proc_memwr$1890 (R).
Removed top 30 address bits (of 32) from memory init port grom_cpu.$auto$proc_memwr.cc:45:proc_memwr$1891 (R).
Removed top 30 address bits (of 32) from memory read port grom_cpu.$memrd$\R$grom_cpu.v:125$86 (R).
Removed top 3 bits (of 5) from mux cell grom_cpu.$ternary$grom_cpu.v:91$72 ($mux).
Removed top 31 bits (of 32) from port B of cell grom_cpu.$add$grom_cpu.v:110$79 ($add).
Removed top 20 bits (of 32) from port Y of cell grom_cpu.$add$grom_cpu.v:110$79 ($add).
Removed top 1 bits (of 5) from mux cell grom_cpu.$ternary$grom_cpu.v:177$90 ($mux).
Removed top 31 bits (of 32) from port B of cell grom_cpu.$sub$grom_cpu.v:259$100 ($sub).
Removed top 20 bits (of 32) from port Y of cell grom_cpu.$sub$grom_cpu.v:259$100 ($sub).
Removed top 31 bits (of 32) from port B of cell grom_cpu.$add$grom_cpu.v:267$101 ($add).
Removed top 20 bits (of 32) from port Y of cell grom_cpu.$add$grom_cpu.v:267$101 ($add).
Removed top 1 bits (of 3) from port B of cell grom_cpu.$procmux$335_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell grom_cpu.$procmux$336_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell grom_cpu.$procmux$337_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$923_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell grom_cpu.$procmux$1005_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell grom_cpu.$procmux$1094_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1156_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1157_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1158_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1159_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1160_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell grom_cpu.$procmux$1164_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell grom_cpu.$procmux$1171_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell grom_cpu.$procmux$1176_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell grom_cpu.$procmux$1177_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell grom_cpu.$procmux$1178_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell grom_cpu.$procmux$1183_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell grom_cpu.$procmux$1184_CMP0 ($eq).
Removed top 1 bits (of 5) from mux cell grom_cpu.$procmux$1200 ($mux).
Removed top 1 bits (of 5) from mux cell grom_cpu.$procmux$1203 ($mux).
Removed top 3 bits (of 5) from port B of cell grom_cpu.$procmux$1214_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell grom_cpu.$procmux$1215_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell grom_cpu.$procmux$1216_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1587_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell grom_cpu.$procmux$1710_CMP0 ($eq).
Removed top 20 bits (of 32) from wire grom_cpu.$add$grom_cpu.v:110$79_Y.
Removed top 1 bits (of 5) from wire grom_cpu.$procmux$1200_Y.
Removed top 1 bits (of 5) from wire grom_cpu.$procmux$1203_Y.
Removed top 3 bits (of 5) from wire grom_cpu.$ternary$grom_cpu.v:91$72_Y.
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:13$181 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:14$182 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:15$183 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:16$184 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:17$185 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:18$186 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:19$187 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:20$188 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:21$189 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:22$190 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:23$191 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:24$192 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:27$193 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:28$194 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:29$195 (store).
Removed top 20 address bits (of 32) from memory init port ram_memory.$meminit$\store$ram_memory.v:31$196 (store).
5.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \alu..
Finding unused cells or wires in module \grom_computer..
Finding unused cells or wires in module \grom_cpu..
Finding unused cells or wires in module \ram_memory..
Removed 0 unused cells and 4 unused wires.
<suppressed ~1 debug messages>
5.9. Executing MEMORY_COLLECT pass (generating $mem cells).
5.10. Executing OPT pass (performing simple optimizations).
5.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module alu.
Optimizing module grom_computer.
Optimizing module grom_cpu.
Optimizing module ram_memory.
5.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\alu'.
Finding identical cells in module `\grom_computer'.
Finding identical cells in module `\grom_cpu'.
Finding identical cells in module `\ram_memory'.
Removed a total of 0 cells.
5.10.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \alu..
Finding unused cells or wires in module \grom_computer..
Finding unused cells or wires in module \grom_cpu..
Finding unused cells or wires in module \ram_memory..
5.10.4. Finished fast OPT passes.
5.11. Printing statistics.
=== alu ===
Number of wires: 37
Number of wire bits: 128
Number of public wires: 8
Number of public wire bits: 32
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 31
$add 2
$and 1
$dff 4
$eq 15
$logic_not 2
$not 1
$or 1
$pmux 1
$reduce_or 1
$sub 2
$xor 1
=== grom_computer ===
Number of wires: 13
Number of wire bits: 52
Number of public wires: 10
Number of public wire bits: 42
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 7
$and 1
$dff 1
$logic_and 1
$mux 1
$not 1
grom_cpu 1
ram_memory 1
=== grom_cpu ===
Number of wires: 276
Number of wire bits: 1362
Number of public wires: 24
Number of public wire bits: 131
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 268
$add 3
$dff 17
$eq 37
$logic_not 5
$mem_v2 1
$mux 137
$not 3
$or 1
$pmux 43
$reduce_or 19
$sub 1
alu 1
=== ram_memory ===
Number of wires: 10
Number of wire bits: 74
Number of public wires: 5
Number of public wire bits: 30
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 6
$dff 1
$mem_v2 1
$mux 4
=== design hierarchy ===
grom_computer 1
grom_cpu 1
alu 1
ram_memory 1
Number of wires: 336
Number of wire bits: 1616
Number of public wires: 47
Number of public wire bits: 235
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 309
$add 5
$and 2
$dff 23
$eq 52
$logic_and 1
$logic_not 7
$mem_v2 2
$mux 142
$not 5
$or 2
$pmux 44
$reduce_or 20
$sub 3
$xor 1
5.12. Executing CHECK pass (checking for obvious problems).
Checking module alu...
Checking module grom_computer...
Checking module grom_cpu...
Checking module ram_memory...
Found and reported 0 problems.
6. Executing SIM pass (simulate the circuit).
Simulating cycle 0.
Simulating cycle 1.
Simulating cycle 2.
Simulating cycle 3.
Simulating cycle 4.
Simulating cycle 5.
Simulating cycle 6.
Simulating cycle 7.
Simulating cycle 8.
Simulating cycle 9.
Simulating cycle 10.
Simulating cycle 11.
Simulating cycle 12.
Simulating cycle 13.
Simulating cycle 14.
Simulating cycle 15.
Simulating cycle 16.
Simulating cycle 17.
Simulating cycle 18.
Simulating cycle 19.
Simulating cycle 20.
Simulating cycle 21.
Simulating cycle 22.
Simulating cycle 23.
Simulating cycle 24.
Simulating cycle 25.
Simulating cycle 26.
Simulating cycle 27.
Simulating cycle 28.
Simulating cycle 29.
Simulating cycle 30.
Simulating cycle 31.
Simulating cycle 32.
Simulating cycle 33.
Simulating cycle 34.
Simulating cycle 35.
Simulating cycle 36.
Simulating cycle 37.
Simulating cycle 38.
Simulating cycle 39.
Simulating cycle 40.
Simulating cycle 41.
Simulating cycle 42.
Simulating cycle 43.
Simulating cycle 44.
Simulating cycle 45.
Simulating cycle 46.
Simulating cycle 47.
Simulating cycle 48.
Simulating cycle 49.
Simulating cycle 50.
Simulating cycle 51.
Simulating cycle 52.
Simulating cycle 53.
Simulating cycle 54.
Simulating cycle 55.
Simulating cycle 56.
Simulating cycle 57.
Simulating cycle 58.
Simulating cycle 59.
Simulating cycle 60.
Simulating cycle 61.
Simulating cycle 62.
Simulating cycle 63.
Simulating cycle 64.
Simulating cycle 65.
Simulating cycle 66.
Simulating cycle 67.
Simulating cycle 68.
Simulating cycle 69.
Simulating cycle 70.
Simulating cycle 71.
Simulating cycle 72.
Simulating cycle 73.
Simulating cycle 74.
Simulating cycle 75.
Simulating cycle 76.
Simulating cycle 77.
Simulating cycle 78.
Simulating cycle 79.
Simulating cycle 80.
Simulating cycle 81.
Simulating cycle 82.
Simulating cycle 83.
Simulating cycle 84.
Simulating cycle 85.
Simulating cycle 86.
Simulating cycle 87.
Simulating cycle 88.
Simulating cycle 89.
Simulating cycle 90.
Simulating cycle 91.
Simulating cycle 92.
Simulating cycle 93.
Simulating cycle 94.
Simulating cycle 95.
Simulating cycle 96.
Simulating cycle 97.
Simulating cycle 98.
Simulating cycle 99.
Simulating cycle 100.
Simulating cycle 101.
Simulating cycle 102.
Simulating cycle 103.
Simulating cycle 104.
Simulating cycle 105.
Simulating cycle 106.
Simulating cycle 107.
Simulating cycle 108.
Simulating cycle 109.
Simulating cycle 110.
Simulating cycle 111.
Simulating cycle 112.
Simulating cycle 113.
Simulating cycle 114.
Simulating cycle 115.
Simulating cycle 116.
Simulating cycle 117.
Simulating cycle 118.
Simulating cycle 119.
Simulating cycle 120.
Simulating cycle 121.
Simulating cycle 122.
Simulating cycle 123.
Simulating cycle 124.
Simulating cycle 125.
Simulating cycle 126.
Simulating cycle 127.
Simulating cycle 128.
Simulating cycle 129.
Simulating cycle 130.
Simulating cycle 131.
Simulating cycle 132.
Simulating cycle 133.
Simulating cycle 134.
Simulating cycle 135.
Simulating cycle 136.
Simulating cycle 137.
Simulating cycle 138.
Simulating cycle 139.
Simulating cycle 140.
Simulating cycle 141.
Simulating cycle 142.
Simulating cycle 143.
Simulating cycle 144.
Simulating cycle 145.
Simulating cycle 146.
Simulating cycle 147.
Simulating cycle 148.
Simulating cycle 149.
Simulating cycle 150.
Simulating cycle 151.
Simulating cycle 152.
Simulating cycle 153.
Simulating cycle 154.
Simulating cycle 155.
Simulating cycle 156.
Simulating cycle 157.
Simulating cycle 158.
Simulating cycle 159.
Simulating cycle 160.
7. Executing SIM pass (simulate the circuit).
ERROR: Error opening 'grom.fst' as FST file
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment