gistfile1.txt

diff --git a/lab001/base.py b/lab001/base.py
index d49106f..3467115 100644
--- a/lab001/base.py
+++ b/lab001/base.py
@@ -7,24 +7,25 @@ from migen.build.xilinx import XilinxPlatform
 #

 _io = [
-    ("user_led",  0, Pins("H17"), IOStandard("LVCMOS33")),
+    ("user_led",  0, Pins("P19"), IOStandard("LVCMOS33")), # LED<1>
+    ("user_led2",  0, Pins("P18"), IOStandard("LVCMOS33")), # LED<2>

-    ("user_sw",  0, Pins("J15"), IOStandard("LVCMOS33")),
+    ("user_sw",  0, Pins("P29"), IOStandard("LVCMOS33")), # DIP<0>

-    ("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")),
+    ("user_btn", 0, Pins("P24"), IOStandard("LVCMOS33")), # PUSH<1>

-    ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
+    ("clk50", 0, Pins("P184"), IOStandard("LVCMOS33")), # CLK

-    ("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
+    ("cpu_reset", 0, Pins("P24"), IOStandard("LVCMOS33")), # PUSH<2>
 ]


 class Platform(XilinxPlatform):
-    default_clk_name = "clk100"
-    default_clk_period = 10.0
+    default_clk_name = "clk50"
+    default_clk_period = 20.0

     def __init__(self):
-        XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
+        XilinxPlatform.__init__(self, "xc3s400-pq208-4", _io, toolchain="ise")

     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
@@ -37,6 +38,8 @@ class Platform(XilinxPlatform):
 # create our platform (fpga interface)
 platform = Platform()
 led = platform.request("user_led")
+btn = platform.request("user_btn")
+led2 = platform.request("user_led2")

 # create our module (fpga description)
 module = Module()
@@ -46,8 +49,9 @@ counter = Signal(26)
 module.comb += led.eq(counter[25])
 module.sync += counter.eq(counter + 1)

+module.comb += led2.eq(btn)
 #
 # build
 #

-platform.build(module)
\ No newline at end of file
+platform.build(module)