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Dark4Codrutz/intel-FeatureTestControl.txt

Last active September 16, 2022 09:20
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some thoughts on the bits making the featuretestcontrol
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intel-FeatureTestControl.txt
from driver inf there is the description, but not in (any?) order:
CxSR, FBC, BLC, DPST, DRRS, RC6, BLC DDI, Turbo, PSR, DFPS, ADT
where each one is rapresented by a bit in the registry, where u find it as hex DWORD.
For example MS Surface driver (9240) vs Intel generic driver (8200) :
1001 0010 0100 0000 Enable CxSR, FBC, BLC, DPST, DRRS, RC6, BLC DDI, Turbo, PSR, DFPS, ADT
1000 0010 0000 0000
For now I only know that bit4 is for DPST, where setting 0 enables the feature, 1 disables it.
@Dark4Codrutz
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Other values with inf comment:
1111 1000 0000 0000‬ Enable FBC, GSV, RC6, DPS, DPST5, Vista Backlight Control, GPMT, Turbo
0110 0000 0000 0000 Disable FBC and DFGT‬
1111 1000 0001 0000‬ Enable FBC, GSV, RC6, DPS, DPST5, Vista Backlight Control, GPMT, Turbo
0010 0000 0000 0000‬ Disable GPMT
0011 0110 0000 0000 Disable GPMT, DDI, ADB, DRRST

@Dark4Codrutz
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Dark4Codrutz commented Jun 26, 2019 •
edited

Might just be platform specific, as confronting the bit values from one to the other some don't make sense. ---> making it even more harder to pin each features bit position

@OneLeBaiLe
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bit 11 for PSR

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