Practicals on LOGISIM and TASM.
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Details and Features of 8086 microprocessor
- enhanced v of 8085 developed by Intek in 1976
- 16-bit microPro
- 20 address lines
- 16 data lines
- 1mb storage and powerful set of instructions(multiply , divide)
- 40pin IC
- Operating Voltage is +5v
- Operating Frequency 5MHz
- Instruction Queue stores 6 instruction bytes , for faster processing
- 29,000 transistors
- 256 vector interepts
- Support up to 64K I/O ports
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Architecture
- Divided intro 2 Parts for Faster Processing
- BIU : Bus Interface Unit
- Fetch instructions/data from memory
- Write Data to Memory and Ports
- Handles all transfers of data and addresses on the buses for the EU
- EU : Execution Unit
- decodes and execute instrutions
- tells BUI where to fetch instructions from
- BIU : Bus Interface Unit
- Divided intro 2 Parts for Faster Processing
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Pin Functions
- AD0 - AD15 : Address Data Bus, Low Order Addr Bus
- A16 - AD19 : High Order Addr Bus
- S0 , S1 , S2 : Status Pins
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Memory segmentation
- Has 4 16-bit special purpose registers
- Code Segment: addressing memory location in the code segment of the memory, where the executable program is stored
- Data Segment: points to the data segment of the memory where the data is stored
- Stack Segment: used to store Stack Segment
- Extra Segment: refers to a segment in the memory which is another data segment in the memory
- Has 4 16-bit special purpose registers
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Memory banking
- used to access two consecutive memory locations in one cycle divided in 2 parts
Even Bank
andOdd Bank
- Even Bank: contains even address , gives lower bytes
- Odd Bank: contains odd address , gives higher bytes
- used to access two consecutive memory locations in one cycle divided in 2 parts
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Minimum Mode Operation
- In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX' pin to logic1
- All the control signals are given out by the microprocessor chip itself.
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Maximum Mode Operation
- In maximum mode, the 8086 is operated by strapping the MN/MX’ pin to ground
- There may be more than one microprocessor in the system configuration
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8288 bus controller
- generate relevant signals for interfacing memory / IO devices in Max. Mode
- Necesary control signals are generated by 8288
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Demultimplexing of AD0-A19/S6
- Process of Seperating Address and data pins AD0-AD15 , A16/S3 - A19/S6
- ALE (Address Latch Enable) is used for this process
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8284 clock generator
- provides a stable clock to the processor
- syncZn of mutiple clock signals
- resetting to the processor along with clock signals
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Assembler directives
- instruct the assembler to perform instructions
- define symbol values
- reserve and initialize storage spaces
ASSUME
: segment name to the assembler , ASSUME CS:codeDB (Define Byte)
: define a 1byte variable , SUM DB 0DW (Define Word)
: allocate 2bytesDD (Double Word)
: store 4bytesDQ (Quad Word)
: stores 8bytesDT (Ten Bytes)
: 10 bytes
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Registers
- Are temporary Data Storage build for CPU
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General Data Registers
- AX : accumulator, and preferred for most operations.
- BX : base register, typically used to hold the address of a procedure or variable.
- CX : count register, typically used for looping.
- DX : data register, typically used for multiplication and division.
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Segment Registers
- Code Segment: addressing memory location in the code segment of the memory, where the executable program is stored
- Data Segment: points to the data segment of the memory where the data is stored
- Stack Segment: used to store Stack Segment
- Extra Segment: refers to a segment in the memory which is another data segment in the memory
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Pointers and Index Registers
- IP : Instruction pointer
- BP : Base pointer
- SP: Stack pointer
- SI : Source index
- DI : Destination index
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Flag Register
- results of the computations in the ALU
- SF (Sign Flag): This flag is set, when the result of any computation is negative
- ZF (Zero Flag)
- Parity Flag
- Carry Flag
- Auxliary Carry Flag
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DOS interrupt and its functions for AH= 21h/09h/01h
COA Video: https://youtu.be/afQGZNh8hE4