DoctorWkt/74ls593.md

## 74ls593.md

      
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              74ls593.md
            
          
    Warren's 74LS593 Notes

The 74LS593 is an 8-bit binary counter with an input register. It also has a carry in and carry out, and the counter's output is tri-state. This makes it ideal to be connected to an address bus where it can increment, output its value to the address bus and also load (jump) to a new value placed by another device on the address bus.
The datasheets are confusing, so I've tried to make some of the details a bit clearer here. Here are the links to the datasheets first:

Texas Instruments 74LS593 datasheet
SGS-Thompson 74HC593 datasheet

Pinouts


Name
Pin
Purpose
Pin
Name
Basic Purpose


A
1
Data
20
Vcc
Power


B
2
Data
19
G
Enable counter output


C
3
Data
18
G#
Enable counter output


D
4
Data
17
RCKEN#
Enable register loading


E
5
Data
16
RCK
Load register when rising edge


F
6
Data
15
CCKEN
Enable counter incrementing


G
7
Data
14
CCKEN#
Enable counter incrementing


H
8
Data
13
CCK
Increment counter when rising edge


CLOAD#
9
Load counter
12
CCLR#
Clear counter


Gnd
10
Ground
11
RCO#
Carry output


G and G# Pin Purposes

G and G# control the output of the counter on to the left-hand pins A to H. The two datasheets differ in how these lines work:
SG says:


G
G#
Function


H
X
Pins A-H output is enabled


X
L
Pins A-H output is enabled


L
H
Pins A-H are tri-state


In other words, high G or low G# (or both) enable the output of the counter's value on pins A-H. The TI datasheet says something else, but I don't think TI is correct. Note: test this to see for real.
Counter Pin Purposes

These lines have no effect on the register.
When CCLR# is low, the counter is reset to zero. Otherwise, keep it high.
CCKEN and CCKEN# enable the counter to increment on a rising CCK edge.


CCKEN
CCKEN#
CCK
Function


H
X
Rising edge
Counter increments


X
L
Rising edge
Counter increments


L
H
X
Counter does not increment


Note that the counter is supposed to be independent of the register, but I've observed that the counter increments faster when both CCK and RCK rise at the same time. Yes, even when RCKEN# is high.
Register Pin Purposes

The register comes before the counter, so you need to load the register first, then transfer the register into the counter.
The only time that the register is loaded from pins A to H is:


RCKEN#
RCK
Function


L
Rising edge
Load register from pins A to H


I would assume that you should set G and G# so that the counter's output is not enabled on pins A to H.
The CLOAD# Pin

This pin is confusing. The SGS-Thompson datasheet says that when CLOAD# is low the data of Q bus (i.e. pins A-H) are loaded into the counter. But the logic diagram in both datasheets shows that CLOAD# controls the loading of the counter from the register, not pins A to H.
Therefore, to get a new value into the counter (i.e. to load the PC), you would need to:

Set G and G# to low and high, respectively, to tri-state the counter output.
Lower RCKEN# and clock RCK to load from pins A-H into the register.
Raise RCKEN# to latch the register.
Lower CLOAD# to transfer the register value in to the counter.
Raise CLOAD# to latch the counter.
Raise either G or lower G# to re-enable the counter output on pins A to H.

And throughout this keep CCKEN and CCEN# low and high, respectively, to ensure the counter does not increment.
Cascading 74LS593 Chips

The TCO# pin goes low when the counter increments from 0xFF to 0x00. Therefore, if you need a 16-bit or larger counter, you can connect TCO# from the low-order 74LS593 to the CCKEN# pin of the next-order 74LS593.
Truth Table

I'm redrawing the truth table from the SGS-Thompson datasheet with the input pins in pin order, as I'm playing with one on a breadboard.


CLOAD# (9)
CCLR# (12)
CCK (13)
CCKEN# (14)
CCKEN (15)
RCK (16)
RCKEN# (17)
G# (18)
G (19)
Function


X
X
X
X
X
X
X
H
L
Pins A-H are tri-state


X
X
X
X
X
X
X
X
H
Pins A-H are enabled


X
X
X
X
X
X
X
L
X
Pins A-H are enabled


H
L
X
X
X
X
X
X
X
Counter is reset to zero


L
H
X
X
X
X
X
X
X
Counter is loaded from register


H
H
Rise
X
H
X
X
X
X
Counter is incremented


H
H
Rise
L
X
X
X
X
X
Counter is incremented


H
H
Drop
X
H
X
X
X
X
Counter is not incremented


H
H
Drop
L
X
X
X
X
X
Counter is not incremented


H
H
X
H
L
X
X
X
X
Counter is not incremented


X
X
X
X
X
X
H
X
X
Register value is not changed


X
X
X
X
X
Drop
L
X
X
Register value is not changed


X
X
X
X
X
Rise
L
X
X
Register is loaded from pins A-H
Name	Pin	Purpose	Pin	Name	Basic Purpose
A	1	Data	20	Vcc	Power
B	2	Data	19	G	Enable counter output
C	3	Data	18	G#	Enable counter output
D	4	Data	17	RCKEN#	Enable register loading
E	5	Data	16	RCK	Load register when rising edge
F	6	Data	15	CCKEN	Enable counter incrementing
G	7	Data	14	CCKEN#	Enable counter incrementing
H	8	Data	13	CCK	Increment counter when rising edge
CLOAD#	9	Load counter	12	CCLR#	Clear counter
Gnd	10	Ground	11	RCO#	Carry output
G	G#	Function
H	X	Pins A-H output is enabled
X	L	Pins A-H output is enabled
L	H	Pins A-H are tri-state
CCKEN	CCKEN#	CCK	Function
H	X	Rising edge	Counter increments
X	L	Rising edge	Counter increments
L	H	X	Counter does not increment
CLOAD# (9)	CCLR# (12)	CCK (13)	CCKEN# (14)	CCKEN (15)	RCK (16)	RCKEN# (17)	G# (18)	G (19)	Function
X	X	X	X	X	X	X	H	L	Pins A-H are tri-state
X	X	X	X	X	X	X	X	H	Pins A-H are enabled
X	X	X	X	X	X	X	L	X	Pins A-H are enabled
H	L	X	X	X	X	X	X	X	Counter is reset to zero
L	H	X	X	X	X	X	X	X	Counter is loaded from register
H	H	Rise	X	H	X	X	X	X	Counter is incremented
H	H	Rise	L	X	X	X	X	X	Counter is incremented
H	H	Drop	X	H	X	X	X	X	Counter is not incremented
H	H	Drop	L	X	X	X	X	X	Counter is not incremented
H	H	X	H	L	X	X	X	X	Counter is not incremented
X	X	X	X	X	X	H	X	X	Register value is not changed
X	X	X	X	X	Drop	L	X	X	Register value is not changed
X	X	X	X	X	Rise	L	X	X	Register is loaded from pins A-H