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November 9, 2019 08:32
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A64 option rom by TicTac
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;--------------------------------------------------------------------- | |
; tictac A64 Bios Tweaker Rev 001 Alpha | |
;--------------------------------------------------------------------- | |
.486p | |
CSEG SEGMENT PARA PUBLIC USE16 'CODE' | |
ASSUME CS:CSEG | |
ORG 0 | |
;--------------------------------------------------------------------- | |
; Expansion PCI ROM Header | |
;--------------------------------------------------------------------- | |
db 55h ; Rom signature byte 1 | |
db 0AAh ; Rom signature byte 2 | |
db 01h ; Rom Size (1bit = 512 bytes) | |
jmp INIT ;jump to initialization | |
;--------------------------------------------------------------------- | |
; Address & Data Port | |
;--------------------------------------------------------------------- | |
address equ 0CF8h ; Access to configuration address | |
data equ 0CFCh ; Access to configuration data | |
;--------------------------------------------------------------------- | |
; PCI Bus, Device, Function, Register | |
;--------------------------------------------------------------------- | |
; _________________________________________________________________ | |
; | 28| 24| 20| 16| 12| 8| 4| 0| Bits Number | |
; |1 0 0 0|0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0|0 0 0 0|0 0 0 0|0 0 0 0| Bits | |
; |1 - - -|- - - -| Bus Number | Device |Func |Reg |- -| Definition | |
; |1 0 0 0|0 0 0 0|0 0 0 0 0 0 0 0|1 1 0 0 0|0 1 0|0 0 0 0 0 0|0 0| Bits | |
; | 8 | 0 | 0 0 | 24 | 2 | | 0 | Decimal | |
; | 8 | 0 | 0 0 | C | 2 | | | Hex | |
; |_______________________________________________________________| | |
dtl_add equ 08000C288h ; DRAM Timing Low | |
dth_add equ 08000C28Ch ; DRAM Timing High | |
dcl_add equ 08000C290h ; DRAM Configuration Low | |
dch_add equ 08000C294h ; DRAM Configuration High | |
ddr_add equ 08000C298h ; DRAM Delay Line Register | |
;--------------------------------------------------------------------- | |
; DRAM Timing Low Address | |
;--------------------------------------------------------------------- | |
; CAS Latency(dtl) | |
tcl_data equ 0FFFFFFF8h ; CAS Latency (3bit) | |
tcl_2 equ 000000001h ; CAS 2 | |
tcl_25 equ 000000005h ; CAS 2.5 | |
tcl_3 equ 000000002h ; CAS 3 | |
; Row Cycle Time(dtl) | |
trc_data equ 0FFFFFF0Fh ; Row Cycle Time (4bit) | |
trc_7 equ 000000000h ; | |
trc_8 equ 000000010h ; | |
trc_9 equ 000000020h ; | |
trc_10 equ 000000030h ; | |
trc_11 equ 000000040h ; | |
trc_12 equ 000000050h ; | |
trc_13 equ 000000060h ; | |
trc_14 equ 000000070h ; | |
trc_15 equ 000000080h ; | |
trc_16 equ 000000090h ; | |
trc_17 equ 0000000A0h ; | |
trc_18 equ 0000000B0h ; | |
trc_19 equ 0000000C0h ; | |
trc_20 equ 0000000D0h ; | |
trc_21 equ 0000000E0h ; | |
trc_22 equ 0000000F0h ; | |
; Row Refresh Cycle Time(dtl) | |
trfc_data equ 0FFFFF0FFh ; Row Refresh Cycle Time (4bit) | |
trfc_9 equ 000000000h ; | |
trfc_10 equ 000000100h ; | |
trfc_11 equ 000000200h ; | |
trfc_12 equ 000000300h ; | |
trfc_13 equ 000000400h ; | |
trfc_14 equ 000000500h ; | |
trfc_15 equ 000000600h ; | |
trfc_16 equ 000000700h ; | |
trfc_17 equ 000000800h ; | |
trfc_18 equ 000000900h ; | |
trfc_19 equ 000000A00h ; | |
trfc_20 equ 000000B00h ; | |
trfc_21 equ 000000C00h ; | |
trfc_22 equ 000000D00h ; | |
trfc_23 equ 000000E00h ; | |
trfc_24 equ 000000F00h ; | |
; RAS to CAS Delay(dtl) | |
trcd_data equ 0FFFF8FFFh ; RAS to CAS Delay (3bit) | |
trcd_2 equ 000002000h ; 2 clock | |
trcd_3 equ 000003000h ; 3 clock | |
trcd_4 equ 000004000h ; 4 clock | |
trcd_5 equ 000005000h ; 5 clock | |
trcd_6 equ 000006000h ; 6 clock | |
; RAS to RAS Delay(dtl) | |
trrd_data equ 0FFF8FFFFh ; RAS to RAS Delay (3bit) | |
trrd_2 equ 000020000h ; 2 clock | |
trrd_3 equ 000030000h ; 3 clock | |
trrd_4 equ 000040000h ; 4 clock | |
; Min. RAS active time(dtl) | |
tras_data equ 0FF0FFFFFh ; Min. RAS active time (4bit) | |
tras_5 equ 000500000h ; 5 clock | |
tras_6 equ 000600000h ; 6 clock | |
tras_7 equ 000700000h ; 7 clock | |
tras_8 equ 000800000h ; 8 clock | |
tras_9 equ 000900000h ; 9 clock | |
tras_10 equ 000A00000h ; 10clock | |
tras_11 equ 000B00000h ; 11clock | |
tras_12 equ 000C00000h ; 12clock | |
tras_13 equ 000D00000h ; 13clock | |
tras_14 equ 000E00000h ; 14clock | |
tras_15 equ 000F00000h ; 15clock | |
; Row Precharge Time(dtl) | |
trp_data equ 0F8FFFFFFh ; Row Precharge Time (3bit) | |
trp_2 equ 002000000h ; 2 clock | |
trp_3 equ 003000000h ; 3 clock | |
trp_4 equ 004000000h ; 4 clock | |
trp_5 equ 005000000h ; 5 clock | |
trp_6 equ 006000000h ; 6 clock | |
; Write Recovery Time(dtl) | |
twr_data equ 0EFFFFFFFh ; Write Recovery Time (1bit) | |
twr_2 equ 000000000h ; 2 clock | |
twr_3 equ 010000000h ; 3 clock | |
;--------------------------------------------------------------------- | |
; DRAM Timing High Address | |
;--------------------------------------------------------------------- | |
; Write to read delay(dth) | |
twtr_data equ 0FFFFFFFEh ; Write to read delay (1bit) | |
twtr_1 equ 000000001h ; 1 clock | |
twtr_2 equ 000000002h ; 2 clock | |
; Read to write delay(dth) | |
trwt_data equ 0FFFFFF8Fh ; Read to write delay (3bit) | |
trwt_1 equ 000000000h ; 1 clock | |
trwt_2 equ 000000010h ; 2 clock | |
trwt_3 equ 000000020h ; 3 clock | |
trwt_4 equ 000000030h ; 4 clock | |
trwt_5 equ 000000040h ; 5 clock | |
trwt_6 equ 000000050h ; 6 clock | |
; Refresh Rate(dth) | |
tref_data equ 0FFFFE0FFh ; Refresh Rate (5bit) | |
tref_100_156 equ 000000000h ; 100MHz 15.6us | |
tref_133_156 equ 000000100h ; 133MHz 15.6us | |
tref_166_156 equ 000000200h ; 166MHz 15.6us | |
tref_200_156 equ 000000300h ; 200MHz 15.6us | |
tref_100_78 equ 000000800h ; 100MHz 7.8us | |
tref_133_78 equ 000000900h ; 133MHz 7.8us | |
tref_166_78 equ 000000A00h ; 166MHz 7.8us | |
tref_200_78 equ 000000B00h ; 200MHz 7.8us | |
tref_100_39 equ 000001000h ; 100MHz 3.9us | |
tref_133_39 equ 000001100h ; 133MHz 3.9us | |
tref_166_39 equ 000001200h ; 166MHz 3.9us | |
tref_200_39 equ 000001300h ; 200MHz 3.9us | |
; Write CAS latency(dth) | |
twcl_data equ 0FF8FFFFFh ; Write CAS latency (3bit) | |
twcl_1 equ 000000000h ; 1 clock | |
twcl_2 equ 000100000h ; 2 clock | |
;--------------------------------------------------------------------- | |
; DRAM Configuration Low Address | |
;--------------------------------------------------------------------- | |
; DLL Disabled(dcl) | |
dll_data equ 0FFFFFFFEh ; DLL disabled (1bit) | |
dll_enable equ 000000000h ; Enabled(default) | |
dll_disable equ 000000001h ; Disabled | |
; Dimm Drive Strength(dcl) | |
dds_data equ 0FFFFFFFDh ; Dimm Drive Strength (1bit) | |
dds_normal equ 000000000h ; (Default) | |
dds_weak equ 000000002h ; (Beware) | |
; Read/Write Qued Bypass(dcl) | |
rwqbp_data equ 0FFFF3FFFh ; Read/Write Qued Bypass (2bit) | |
rwqbp_2x equ 000000000h ; 2x | |
rwqbp_4x equ 000004000h ; 4x | |
rwqbp_8x equ 000008000h ; 8x | |
rwqbp_16x equ 00000C000h ; 16x | |
; Bypass Max(dcl) | |
bpm_data equ 0F1FFFFFFh ; Bypass Max (3bit) | |
bpm_0x equ 000000000h ; 0x (Disabled) | |
bpm_1x equ 002000000h ; 1x | |
bpm_2x equ 004000000h ; 2x | |
bpm_3x equ 006000000h ; 3x | |
bpm_4x equ 008000000h ; 4x | |
bpm_5x equ 00A000000h ; 5x | |
bpm_6x equ 00C000000h ; 6x | |
bpm_7x equ 00E000000h ; 7x | |
; Command Rate(dcl) | |
cr_data equ 0EFFFFFFFh ; Command Rate (1bit) | |
cr_1t equ 000000000h ; 1T | |
cr_2t equ 010000000h ; 2T | |
;--------------------------------------------------------------------- | |
; DRAM Configuration High Address | |
;--------------------------------------------------------------------- | |
; Maximum Async Latency(dch) | |
async_data equ 0FFFFFFF0h ; Maximum Async Latency (4bit) | |
async_0 equ 000000000h ; 0 ns | |
async_1 equ 000000001h ; 1 ns | |
async_2 equ 000000002h ; 2 ns | |
async_3 equ 000000003h ; 3 ns | |
async_4 equ 000000004h ; 4 ns | |
async_5 equ 000000005h ; 5 ns | |
async_6 equ 000000006h ; 6 ns | |
async_7 equ 000000007h ; 7 ns | |
async_8 equ 000000008h ; 8 ns | |
async_9 equ 000000009h ; 9 ns | |
async_10 equ 00000000Ah ; 10ns | |
async_11 equ 00000000Bh ; 11ns | |
async_12 equ 00000000Ch ; 12ns | |
async_13 equ 00000000Dh ; 13ns | |
async_14 equ 00000000Eh ; 14ns | |
async_15 equ 00000000Fh ; 15ns | |
; Read Preamble(dch) | |
rp_data equ 0FFFFF0FFh ; Read Preamble (4bit) | |
rp_20 equ 000000000h ; 2.0ns | |
rp_25 equ 000000100h ; 2.5ns | |
rp_30 equ 000000200h ; 3.0ns | |
rp_35 equ 000000300h ; 3.5ns | |
rp_40 equ 000000400h ; 4.0ns | |
rp_45 equ 000000500h ; 4.5ns | |
rp_50 equ 000000600h ; 5.0ns | |
rp_55 equ 000000700h ; 5.5ns | |
rp_60 equ 000000800h ; 6.0ns | |
rp_65 equ 000000900h ; 6.5ns | |
rp_70 equ 000000A00h ; 7.0ns | |
rp_75 equ 000000B00h ; 7.5ns | |
rp_80 equ 000000C00h ; 8.0ns | |
rp_85 equ 000000D00h ; 8.5ns | |
rp_90 equ 000000E00h ; 9.0ns | |
rp_95 equ 000000F00h ; 9.5ns | |
; Idle Cycle Limit(dch) | |
icl_data equ 0FFF8FFFFh ; Idle Cycle Limit (3bit) | |
icl_0 equ 000000000h ; 0 clock | |
icl_4 equ 000010000h ; 4 clock | |
icl_8 equ 000020000h ; 8 clock | |
icl_16 equ 000030000h ; 16clock | |
icl_32 equ 000040000h ; 32clock | |
icl_64 equ 000050000h ; 64clock | |
icl_128 equ 000060000h ; 128clock | |
icl_256 equ 000070000h ; 256clock | |
; Dynamic idle cycle counter enable(dch) | |
dicc_data equ 0FFF7FFFFh ; Dynamic idle cycle limit (1bit) | |
dicc_disable equ 000000000h ; disabled | |
dicc_enable equ 000080000h ; enabled | |
; Memory Clock Frequency(dch) | |
mcf_data equ 0FF8FFFFFh ; Memory Clock Frequency (3bit) | |
mcf_100 equ 000000000h ; 100MHz | |
mcf_133 equ 000200000h ; 133MHz | |
mcf_166 equ 000500000h ; 166MHz | |
mcf_200 equ 000700000h ; 200MHz (1:1) | |
;--------------------------------------------------------------------- | |
; DRAM DQS Delay Line Register | |
;--------------------------------------------------------------------- | |
; DQS Slew Value(ddr) | |
dqs_data equ 0FF00FFFFh ; Delay Line Adjust (8bit) | |
dqs_1 equ 000010000h ; 1 | |
dqs_2 equ 000020000h ; 2 | |
dqs_3 equ 000030000h ; 3 | |
dqs_4 equ 000040000h ; 4 | |
dqs_5 equ 000050000h ; 5 | |
dqs_6 equ 000060000h ; 6 | |
dqs_7 equ 000070000h ; 7 | |
dqs_8 equ 000080000h ; 8 | |
dqs_9 equ 000090000h ; 9 | |
dqs_10 equ 0000A0000h ; 10 | |
dqs_255 equ 000FF0000h ; 255 | |
; DQS Slew Control(ddr) | |
dqsc_data equ 0FCFFFFFFh ; Adjust DQS (1bit) & (1bit) | |
dqsc_slow equ 001000000h ; Slower DQS | |
dqsc_fast equ 002000000h ; Faster DQS | |
;--------------------------------------------------------------------- | |
; Sub Routine | |
;--------------------------------------------------------------------- | |
ORG 100h | |
SAVE1 PROC NEAR ; Save all register that will be affected by our code | |
push eax | |
push ebx | |
push edx | |
pushfd | |
ret | |
SAVE1 ENDP | |
SENDER PROC NEAR ; Active communication with address | |
mov dx,address | |
out dx,eax | |
ret | |
SENDER ENDP | |
RECEIVER PROC NEAR ; Comunicate with the address & receive the data | |
mov dx,address | |
out dx,eax | |
mov dx,data | |
in eax,dx | |
ret | |
RECEIVER ENDP | |
TUNER1 PROC NEAR ; Sending new data from ebx stack | |
xchg eax,ebx | |
out dx,eax | |
xchg eax,ebx | |
ret | |
TUNER1 ENDP | |
TUNER2 PROC NEAR ; Increase data (OR) | |
or eax,ebx | |
out dx,eax | |
ret | |
TUNER2 ENDP | |
TUNER3 PROC NEAR ; Decrease data (AND) | |
and eax,ebx | |
out dx,eax | |
ret | |
TUNER3 ENDP | |
RETURN1 PROC NEAR ; Restore register contents and return far to system | |
popfd | |
pop edx | |
pop ebx | |
pop eax | |
retf | |
RETURN1 ENDP | |
RETURN2 PROC NEAR ; Restore register contents and return to SATA bios | |
popfd | |
pop edx | |
pop ebx | |
pop eax | |
retf | |
RETURN2 ENDP | |
;--------------------------------------------------------------------- | |
; Main Routine | |
;--------------------------------------------------------------------- | |
INIT PROC NEAR | |
; save all register that will be affected by our code | |
call SAVE1 | |
; trc = 13 | |
mov eax,dtl_add | |
mov ebx,trc_13 | |
call RECEIVER | |
and eax,trc_data | |
call TUNER2 | |
; trfc = 15 | |
mov eax,dtl_add | |
mov ebx,trfc_15 | |
call RECEIVER | |
and eax,trfc_data | |
call TUNER2 | |
; END Patch back to system bios or SATA jump (RETURN1 = System ; RETURN2 = SATA jump) | |
call RETURN2 | |
INIT ENDP | |
ORG 200h | |
CSEG ENDS | |
END | |
;--------------------------------------------------------------------- | |
; tictac A64 Bios Tweaker Rev 001 Alpha | |
;--------------------------------------------------------------------- |
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