A VHDL project that does something I can't remember with a 4 digit multiplexed 7seg display

constraints.ucf

CONFIG PROHIBIT=P144;
CONFIG PROHIBIT=P69;
CONFIG PROHIBIT=P60;

NET avr_rst LOC = "P139" | IOSTANDARD=LVTTL;
NET CLK     LOC="P94"  | IOSTANDARD=LVTTL;
TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%;

NET switches(7) LOC = "P39" | IOSTANDARD=LVTTL;
NET switches(6) LOC = "P48" | IOSTANDARD=LVTTL;
NET switches(5) LOC = "P51" | IOSTANDARD=LVTTL;
NET switches(4) LOC = "P56" | IOSTANDARD=LVTTL;
NET switches(3) LOC = "P58" | IOSTANDARD=LVTTL;
NET switches(2) LOC = "P61" | IOSTANDARD=LVTTL;
NET switches(1) LOC = "P66" | IOSTANDARD=LVTTL;
NET switches(0) LOC = "P74" | IOSTANDARD=LVTTL;

NET segments(7) LOC = "P47" | IOSTANDARD=LVTTL;
NET segments(6) LOC = "P50" | IOSTANDARD=LVTTL;
NET segments(5) LOC = "P55" | IOSTANDARD=LVTTL;
NET segments(4) LOC = "P57" | IOSTANDARD=LVTTL;
NET segments(3) LOC = "P59" | IOSTANDARD=LVTTL;
NET segments(2) LOC = "P62" | IOSTANDARD=LVTTL;
NET segments(1) LOC = "P67" | IOSTANDARD=LVTTL;
NET segments(0) LOC = "P75" | IOSTANDARD=LVTTL;

NET digits(3) LOC = "P79" | IOSTANDARD=LVTTL;
NET digits(2) LOC = "P81" | IOSTANDARD=LVTTL;
NET digits(1) LOC = "P83" | IOSTANDARD=LVTTL;
NET digits(0) LOC = "P85" | IOSTANDARD=LVTTL;

NET buttons(1) LOC = "P97" | IOSTANDARD=LVTTL;
NET buttons(0) LOC = "P99" | IOSTANDARD=LVTTL;

mux7seg.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:34:59 08/03/2017 
-- Design Name: 
-- Module Name:    mux7seg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux7seg is
    Port (
		CLK		: in	STD_LOGIC;
		switches 	: in	STD_LOGIC_VECTOR(0 downto 0);
		buttons		: in	STD_LOGIC_VECTOR(0 downto 0);
		segments	: out	STD_LOGIC_VECTOR(7 downto 0);
      		digits 		: out STD_LOGIC_VECTOR(3 downto 0);
     		avr_rst 	: out STD_LOGIC);
end mux7seg;

architecture Behavioral of mux7seg is
signal x: STD_LOGIC_VECTOR(15 downto 0);
signal secondsish: STD_LOGIC_VECTOR(22 downto 0);
signal pulsed_clock: STD_LOGIC;
begin
	avr_rst <= '0'; -- Holding the AVR in reset as we aren't using it.

	x7seg_1: entity work.x7seg PORT MAP(
		x => x,
		clk => CLK,
		clr => switches(0),
		a_to_dp => segments,
		digits => digits
	);
	
	-- Count on rising clk
	process(CLK, switches(0))
	begin
		if rising_edge(CLK) and switches(0) = '0' then
			secondsish <= secondsish + 1;
		end if;
	end process;
	
	pulse_1: entity work.pulse PORT MAP(
		s => not buttons(0),
		clk => secondsish(18),
		clr => '0',
		outp => pulsed_clock
	);
    
	-- Increase displayed count each secondish
	--process(secondsish(20))
	process(pulsed_clock)
	begin
		if rising_edge(pulsed_clock) then
			x <= x + 1;
		end if;
	end process;


end Behavioral;

pulse.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:52:31 08/05/2017 
-- Design Name: 
-- Module Name:    pulse - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pulse is
	Port (
		s	: in	STD_LOGIC;
		clk	: in	STD_LOGIC;
		clr	: in	STD_LOGIC;
      		outp	: out	STD_LOGIC);
end pulse;

architecture Behavioral of pulse is
signal delay : STD_LOGIC_VECTOR(2 downto 0);
begin

	process(clk, clr)
	begin
		if clr = '1' then
			delay <= (others => '0');
		elsif rising_edge(clk) then
			delay(1 downto 0) <= delay(2 downto 1);
			delay(2) <= s;
		end if;
	end process;
	outp <= delay(2) and delay(1) and not delay(0);
end Behavioral;

x7seg.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:05:56 08/03/2017 
-- Design Name: 
-- Module Name:    x7seg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity x7seg is
    Port (	x		: in	STD_LOGIC_VECTOR(15 downto 0);
           	clk		: in	STD_LOGIC;
	  	clr		: in	STD_LOGIC;
		a_to_dp		: out STD_LOGIC_VECTOR(7 downto 0);
		digits		: out STD_LOGIC_VECTOR(3 downto 0));
end x7seg;

architecture x7seg of x7seg is
signal s		: STD_LOGIC_VECTOR(1 downto 0);
signal disp		: STD_LOGIC_VECTOR(3 downto 0);
signal aen		: STD_LOGIC_VECTOR(3 downto 0);
signal clkdiv		: STD_LOGIC_VECTOR(17 downto 0);
begin
	s <= clkdiv(17 downto 16);
	
	process(s, x) 
	begin
		case s is
			when "00" => disp <= x(3 downto 0);
			when "01" => disp <= x(7 downto 4);
			when "10" => disp <= x(11 downto 8);
			when others => disp <= x(15 downto 12);
		end case;
	end process;
	
	-- ancode: encode the enable/disable signals for the digits
	process(s, aen)
	begin
		digits <= "1111";
		if aen(conv_integer(s)) = '1' then 
			digits(conv_integer(s)) <= '0';
		end if;
	end process;

	-- Clock divider counter
	process(clk, clr)
	begin
		if clr = '1' then
			clkdiv <= (others => '0');
			aen <= (others => '0');
		elsif rising_edge(clk) then
			clkdiv <= clkdiv + 1;
			aen <= (others => '1');
		end if;
	end process;
	
	-- hex-to-7seg decoder
	process(disp)
	begin
		case disp is
			when X"0" => a_to_dp <= "00000011"; -- 0
			when X"1" => a_to_dp <= "10011111"; -- 1
			when X"2" => a_to_dp <= "00100101"; -- 2
			when X"3" => a_to_dp <= "00001101"; -- 3
			when X"4" => a_to_dp <= "10011001"; -- 4
			when X"5" => a_to_dp <= "01001001"; -- 5
			when X"6" => a_to_dp <= "01000001"; -- 6.
			when X"7" => a_to_dp <= "00011111"; -- 7
			when X"8" => a_to_dp <= "00000001"; -- 8
			when X"9" => a_to_dp <= "00011001"; -- 9.
			when X"A" => a_to_dp <= "00010001"; -- A
			when X"B" => a_to_dp <= "11000001"; -- b
			when X"C" => a_to_dp <= "01100011"; -- C
			when X"D" => a_to_dp <= "10000101"; -- d
			when X"E" => a_to_dp <= "01100001"; -- E
			when others => a_to_dp <= "01110001"; -- F
		end case;
	end process;
end x7seg;