LiteScope SoC definition for the TinyFPGA BX

litex_client.py

from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver

wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()

analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True, config_csv="test/analyzer.csv")

analyzer.configure_subsampler(1)  ## increase this to "skip" cycles, e.g. subsample
analyzer.configure_group(0)

# trigger conditions will depend upon each other in sequence
# analyzer.add_falling_edge_trigger("soc_videooverlaysoc_hdmi_in0_timing_payload_vsync")
# analyzer.add_rising_edge_trigger("soc_videooverlaysoc_hdmi_in0_timing_payload_de")
# analyzer.add_trigger(cond={"soc_videooverlaysoc_hdmi_in0_timing_payload_hsync" : 1})

analyzer.run(offset=32, length=128)  ### CHANGE THIS TO MATCH DEPTH
analyzer.wait_done()
analyzer.upload()
analyzer.save("test/dump.vcd")

wb.close()

tinyfpga_litescope.py

#!/usr/bin/env python3

from migen import *
from migen.genlib.io import CRG

from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge

from litex_boards.partner.platforms import tinyfpga_bx

from litescope import LiteScopeIO, LiteScopeAnalyzer


class LiteScopeSoC(SoCCore):
    csr_map = {
        "io":       16,
        "analyzer": 17
    }
    csr_map.update(SoCCore.csr_map)

    def __init__(self, platform):
        platform.add_extension(tinyfpga_bx.serial)

        sys_clk_freq = int((1e9/platform.default_clk_period))
        SoCCore.__init__(self, platform, sys_clk_freq,
            cpu_type=None,
            csr_data_width=32,
            with_uart=False,
            ident="Litescope example design", ident_version=True,
            with_timer=False
        )
        # crg
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        # bridge
        self.add_cpu(UARTWishboneBridge(platform.request("serial"),
            sys_clk_freq, baudrate=115200))
        self.add_wb_master(self.cpu.wishbone)

        # Litescope IO
        self.submodules.io = LiteScopeIO(8)
        for i in range(13, 24):
            try:
                self.comb += platform.request("GPIO", i).eq(self.io.output[i])
            except:
                pass

        # Litescope Analyzer
        analyzer_groups = {}

        # counter group
        counter = Signal(16, name_override="counter")
        zero = Signal(name_override="zero")
        self.sync += counter.eq(counter + 1)
        self.comb += zero.eq(counter == 0)
        analyzer_groups[0] = [
            zero,
            counter
        ]

        # communication group
        # analyzer_groups[1] = [
        #     platform.lookup_request("serial").tx,
        #     platform.lookup_request("serial").rx,
        #     self.cpu.wishbone
        # ]

        # fsm group
        fsm = FSM(reset_state="STATE1")
        self.submodules += fsm
        fsm.act("STATE1",
            NextState("STATE2")
        )
        fsm.act("STATE2",
            NextState("STATE1")
        )
        analyzer_groups[1] = [
            fsm
        ]

        # analyzer
        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 128)

    def do_exit(self, vns):
        self.analyzer.export_csv(vns, "test/analyzer.csv")


platform = tinyfpga_bx.Platform()

soc = LiteScopeSoC(platform)
vns = platform.build(soc)

#
# Create csr and analyzer files
#
soc.finalize()
csr_regions = soc.get_csr_regions()
csr_constants = soc.get_constants()
from litex.build.tools import write_to_file
from litex.soc.integration import cpu_interface

csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
write_to_file("test/csr.csv", csr_csv)
soc.do_exit(vns)


#
# Program
#
platform.create_programmer().load_bitstream("build/top.bin")