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EgorBot/diff_asm_bcd38073.asm Secret

Created January 23, 2025 16:14
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diff_asm_bcd38073.asm
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diff_asm_bcd38073.asm
Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5014506000, [percent: local period]
JIT_NewS_MP_FastPortable(CORINFO_CLASS_STRUCT_*)() /home/egorbot/core_root_diff/libcoreclr.so
Percent
Disassembly of section .text:
0000000000360fb8 <GetCLRRuntimeHost@@V1.0+0x13080c>:
1.40 stp x29, x30, [sp, #-32]!
2.24 str x19, [sp, #16]
1.01 mov x29, sp
0.03 adrp x8, __getauxval@plt+0x36950
1.26 mov x19, x0
1.64 ldr x8, [x8, #1192]
1.42 ↓ cbz x8, 20
→ bl TLS init function for t_runtime_thread_locals@plt
1.26 20: adrp x0, __getauxval@plt+0x36950
1.45 ldr x1, [x0, #1200]
1.26 add x0, x0, #0x4b0
1.37 → blr x1
4.35 mrs x8, tpidr_el0
1.23 ldr w9, [x19, #4]
0.99 add x8, x8, x0
1.26 ldp x10, x0, [x8]
45.87 sub x10, x10, x0
1.72 cmp x10, x9
0.08 ↓ b.cs 5c
mov x0, x19
0.25 ldr x19, [sp, #16]
0.19 ldp x29, x30, [sp], #32
0.03 ↓ b 74
24.11 5c: add x9, x0, x9
1.56 str x9, [x8, #8]
1.09 str x19, [x0]
1.51 ldr x19, [sp, #16]
1.42 ldp x29, x30, [sp], #32
← ret
Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5014506000, [percent: local period]
JIT_WriteBarrier() /home/egorbot/core_root_diff/libcoreclr.so
Percent
Disassembly of section .text:
000000000049d3f4 <GetCLRRuntimeHost@@V1.0+0x26cc48>:
2.53 stlr x15, [x14]
1.98 ldr x12, GetCLRRuntimeHost@@V1.0+0x26cd64
2.32 ↓ cbz x12, 20
add x12, x12, x14, lsr #12
ldrb w17, [x12]
↓ cbnz x17, 20
mov w17, #0xff // #255
strb w17, [x12]
2.23 20: ldr x12, GetCLRRuntimeHost@@V1.0+0x26cd6c
1.94 ldr x17, GetCLRRuntimeHost@@V1.0+0x26cd74
0.17 cmp x15, x12
2.11 ccmp x15, x17, #0x2, cs // cs = hs, nlast
↓ b.cs d0
5.81 ldr x17, GetCLRRuntimeHost@@V1.0+0x26cd8c
2.36 ↓ cbz x17, 98
1.77 ldr w12, GetCLRRuntimeHost@@V1.0+0x26cd94
lsr x15, x15, x12
1.85 add x15, x15, x17
1.56 lsr x12, x14, x12
2.53 add x12, x12, x17
1.94 ldrb w12, [x12]
2.99 ↓ cbz w12, d0
3.03 ldrb w15, [x15]
33.74 cmp w15, w12
↓ b.cs d0
13.18 ldr w17, GetCLRRuntimeHost@@V1.0+0x26cd98
1.98 ↓ cbz w17, 98
2.36 lsr w17, w14, #8
and w17, w17, #0x7
1.73 mov w15, #0x1 // #1
0.08 lsl w17, w15, w17
1.68 ldr x12, GetCLRRuntimeHost@@V1.0+0x26cd54
add x15, x12, x14, lsr #11
2.23 ldrb w12, [x15]
1.77 tst w12, w17
0.08 ↓ b.ne d0
stsetb w17, [x15]
↓ b b4
98: ldr x12, GetCLRRuntimeHost@@V1.0+0x26cd54
add x15, x12, x14, lsr #11
ldrb w12, [x15]
cmp x12, #0xff
↓ b.eq d0
mov x12, #0xff // #255
strb w12, [x15]
b4: ldr x12, GetCLRRuntimeHost@@V1.0+0x26cd5c
add x15, x12, x14, lsr #21
ldrb w12, [x15]
cmp x12, #0xff
↓ b.eq d0
mov x12, #0xff // #255
strb w12, [x15]
4.04 d0: add x14, x14, #0x8
← ret
Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5014506000, [percent: local period]
instance void [benchapp] MyBench::WB_ephemeral()[OptimizedTier1]() /tmp/jitted-60522-7276.so
Percent
Disassembly of section .text:
0000000000000080 <instance void [benchapp] MyBench::WB_ephemeral()[OptimizedTier1]>:
6.94 stp x29, x30, [sp, #-32]!
15.38 str x19, [sp, #24]
6.64 mov x29, sp
0.60 mov x19, x0
7.09 mov x0, #0x4948 // #18760
6.79 movk x0, #0xbc01, lsl #16
6.18 movk x0, #0xf0cd, lsl #32
6.64 bl ffffffffff6497e8 <instance void [benchapp] MyBench::WB_ephemeral()[OptimizedTier1]+0xffffffffff649768>
16.74 mov x15, x0
0.15 add x14, x19, #0x8
8.14 bl ffffffffff6497f8 <instance void [benchapp] MyBench::WB_ephemeral()[OptimizedTier1]+0xffffffffff649778>
9.05 ldr x19, [sp, #24]
8.14 ldp x29, x30, [sp], #32
1.51 ← ret
Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5014506000, [percent: local period]
instance void [2810ada2-2a8b-49d3-9234-74b1b29ebbcdEmitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-60522-7241.so
Percent
Disassembly of section .text:
0000000000000080 <instance void [2810ada2-2a8b-49d3-9234-74b1b29ebbcdEmitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]>:
stp x29, x30, [sp, #-32]!
stp x19, x20, [sp, #16]
mov x29, sp
mov x19, x0
cmp x1, #0x0
↓ b.le 124
mov x20, x1
2.69 1c: ldr x1, [x19, #80]
1.92 ldr x0, [x1, #8]
2.31 ldr x1, [x1, #24]
1.92 → blr x1
1.92 ldr x1, [x19, #80]
1.15 ldr x0, [x1, #8]
1.92 ldr x1, [x1, #24]
1.15 → blr x1
1.92 ldr x1, [x19, #80]
1.54 ldr x0, [x1, #8]
0.38 ldr x1, [x1, #24]
1.15 → blr x1
1.54 ldr x1, [x19, #80]
3.46 ldr x0, [x1, #8]
1.92 ldr x1, [x1, #24]
0.77 → blr x1
3.46 ldr x1, [x19, #80]
1.15 ldr x0, [x1, #8]
1.54 ldr x1, [x1, #24]
1.54 → blr x1
1.54 ldr x1, [x19, #80]
1.54 ldr x0, [x1, #8]
1.54 ldr x1, [x1, #24]
0.38 → blr x1
4.23 ldr x1, [x19, #80]
0.77 ldr x0, [x1, #8]
2.31 ldr x1, [x1, #24]
2.31 → blr x1
1.15 ldr x1, [x19, #80]
1.54 ldr x0, [x1, #8]
1.15 ldr x1, [x1, #24]
0.77 → blr x1
1.92 ldr x1, [x19, #80]
0.38 ldr x0, [x1, #8]
0.77 ldr x1, [x1, #24]
1.15 → blr x1
1.92 ldr x1, [x19, #80]
0.77 ldr x0, [x1, #8]
2.31 ldr x1, [x1, #24]
1.54 → blr x1
1.54 ldr x1, [x19, #80]
0.38 ldr x0, [x1, #8]
3.08 ldr x1, [x1, #24]
0.77 → blr x1
1.54 ldr x1, [x19, #80]
3.08 ldr x0, [x1, #8]
0.77 ldr x1, [x1, #24]
2.31 → blr x1
1.15 ldr x1, [x19, #80]
0.38 ldr x0, [x1, #8]
0.38 ldr x1, [x1, #24]
1.15 → blr x1
1.54 ldr x1, [x19, #80]
1.15 ldr x0, [x1, #8]
0.77 ldr x1, [x1, #24]
2.31 → blr x1
1.15 ldr x1, [x19, #80]
0.38 ldr x0, [x1, #8]
1.54 ldr x1, [x1, #24]
1.15 → blr x1
1.15 ldr x1, [x19, #80]
1.54 ldr x0, [x1, #8]
1.54 ldr x1, [x1, #24]
→ blr x1
3.08 sub x20, x20, #0x1
0.77 ↑ cbnz x20, 1c
124: ldp x19, x20, [sp, #16]
ldp x29, x30, [sp], #32
← ret
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