diff_asm_b84ab9f0.asm

diff_asm_b84ab9f0.asm

Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5006502000, [percent: local period]
instance int32 [benchapp] Bench::TestInner(class [System.Runtime]System.Collections.Generic.ICollection`1<string>)[OptimizedTier1]() /tmp/jitted-53947-7271.so
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            Disassembly of section .text:
               
            0000000000000080 <instance int32 [benchapp] Bench::TestInner(class [System.Runtime]System.Collections.Generic.ICollection`1<string>)[OptimizedTier1]>:
 30.62        stp  x29, x30, [sp, #-16]!
  0.11        mov  x29, sp  
  3.20        ldr  x0, [x1] 
  1.72        mov  x11, #0x9070                    // #36976
  0.17        movk x11, #0x51e, lsl #16
  1.64        movk x11, #0xe4aa, lsl #32
  1.73        cmp  x0, x11  
            ↓ b.ne 2c       
  1.79        ldr  w0, [x1, #8]
  1.72  24:   ldp  x29, x30, [sp], #16
 57.30      ← ret           
        2c:   mov  x0, x1   
              mov  x11, #0x2458                    // #9304
              movk x11, #0x404, lsl #16
              movk x11, #0xe4aa, lsl #32
              ldr  x16, [x11]
            → blr  x16      
            ↑ b    24       
Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5006502000, [percent: local period]
instance void [d8b03265-5d61-4709-b1d8-b442eacaeb14Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-53947-7234.so
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             Disassembly of section .text:
               
             0000000000000080 <instance void [d8b03265-5d61-4709-b1d8-b442eacaeb14Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]>:
               stp   x29, x30, [sp, #-48]!
               stp   x19, x20, [sp, #24]
               str   x21, [sp, #40]
               mov   x29, sp  
               mov   x19, x0  
               cmp   x1, #0x0 
             ↓ b.le  168      
               mov   x20, x1  
  0.72   20:   ldp   x1, x21, [x19, #48]
  0.65         ldr   x0, [x1, #8]
  0.51         ldr   x1, [x1, #24]
  0.65       → blr   x1       
  3.75         stlur w0, [x21, #56]
  0.65         ldp   x1, x21, [x19, #48]
  0.36         ldr   x0, [x1, #8]
  0.58         ldr   x1, [x1, #24]
  0.87       → blr   x1       
  3.97         stlur w0, [x21, #56]
  0.07         ldp   x1, x21, [x19, #48]
  0.87         ldr   x0, [x1, #8]
  0.43         ldr   x1, [x1, #24]
  0.94       → blr   x1       
  4.62         stlur w0, [x21, #56]
  0.22         ldp   x1, x21, [x19, #48]
  0.29         ldr   x0, [x1, #8]
  0.79         ldr   x1, [x1, #24]
  0.43       → blr   x1       
  4.40         stlur w0, [x21, #56]
  0.36         ldp   x1, x21, [x19, #48]
  0.36         ldr   x0, [x1, #8]
  0.72         ldr   x1, [x1, #24]
  0.65       → blr   x1       
  4.83         stlur w0, [x21, #56]
  0.58         ldp   x1, x21, [x19, #48]
  0.29         ldr   x0, [x1, #8]
  0.14         ldr   x1, [x1, #24]
  0.65       → blr   x1       
  4.40         stlur w0, [x21, #56]
  0.43         ldp   x1, x21, [x19, #48]
  0.65         ldr   x0, [x1, #8]
  0.51         ldr   x1, [x1, #24]
  0.51       → blr   x1       
  4.11         stlur w0, [x21, #56]
  0.51         ldp   x1, x21, [x19, #48]
  0.51         ldr   x0, [x1, #8]
  0.51         ldr   x1, [x1, #24]
  0.79       → blr   x1       
  4.47         stlur w0, [x21, #56]
  0.36         ldp   x1, x21, [x19, #48]
  0.51         ldr   x0, [x1, #8]
  0.36         ldr   x1, [x1, #24]
  0.14       → blr   x1       
  3.97         stlur w0, [x21, #56]
  0.58         ldp   x1, x21, [x19, #48]
  0.29         ldr   x0, [x1, #8]
  0.58         ldr   x1, [x1, #24]
  0.58       → blr   x1       
  3.39         stlur w0, [x21, #56]
  0.36         ldp   x1, x21, [x19, #48]
  0.79         ldr   x0, [x1, #8]
  0.58         ldr   x1, [x1, #24]
  0.29       → blr   x1       
  5.12         stlur w0, [x21, #56]
  0.72         ldp   x1, x21, [x19, #48]
  0.72         ldr   x0, [x1, #8]
  0.51         ldr   x1, [x1, #24]
  0.43       → blr   x1       
  3.39         stlur w0, [x21, #56]
  0.72         ldp   x1, x21, [x19, #48]
  0.43         ldr   x0, [x1, #8]
  0.51         ldr   x1, [x1, #24]
  0.65       → blr   x1       
  3.75         stlur w0, [x21, #56]
  0.65         ldp   x1, x21, [x19, #48]
  0.51         ldr   x0, [x1, #8]
  0.51         ldr   x1, [x1, #24]
  0.79       → blr   x1       
  4.04         stlur w0, [x21, #56]
  0.72         ldp   x1, x21, [x19, #48]
  0.51         ldr   x0, [x1, #8]
  0.72         ldr   x1, [x1, #24]
  0.72       → blr   x1       
  3.39         stlur w0, [x21, #56]
  0.51         ldp   x1, x21, [x19, #48]
  0.36         ldr   x0, [x1, #8]
  0.36         ldr   x1, [x1, #24]
  0.65       → blr   x1       
  3.75         stlur w0, [x21, #56]
  0.36         sub   x20, x20, #0x1
             ↑ cbnz  x20, 20  
        168:   ldr   x21, [sp, #40]
               ldp   x19, x20, [sp, #24]
               ldp   x29, x30, [sp], #48
             ← ret            
Samples: 10K of event 'cpu-clock', 1999 Hz, Event count (approx.): 5006502000, [percent: local period]
instance int32 [benchapp] Bench::Test()[OptimizedTier1]() /tmp/jitted-53947-7270.so
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            Disassembly of section .text:
               
            0000000000000080 <instance int32 [benchapp] Bench::Test()[OptimizedTier1]>:
 10.74        stp  x29, x30, [sp, #-16]!
  0.92        mov  x29, sp  
 23.72        mov  x1, #0x2d00                     // #11520
  1.23        movk x1, #0xf800, lsl #16
 11.76        movk x1, #0xe469, lsl #32
 13.50        ldr  x1, [x1] 
  0.10        mov  x2, #0xd260                     // #53856
 13.39        movk x2, #0x5c1, lsl #16
  0.31        movk x2, #0xe4aa, lsl #32
 10.94        ldr  x2, [x2] 
 13.39        ldp  x29, x30, [sp], #16
            → br   x2