2012-02-02-esercizio2-interfaccia.v

module Interfaccia_SuperSemplificata(ir, ior_, d7_d0, dav_, rfd, bytein, reset_);
	input ior_, dav_, reset_;
	input [7:0] bytein;
	output ir;
	inout [7:0] d7_d0;
	
	reg [7:0] BUFF;
	
	RSA_Interfaccia rsa(rfd, dav_, ir, ior_, reset_);
	
	assign d7_d0 = (ior_ == 0) ? BUFF : 'HZZ; // forchetta bus dati
	
	always @(negedge dav_)
		BUFF <= bytein;
endmodule


/**
 * {dav_,ior_}
 *       00   01   11   10 | rfd | ir |
 * ----+----+----+----+----+-----+----+
 *  S0 |    | S1 |(S0)|    |  1    0
 *     +----+----+----+----+
 *  S1 | S2 |(S1)|    |    |  0    1
 *     +----+----+----+----+ 
 *  S2 |(S2)| S3 |    |    |  0    1
 *     +----+----+----+----+
 *  S3 |    |(S3)| S0 |    |  0    0
 * ----+----+----+----+----+-----------
 * 
 * Tabella di flusso della rete sequenziale asincrona, con annessi gli stati di
 * uscita. Lo stato interno iniziale è S0, impostato al reset.
 * 
 * La codifica standard degli stati interni consente di non avere alee essenziali. 
 */
module RSA_Interfaccia(rfd, dav_, ir, ior_, reset_);
	input dav_, ior_;
	output ir, rfd;
	
	reg [1:0] STAR;
	
	parameter S0 = 2'B00, S1 = 2'B01, S2 = 2'B10, S3 = 2'B11;
	
	assign {rfd, ir} = CN2(STAR);
	
	always @(dav_ or ior_ or reset_)
		if (reset_ == 0) STAR <= S0;
		else casex (STAR)
			S0: STAR <= ({dav_, ior_} == 'B01) ? S1 : S0;
			S1: STAR <= ({dav_, ior_} == 'B00) ? S2 : S1;
			S2: STAR <= ({dav_, ior_} == 'B01) ? S3 : S2;
			S3: STAR <= ({dav_, ior_} == 'B11) ? S0 : S3;
		endcase
endmodule

function [1:0] CN2;
	input [1:0] star;
	parameter S0 = 2'B00, S1 = 2'B01, S2 = 2'B10, S3 = 2'B11;
	
	casex (STAR)
		S0: CN2 = 'B10;
		S1: CN2 = 'B01;
		S2: CN2 = 'B01;
		S3: CN2 = 'B00;
	endcase
endfunction

2012-02-02-esercizio2-separazione.v

/**
 * Feder1co 5oave
 * Separazione in parte operativa e parte controllo
 */
module XXX(p, reset_, mw_, a7_a0, d7_d0, ior_, ir);
	input p, _reset, ir;
	output mw_, ior_;
	output [7:0] a7_a0;
	inout [7:0] d7_d0;
	
	// variabili di condizionamento
	wire cd1, cd2;
	
	// variabili di comando
	wire [1:0] cm1, cm2;
	wire cm3, cm4, cm5, cm6;
	
	Parte_Controllo PC(p, reset_, cd1, cd2, ...);
	Parte_Operativa PO(p, reset_, mw_, a7_a0, d7_d0, ior_, ir, cd1, cd2, ...);
endmodule

module Parte_Controllo(p, reset_, cd1, cd2, cm1, cm2, cm3, cm4, cm5, cm6);
	input p, reset_, cd1, cd2;
	
	
	reg [3 :0] STAR;
	
	// variabili di comando
	output [1:0] cm1, cm2;
	output cm3, cm4, cm5, cm6;
	assign cm1 = (STAR == S7) ? 'B00 : (STAR == S8) ? 'B11 : 'B01;
	assign cm2 = (STAR == S0) ? 'B00 :
	             (STAR == S4) ? 'B00 :
				 (STAR == S2) ? 'B11 :
				 (STAR == S6) ? 'B11 : 'B10;
	assign cm3 = (STAR == S2) ? 1 : 0;
	assign cm4 = (STAR == S6) ? 1 : 0;
	assign cm5 = (STAR == S7) ? 1 : 0;
	assign cm6 = (STAR == S9) ? 1 : 0;
	
	parameter S0 = 'H0, S1 = 'H1, S2 = 'H2, S3 = 'H3, S4 = 'H4, S5 = 'H5,
	          S6 = 'H6, S7 = 'H7, S8 = 'H8, S9 = 'H9, STOP = 'HA;

	always @(posedge p or negedge reset_)
		if (reset_ == 0) STAR = S0;
		else #3
			casex (STAR)
				S0: STAR <= (cd1 == 1) ? S1 : S0; // aspetto ir -> 1
				S1: STAR <= S2; // wait
				S2: STAR <= S3;
				S3: STAR <= (cd1 == 1) ? S3 : S4; // aspetto ir -> 0
				S4: STAR <= (cd1 == 1) ? S5 : S4; // aspetto ir -> 1
				S5: STAR <= S6; // wait
				S6: STAR <= S7;
				S7: STAR <= S8;
				S8: STAR <= (cd2 == 1) ? STOP : S9;
				S9: STAR <= S0;
				STOP: STAR <= STOP;
			endcase
endmodule

module Parte_Operativa(p, reset_, mw_, a7_a0, d7_d0, ior_, ir, cd1, cd2, cm1, cm2, cm3, cm4, cm5, cm6);
	input p, reset_, ir, ...;
	input [7:0] a7_a0;
	output mw_, ior_;
	inout [7:0] d7_d0;
	
	// variabili di comando
	input [1:0] cm1, cm2;
	input cm3, cm4, cm5, cm6;
	
	reg [7:0] MAR, DATA;
	reg [9:0] COUNT;
	reg MW_, DIR, IOR_;
	
	assign d7_d0 = (DIR == 1) ? DATA : 'HZZ; // forchetta sul bus dati
	assign a7_a0 = MAR; // bus indirizzi
	assign mw_ = MW_;
	assign ior_ = IOR_;
	
	// variabili di condizionamento
	output cd1, cd2;
	assign cd1 = ir;
	assign cd2 = (COUNT == 1023) ? 1 : 0;
	
	// registro MW_
	always @(posedge p or negedge reset_)
		if (reset_ == 0)
			MW_ <= 1;
		else #3
			casex (cm1)
				'B00: MW_ <= 0;
				'B11: MW_ <= 1;
				default: MW_ <= MW_;
			endcase
	
	// registro IOR_
	always @(posedge p or negedge reset_)
		if (reset_ == 0)
			IOR_ <= 1;
		else #3
			casex (cm2)
				'B00: IOR_ <= ~ir;
				'B01: IOR_ <= 1;
				default: IOR_ <= IOR_;
			endcase
	
	// registro MAR
	always @(posedge p) #3
		MAR <= (cm3 == 1) ? a7_a0 : MAR;
		
	// registro DATA
	always @(posedge p) #3
		DATA <= (cm4 == 1) ? d7_d0 : DATA;
	
	// registro DIR
	always @(posedge p or negedge reset_)
		DIR <= reset_ & cm5;
		
	// registro COUNT
	always @(posedge p or negedge reset_)
		if (reset_ == 0) COUNT <= 0;
		else #3 COUNT <= (cm6 == 1) ? (COUNT + 1) : COUNT;
endmodule

2012-02-02-esercizio2.v

/**
 * Feder1co 5oave
 * Descrizione in un unico blocco
 */
module XXX(p, reset_, mw_, a7_a0, d7_d0, ior_, ir);
	input p, reset_, ir;
	output mw_, ior_;
	output [7:0] a7_a0;
	inout [7:0] d7_d0;
	
	reg MW_, IOR_, DIR;
	reg [7:0] MAR, DATA;
	reg [9:0] COUNT;
	reg [3:0] STAR;
	
	parameter
	
	assign d7_d0 = (DIR == 1) ? DATA : 'HZZ; // forchetta sul bus dati
	assign mw_ = MW_;
	assign ior_ = IOR_;
	assign a7_a0 = MAR;
	
	
	always @(posedge p or negedge reset_)
		if (reset_ == 0) begin
			STAR <= S0; MW_ <= 1; IOR_ <= 1; DIR <= 0; COUNT <= 0;
		end else #3
			casex (STAR)
				S0: begin STAR <= (ir==1) ? S1 : S0; IOR_ <= (ir==1) ? 0 : 1; end
				S1: STAR <= S2; // wait
				S2: begin MAR <= d7_d0; IOR_ <= 1; STAR <= S3; end
				S3: STAR <= (ir==1) ? S4 : S3;
				S4: begin STAR <= (ir==1) ? S5 : S4; IOR_ <= (ir==1) ? 0 : 1; end
				S5: STAR <= S6; // wait
				S6: begin IOR_ <= 1; DATA <= d7_d0; STAR <= S7; end
				S7: begin DIR <= 1; MW_ <= 0; STAR <= S8; end
				S8: begin MW_ <= 1; STAR <= (COUNT==1023) ? STOP : S9; end
				S9: begin DIR <= 0; COUNT <= (COUNT + 1); STAR <= S0; end
				STOP: STAR <= STOP;
			endcase
endmodule