vhdl vga sample

counter.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera;
use altera.altera_syn_attributes.all;

entity Counter is
	generic (Size:Integer);
	port (
		Step, Reset: in std_logic;
		State: buffer std_logic_vector (Size-1 downto 0));
end Counter;

architecture Counter of Counter is
begin
	process(Reset, Step, State)
	begin
		if Reset = '1' then
			State <= (State'range => '0');
		elsif rising_edge(Step) then
			State <= std_logic_vector(unsigned(State) + 1);
		else
			State <= State;
		end if;
	end process;
end;

helloworld.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library pixclk25175;
use pixclk25175.all;

entity helloworld is
	port (
		CLOCK_50 : in std_logic;
		KEY : in std_logic_vector (1 downto 0);
		GPIO : out std_logic_vector (7 downto 0);
		LED : out std_logic_vector (7 downto 0));
end helloworld;

architecture ppl_type of helloworld is

constant HFrontPorch  : integer := 16;
constant HVisibleArea : integer := 640;
constant HBackPorch   : integer := 48;
constant HSyncPulse   : integer := 96;

constant VFrontPorch  : integer := 10;
constant VVisibleArea : integer := 480;
constant VBackPorch   : integer := 33;
constant VSyncPulse   : integer := 2;

constant HTotal : integer := HBackPorch + HVisibleArea + HFrontPorch + HSyncPulse;
constant VTotal : integer := VBackPorch + VVisibleArea + VFrontPorch + VSyncPulse;

signal pixclk: std_logic;
signal horiz_overflow, vert_overflow: std_logic;
signal HCounter: std_logic_vector (9 downto 0);
signal VCounter: std_logic_vector (9 downto 0);
-- signal FCounter: std_logic_vector (7 downto 0);
signal ShiftCounter: std_logic_vector (4 downto 0);
signal ShiftReset: std_logic;
signal HCounter_reset, VCounter_reset: std_logic;
signal UNKEY: std_logic_vector (1 downto 0);
signal HSYNC, VSYNC: std_logic;
signal InHWindow, InVWindow: boolean;
signal RED0, RED1, GREEN0, GREEN1, BLUE0, BLUE1: std_logic;
signal MonitorOn: std_logic;
begin
	UNKEY <= not KEY;
	counter_shift: entity work.Counter
		generic map (Size => 5)
		port map (
			Step => UNKEY(0),
			State => ShiftCounter,
			Reset => ShiftReset);
	monitor_switch: entity work.Counter
		generic map (Size => 1)
		port map (
			Step => UNKEY(1),
			State(0) => MonitorOn,
			Reset => '0');
	process(ShiftCounter)
	begin
		ShiftReset <= '0';
		if (unsigned(ShiftCounter) = 28) then
			ShiftReset <= '1';
		end if;
	end process;
	counter_horiz: entity work.Counter
		generic map (Size => 10)
		port map (
			Step => pixclk,
			State => HCounter,
			Reset => HCounter_reset);
	counter_vert: entity work.Counter
		generic map (Size => 10)
		port map (
			Step => horiz_overflow,
			State => VCounter,
			Reset => VCounter_reset);
	pixclk_ent: entity pixclk25175.pixclk25175
		port map (
			inclk0 => CLOCK_50,
			c0 => pixclk);
--	counter_frame: entity work.Counter
--		generic map (Size => 8)
--		port map (
--			Step => vert_overflow,
--			State => FCounter,
--			Reset => UNKEY(1));
	process(HCounter)
	begin
		horiz_overflow <= '0';
		if (unsigned(HCounter) = HTotal) then
			horiz_overflow <= '1';
		end if;
	end process;
	
	-- hsync
	process(HCounter)
	begin
		HSYNC <= '1';
		if (unsigned(HCounter) >= HTotal - HSyncPulse) then
			HSYNC <= '0';
		end if;
	end process;
	
	-- vsync
	process(VCounter)
	begin
		VSYNC <= '1'; -- negative sync
		if (unsigned(VCounter) >= VTotal - VSyncPulse) then
			VSYNC <= '0';
		end if;
	end process;
	
	-- h/v windows
	process(HCounter)
	begin
		InHWindow <= false;
		if (unsigned(HCounter) >= HBackPorch and unsigned(HCounter) < HBackPorch + HVisibleArea) then
			InHWindow <= true;
		end if;
	end process;
	
	process(VCounter)
	begin
		InVWindow <= false;
		if (unsigned(VCounter) >= VBackPorch and unsigned(VCounter) < VBackPorch + VVisibleArea) then
			InVWindow <= true;
		end if;
	end process;
	
	process(horiz_overflow)
	begin
		if (HCounter_reset = '1') then
			HCounter_reset <= '0';
		elsif (rising_edge(horiz_overflow)) then
			HCounter_reset <= '1';
		end if;
	end process;
	
	process(VCounter)
	begin
		vert_overflow <= '0';
		if (unsigned(VCounter) = VTotal) then
			vert_overflow <= '1';
		end if;
	end process;
	
	process(InHWindow,InVWindow,HCounter,VCounter)
	variable r_index, g_index, b_index: integer;
	begin
		RED0 <= '0';
		RED1 <= '0';
		GREEN0 <= '0';
		GREEN1 <= '0';
		BLUE0 <= '0';
		BLUE1 <= '0';
		if (InVWindow and InHWindow) then
			r_index := to_integer(unsigned(ShiftCounter) mod 3);
			g_index := to_integer((unsigned(ShiftCounter) / 3) mod 3);
			b_index := to_integer(unsigned(ShiftCounter) / 9);
			RED0 <= HCounter(r_index * 2 + 0) xor VCounter(r_index * 2 + 0);
			RED1 <= HCounter(r_index * 2 + 1) xor VCounter(r_index * 2 + 1);
			GREEN0 <= HCounter(g_index * 2 + 0) xor VCounter(g_index * 2 + 0);
			GREEN1 <= HCounter(g_index * 2 + 1) xor VCounter(g_index * 2 + 1);
			BLUE0 <= HCounter(b_index * 2 + 0) xor VCounter(b_index * 2 + 0);
			BLUE1 <= HCounter(b_index * 2 + 1) xor VCounter(b_index * 2 + 1);
		end if;
	end process;
	
	process(vert_overflow, VCounter_reset)
	begin
		if VCounter_reset = '1' then
			VCounter_reset <= '0';
		elsif (rising_edge(vert_overflow)) then
			VCounter_reset <= '1';
		end if;
	end process;
	-- LED <= FCounter;
	LED(4 downto 0) <= ShiftCounter;
	GPIO(0) <= HSYNC and MonitorOn;
	GPIO(1) <= VSYNC and MonitorOn;
	GPIO(2) <= RED1;
	GPIO(3) <= RED0;
	GPIO(4) <= GREEN1;
	GPIO(5) <= GREEN0;
	GPIO(6) <= BLUE1;
	GPIO(7) <= BLUE0;
end;