IF-STRUCTURE IN C-LANGUAGE TO ASSEMBLY

main_if_structure.asm

; FERNANDO LÓPEZ RAMÍREZ - A07144620
;****************** HEADER FILES ******************************
    list	    p=18f4550        ; list directive to define processor
    #include	    "p18f4550.inc"

;***************** CONFIGURATION BITS ******************************
    
; PIC18F4550 Configuration Bit Settings

; ASM source line config statements

;#include "p18F4550.inc"

; CONFIG1L
  CONFIG  PLLDIV = 5            ; PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
  CONFIG  CPUDIV = OSC3_PLL4    ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /3][96 MHz PLL Src: /4])
  CONFIG  USBDIV = 2            ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)

; CONFIG1H
  CONFIG  FOSC = HSPLL_HS       ; Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  CONFIG  IESO = OFF            ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
  CONFIG  PWRT = ON             ; Power-up Timer Enable bit (PWRT enabled)
  CONFIG  BOR = OFF             ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
  CONFIG  BORV = 3              ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
  CONFIG  VREGEN = OFF          ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)

; CONFIG2H
  CONFIG  WDT = OFF             ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
  CONFIG  WDTPS = 32768         ; Watchdog Timer Postscale Select bits (1:32768)

; CONFIG3H
  CONFIG  CCP2MX = OFF          ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
  CONFIG  PBADEN = OFF          ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
  CONFIG  LPT1OSC = OFF         ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
  CONFIG  MCLRE = ON            ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

; CONFIG4L
  CONFIG  STVREN = OFF          ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
  CONFIG  LVP = OFF             ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
  CONFIG  ICPRT = OFF           ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
  CONFIG  XINST = OFF           ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

; CONFIG5L
  CONFIG  CP0 = OFF             ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
  CONFIG  CP1 = OFF             ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
  CONFIG  CP2 = OFF             ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
  CONFIG  CP3 = OFF             ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

; CONFIG5H
  CONFIG  CPB = OFF             ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
  CONFIG  CPD = OFF             ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

; CONFIG6L
  CONFIG  WRT0 = OFF            ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
  CONFIG  WRT1 = OFF            ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
  CONFIG  WRT2 = OFF            ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
  CONFIG  WRT3 = OFF            ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

; CONFIG6H
  CONFIG  WRTC = OFF            ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
  CONFIG  WRTB = OFF            ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
  CONFIG  WRTD = OFF            ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

; CONFIG7L
  CONFIG  EBTR0 = OFF           ; Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
  CONFIG  EBTR1 = OFF           ; Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
  CONFIG  EBTR2 = OFF           ; Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
  CONFIG  EBTR3 = OFF           ; Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

; CONFIG7H
  CONFIG  EBTRB = OFF           ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

  
;**************** DESCRIPTION OF THE CODE *********************************
    ; THE IMPLEMENTATION OF AN IF STRUCTURE IN C-LANGUAGE IS DEMONSTRATED:
    ; if((x-y)<3) {
    ;	a=b-c;
    ;	x=0; 
    ; } 
    ; else { 
    ;	y=0;
    ;	d=e+f+g;
    ; } 
  
;**************** VARIABLES DEFINITION *********************************
    CONSTANT	THREE = 0x3
    RegA   EQU	0X001
    RegB   EQU	0X002
    RegC   EQU	0X003
    RegD   EQU	0X004
    RegE   EQU	0X005
    RegF   EQU	0X006
    RegG   EQU	0X007
    RegX   EQU	0X008
    RegY   EQU	0X009
    RegTmp EQU 0x00A
     
;;**************** MAIN CODE *****************************
    ORG 0X000	; Reset Vector
    GOTO MAIN	; Go to the Main Routine

INITIALIZE:
    MOVLW 0X04
    MOVWF RegB	; RegB = 0x04
    MOVLW 0X02
    MOVWF RegC	; RegC = 0x02
    MOVLW 0X01
    MOVWF RegE	; RegE = 0x01
    MOVLW 0X01
    MOVWF RegF	; RegF = 0x01
    MOVLW 0X01
    MOVWF RegG	; RegG = 0x01
    MOVLW 0X05
    MOVWF RegX	; RegX = 0x05
    MOVLW 0X01
    MOVWF RegY	; RegY = 0x01
    
    BSF OSCCON, IRCF0	; Internal oscillator running at 4 MHz
    BSF OSCCON, IRCF1	
    BSF OSCCON, IRCF2
    
    RETURN

MAIN:
    CALL    INITIALIZE
    MOVF    RegY, W	; Regx -> Accum
    SUBWF   RegX, W	; (RegX - RegY) -> Accum
    MOVWF   RegTmp	; RegTmp = (RegX - RegY)
    CPFSGT  THREE	; (3 > RegTmp)
    GOTO    FALSE_CASE
    GOTO    TRUE_CASE
    
LOOP:
    GOTO LOOP

FALSE_CASE:
    CLRF    RegY	; RegY = 0x00
    MOVF    RegE, W	; (RegE) -> Accum
    ADDWF   RegF, W	; (RegE + RegF) -> Accum
    ADDWF   RegG, W	; (RegE + RegF + RegG) -> Accum
    MOVWF   RegD	; RegD = (RegE + RegF + RegG)
    GOTO    LOOP

TRUE_CASE:
    MOVF    RegC, W    ; RegC -> Accum
    SUBWF   RegB, W    ; (RegB - RegC) -> Accum
    MOVWF   RegA       ; RegA = (RegB - RegC)
    CLRF    RegX       ; RegX = 0x00
    GOTO    LOOP
    
    END