SWITCH-CASE STRUCTURE IN C-LANGUAGE TO ASSEMBLY

main_sw_structure.asm

; FERNANDO LÓPEZ RAMÍREZ - A07144620
;****************** HEADER FILES ******************************
    list	    p=18f4550        ; list directive to define processor
    #include	    "p18f4550.inc"

;***************** CONFIGURATION BITS ******************************
    
; PIC18F4550 Configuration Bit Settings

; ASM source line config statements

;#include "p18F4550.inc"

; CONFIG1L
  CONFIG  PLLDIV = 5            ; PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
  CONFIG  CPUDIV = OSC3_PLL4    ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /3][96 MHz PLL Src: /4])
  CONFIG  USBDIV = 2            ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)

; CONFIG1H
  CONFIG  FOSC = HSPLL_HS       ; Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  CONFIG  IESO = OFF            ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
  CONFIG  PWRT = ON             ; Power-up Timer Enable bit (PWRT enabled)
  CONFIG  BOR = OFF             ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
  CONFIG  BORV = 3              ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
  CONFIG  VREGEN = OFF          ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)

; CONFIG2H
  CONFIG  WDT = OFF             ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
  CONFIG  WDTPS = 32768         ; Watchdog Timer Postscale Select bits (1:32768)

; CONFIG3H
  CONFIG  CCP2MX = OFF          ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
  CONFIG  PBADEN = OFF          ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
  CONFIG  LPT1OSC = OFF         ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
  CONFIG  MCLRE = ON            ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

; CONFIG4L
  CONFIG  STVREN = OFF          ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
  CONFIG  LVP = OFF             ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
  CONFIG  ICPRT = OFF           ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
  CONFIG  XINST = OFF           ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

; CONFIG5L
  CONFIG  CP0 = OFF             ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
  CONFIG  CP1 = OFF             ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
  CONFIG  CP2 = OFF             ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
  CONFIG  CP3 = OFF             ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

; CONFIG5H
  CONFIG  CPB = OFF             ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
  CONFIG  CPD = OFF             ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

; CONFIG6L
  CONFIG  WRT0 = OFF            ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
  CONFIG  WRT1 = OFF            ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
  CONFIG  WRT2 = OFF            ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
  CONFIG  WRT3 = OFF            ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

; CONFIG6H
  CONFIG  WRTC = OFF            ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
  CONFIG  WRTB = OFF            ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
  CONFIG  WRTD = OFF            ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

; CONFIG7L
  CONFIG  EBTR0 = OFF           ; Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
  CONFIG  EBTR1 = OFF           ; Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
  CONFIG  EBTR2 = OFF           ; Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
  CONFIG  EBTR3 = OFF           ; Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

; CONFIG7H
  CONFIG  EBTRB = OFF           ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

  
;**************** DESCRIPTION OF THE CODE *********************************
    ; THE IMPLEMENTATION OF A SWITCH-CASE STRUCTURE IN C-LANGUAGE IS DEMONSTRATED:
    ;
    ;	switch(RegPortD) { 
    ;	    case 0x01: RegTmp = add_asm(a, b);
    ;		break; 
    ;	    case 0x02: RegTmp = sub_asm(a,b)
    ;		break; 
    ;	    default: RegTmp = dec_asm(a);
    ;	}
    ;
    ;	char add_asm(char a, char b) { 
    ;	    char c;
    ;	    c = a + b;
    ;	    return c;
    ;	} 
    ;
    ;	char sub_asm(char a, char b) {
    ;	    char c;
    ;	    c = a - b;
    ;	    return c;
    ;	}
    ;
    ;	char decr_asm(char a,) {
    ;	    char c; 
    ;	    c = a – 1;
    ;	    return c;
    ;	}
  
;**************** VARIABLES DEFINITION *********************************
    RegA   EQU	0X001
    RegB   EQU	0X002
    RegC   EQU	0X003
    RegTmp EQU	0x004
    RegPortD EQU 0X005
     
;**************** MAIN CODE *****************************
    ORG 0X000	; Reset Vector
    GOTO MAIN	; Go to the Main Routine

INITIALIZE:
    MOVLW 0XF
    MOVWF ADCON1    ; PORTD are digital
    SETF  TRISD	    ; PORTD is an input port
    ; All GPRs are initialized to zero
    MOVLW 0X05
    MOVWF RegA	; RegA = 0x05
    MOVLW 0X01
    MOVWF RegB	; RegB = 0x01
    CLRF RegC
    CLRF RegTmp
    CLRF RegPortD
    ; Internal oscillator running at 4 MHz
    BSF OSCCON, IRCF0
    BSF OSCCON, IRCF1	
    BSF OSCCON, IRCF2
    
    RETURN

MAIN:
    CALL    INITIALIZE
    
LOOP:
    MOVF  RegC, W    ; The result that is in RegC, is moved to the Accum
    MOVWF RegTmp    ; The value of the Accum now is saved in RegTmp
    MOVF  PORTD, W   ; Read a PORT: PORTD -> Accum
    MOVWF RegPortD  ; Save in the register
    ; CASE 1
    MOVLW 0X01
    SUBWF RegPortD, W	; RegPortD is tested against 0X01
    BZ	  ADD_ASM	; Executes when z=1, indicating RegPortD=0x01
    ; CASE 2
    MOVLW 0X02
    SUBWF RegPortD, W	; RegPortD is tested against 0X01
    BZ	  SUB_ASM	; Executes when z=1, indicating RegPortD=0x01
    ; DEFAULT
    BRA	  DEC_ASM	; None of the two cases are true, then default executes
    ; No matter what is the result, everything is saved in RegTmp

ADD_ASM:
    MOVF    RegA, W	; RegA -> Accum
    ADDWF   RegB, W	; (RegA + RegB) -> Accum
    MOVWF   RegC        ; RegC = (RegA + RegB)
    GOTO    LOOP
    
SUB_ASM:
    MOVF    RegB, W	; RegA -> Accum
    SUBWF   RegA, W	; (RegA - RegB) -> Accum
    MOVWF   RegC        ; RegC = (RegA + RegB)
    GOTO    LOOP
    
DEC_ASM:
    DECF    RegA, F	; RegA is decremented
    MOVWF   RegC        ; RegC = (RegA - 1)
    GOTO    LOOP
    
    END