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specs diff 1.4 to 1.5
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--- dcpu16.txt 2012-04-26 13:57:37.477152465 +0200 | |
+++ dcpu16_1_5.txt 2012-04-26 13:57:12.209965926 +0200 | |
@@ -1,6 +1,6 @@ | |
DCPU-16 Specification | |
Copyright 1985 Mojang | |
-Version 1.4 | |
+Version 1.5 | |
@@ -80,17 +80,18 @@ | |
2 | 0x05 | MLI b, a | like MUL, but treat b, a as signed | |
3 | 0x06 | DIV b, a | sets b to b/a, sets EX to ((b<<16)/a)&0xffff. if a==0, | |
| | | sets b and EX to 0 instead. (treats b, a as unsigned) | |
- 3 | 0x07 | DVI b, a | like DIV, but treat b, a as signed | |
+ 3 | 0x07 | DVI b, a | like DIV, but treat b, a as signed. Rounds towards 0 | |
3 | 0x08 | MOD b, a | sets b to b%a. if a==0, sets b to 0 instead. | |
- 1 | 0x09 | AND b, a | sets b to b&a | |
- 1 | 0x0a | BOR b, a | sets b to b|a | |
- 1 | 0x0b | XOR b, a | sets b to b^a | |
- 2 | 0x0c | SHR b, a | sets b to b>>>a, sets EX to ((b<<16)>>a)&0xffff | |
+ 3 | 0x09 | MDI b, a | like MOD, but treat b, a as signed. Rounds towards 0 | |
+ 1 | 0x0a | AND b, a | sets b to b&a | |
+ 1 | 0x0b | BOR b, a | sets b to b|a | |
+ 1 | 0x0c | XOR b, a | sets b to b^a | |
+ 2 | 0x0d | SHR b, a | sets b to b>>>a, sets EX to ((b<<16)>>a)&0xffff | |
| | | (logical shift) | |
- 2 | 0x0d | ASR b, a | sets b to b>>a, sets EX to ((b<<16)>>>a)&0xffff | |
+ 2 | 0x0e | ASR b, a | sets b to b>>a, sets EX to ((b<<16)>>>a)&0xffff | |
| | | (arithmetic shift) (treats b as signed) | |
- 2 | 0x0e | SHL b, a | sets b to b<<a, sets EX to ((b<<a)>>16)&0xffff | |
- 2 | 0x0f | STI b, a | sets b to a, then increases I and J by 1 | |
+ 2 | 0x0f | SHL b, a | sets b to b<<a, sets EX to ((b<<a)>>16)&0xffff | |
+ | |
2+| 0x10 | IFB b, a | performs next instruction only if (b&a)!=0 | |
2+| 0x11 | IFC b, a | performs next instruction only if (b&a)==0 | |
2+| 0x12 | IFE b, a | performs next instruction only if b==a | |
@@ -107,8 +108,8 @@ | |
| | | flow, 0x0 otherwise | |
- | 0x1c | - | | |
- | 0x1d | - | | |
- - | 0x1e | - | | |
- - | 0x1f | - | | |
+ 2 | 0x1e | STI b, a | sets b to a, then increases I and J by 1 | |
+ 2 | 0x1f | STD b, a | sets b to a, then decreases I and J by 1 | |
---+------+----------+---------------------------------------------------------- | |
* The branching opcodes take one cycle longer to perform if the test fails | |
@@ -136,8 +137,11 @@ | |
4 | 0x08 | INT a | triggers a software interrupt with message a | |
1 | 0x09 | IAG a | sets a to IA | |
1 | 0x0a | IAS a | sets IA to a | |
- - | 0x0b | - | | |
- - | 0x0c | - | | |
+ 3 | 0x0b | IAP a | if IA is 0, does nothing, otherwise pushes IA to the stack, | |
+ | | | then sets IA to a | |
+ 2 | 0x0c | IAQ a | if a is nonzero, interrupts will be added to the queue | |
+ | | | instead of triggered. if a is zero, interrupts will be | |
+ | | | triggered as normal again | |
- | 0x0d | - | | |
- | 0x0e | - | | |
- | 0x0f | - | | |
@@ -166,7 +170,9 @@ | |
=== INTERRUPTS ================================================================= | |
-The DCPU-16 will perform at most one interrupt between each instruction. | |
+The DCPU-16 will perform at most one interrupt between each instruction. If | |
+multiple interrupts are triggered at the same time, they are added to a queue. | |
+If the queue grows longer than 256 interrupts, the DCPU-16 will catch fire. | |
When IA is set to something other than 0, interrupts triggered on the DCPU-16 | |
will push PC to the stack, followed by pushing A to the stack, then set the PC | |
@@ -180,8 +186,8 @@ | |
The DCPU-16 has no way of knowing when an interrupt handler has finished, so if | |
an interrupt is triggered while an interrupt is being handled, the handler will | |
-get called twice. Calling IAS 0 immediately at the start of the handler will | |
-reliably prevent multiple concurrent interrupts. | |
+get called twice. Calling IAS 0 or IAQ 1 immediately at the start of the handler | |
+will reliably prevent multiple concurrent interrupts. |
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