Test 16b x 16b -> 32b multiplier

mult.sv

module mult(
  input logic clk_i,
  input logic rst_ni,
  input logic signed [15:0] a_i,
  input logic signed [15:0] b_i,
  output logic signed [31:0] c_o
);

  logic signed [15:0] a_q;
  logic signed [15:0] b_q;
  logic signed [31:0] c_d, c_q;
  logic signed [31:0] prod;
  always_ff @(posedge clk_i or negedge rst_ni)
  begin
    if(~rst_ni) begin
      a_q <= '0;
      b_q <= '0;
      c_q <= '0;
    end
    else begin
      a_q <= a_i;
      b_q <= b_i;
      c_q <= c_d;
    end
  end

  assign prod = a_q * b_q;
  assign c_d = prod + c_q;
  assign c_o = c_q;

endmodule