Nyuzi Make error output

nyuzi_make_error.txt

I copied my error messages and pasted them here. They are from 2 commits: 

1. 56a119: membench: let compiler unroll loops
2. 8aba98: hardware: enable more warnings and fix them. Other cleanup.

The 1. is the latest commit at the time. The 2. is the 1st commit it starts to cannot be built. 

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commit 56a119846c24934eaf4732b0cf63dc164f3ffe71
Author: Jeff Bush <jeffbush001@gmail.com>
Date:   Fri Sep 4 08:37:39 2015 -0700

    membench: let compiler unroll loops

fulcronz@textbook:~/Projects/NyuziProcessor$ make
cd hardware/ && make
make[1]: Entering directory '/home/fulcronz/Projects/NyuziProcessor/hardware'
verilator --unroll-count 512 --assert -Werror-IMPLICIT -Wwarn-syncasyncnet -Wwarn-blkseq -Icore -y testbench -y fpga/common --cc testbench/verilator_tb.sv --exe testbench/verilator_main.cpp -DSIMULATION=1 
%Warning-WIDTH: core/fp_execute_stage1.sv:139: Operator SUB expects 6 bits on the LHS, but LHS's SEL generates 8 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: core/fp_execute_stage1.sv:139: Operator SUB expects 6 bits on the RHS, but RHS's CONST '8'h96' generates 8 bits.
%Warning-WIDTH: fpga/common/sdram_controller.sv:355: Operator SUB expects 3 bits on the LHS, but LHS's VARREF 'SDRAM_BURST_LENGTH' generates 32 or 4 bits.
%Warning-WIDTH: fpga/common/sdram_controller.sv:371: Operator SUB expects 3 bits on the LHS, but LHS's VARREF 'SDRAM_BURST_LENGTH' generates 32 or 4 bits.
%Error: Exiting due to 4 warning(s)
%Error: Command Failed /usr/bin/verilator_bin --unroll-count 512 --assert -Werror-IMPLICIT -Wwarn-syncasyncnet -Wwarn-blkseq -Icore -y testbench -y fpga/common --cc testbench/verilator_tb.sv --exe testbench/verilator_main.cpp '-DSIMULATION=1'
Makefile:30: recipe for target '../bin/verilator_model' failed
make[1]: *** [../bin/verilator_model] Error 10
make[1]: Leaving directory '/home/fulcronz/Projects/NyuziProcessor/hardware'
Makefile:21: recipe for target 'all' failed
make: *** [all] Error 2

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commit 8aba9840a9c94e9ccd8b307928c04d284967551c
Author: Jeff Bush <jeffbush001@gmail.com>
Date:   Sun Aug 16 09:33:09 2015 -0700

    hardware: enable more warnings and fix them. Other cleanup.
    
    - Fix places where reset was used synchrnously (all sim code)
    - Use _unused as signal name where appropriate (it is ignored by verilator)
    - Remove a bunch of unused signal defs
    - Make trace queue in testbench use non-blocking assignments
    
fulcronz@textbook:~/Projects/NyuziProcessor$ make
cd hardware/ && make
make[1]: Entering directory '/home/fulcronz/Projects/NyuziProcessor/hardware'
verilator --unroll-count 512 --assert -Werror-IMPLICIT -Wwarn-syncasyncnet -Wwarn-blkseq -Icore -y testbench -y fpga/common --cc testbench/verilator_tb.sv --exe testbench/verilator_main.cpp -DSIMULATION=1 
%Warning-WIDTH: core/fp_execute_stage1.sv:139: Operator SUB expects 6 bits on the LHS, but LHS's SEL generates 8 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: core/fp_execute_stage1.sv:139: Operator SUB expects 6 bits on the RHS, but RHS's CONST '8'h96' generates 8 bits.
%Warning-WIDTH: fpga/common/sdram_controller.sv:355: Operator SUB expects 3 bits on the LHS, but LHS's VARREF 'SDRAM_BURST_LENGTH' generates 32 or 4 bits.
%Warning-WIDTH: fpga/common/sdram_controller.sv:371: Operator SUB expects 3 bits on the LHS, but LHS's VARREF 'SDRAM_BURST_LENGTH' generates 32 or 4 bits.
%Error: Exiting due to 4 warning(s)
%Error: Command Failed /usr/bin/verilator_bin --unroll-count 512 --assert -Werror-IMPLICIT -Wwarn-syncasyncnet -Wwarn-blkseq -Icore -y testbench -y fpga/common --cc testbench/verilator_tb.sv --exe testbench/verilator_main.cpp '-DSIMULATION=1'
Makefile:30: recipe for target '../bin/verilator_model' failed
make[1]: *** [../bin/verilator_model] Error 10
make[1]: Leaving directory '/home/fulcronz/Projects/NyuziProcessor/hardware'
Makefile:21: recipe for target 'all' failed
make: *** [all] Error 2

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