SRAMGenericModule.v

module SRAMGenericModule(
  input        clock,
  input        reset,
  output       io_dataPath_write_in_data_ready,
  input        io_dataPath_write_in_data_valid,
  input  [7:0] io_dataPath_write_in_data_bits,
  output [7:0] io_dataPath_read_out_Data,
  input        io_ctrlPath_write_fin,
  input        io_ctrlPath_read_en,
  input        io_ctrlPath_read_index_inc
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] dataSPad [0:15999]; // @[CoreArray.scala 175:48]
  wire [7:0] dataSPad__T_15_data; // @[CoreArray.scala 175:48]
  wire [13:0] dataSPad__T_15_addr; // @[CoreArray.scala 175:48]
  wire [7:0] dataSPad__T_9_data; // @[CoreArray.scala 175:48]
  wire [13:0] dataSPad__T_9_addr; // @[CoreArray.scala 175:48]
  wire  dataSPad__T_9_mask; // @[CoreArray.scala 175:48]
  wire  dataSPad__T_9_en; // @[CoreArray.scala 175:48]
  reg  dataSPad__T_15_en_pipe_0;
  reg [13:0] dataSPad__T_15_addr_pipe_0;
  reg [13:0] padWriteIndexReg; // @[CoreArray.scala 169:39]
  reg [13:0] padReadIndexReg; // @[CoreArray.scala 170:38]
  wire  writeFire = io_dataPath_write_in_data_ready & io_dataPath_write_in_data_valid; // @[Decoupled.scala 40:37]
  wire [7:0] dataWire = dataSPad__T_15_data; // @[CoreArray.scala 168:28 CoreArray.scala 202:12]
  wire  _T_1 = $signed(dataWire) == 8'sh0; // @[CoreArray.scala 179:28]
  wire  _T_2 = _T_1 & io_ctrlPath_read_index_inc; // @[CoreArray.scala 179:36]
  wire  _T_3 = padReadIndexReg != 14'h0; // @[CoreArray.scala 179:72]
  wire  readWrapWire = _T_2 & _T_3; // @[CoreArray.scala 179:52]
  wire [13:0] _T_6 = padWriteIndexReg + 14'h1; // @[CoreArray.scala 185:79]
  wire [13:0] _T_11 = padReadIndexReg + 14'h1; // @[CoreArray.scala 197:40]
  assign dataSPad__T_15_addr = dataSPad__T_15_addr_pipe_0;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign dataSPad__T_15_data = dataSPad[dataSPad__T_15_addr]; // @[CoreArray.scala 175:48]
  `else
  assign dataSPad__T_15_data = dataSPad__T_15_addr >= 14'h3e80 ? _RAND_1[7:0] : dataSPad[dataSPad__T_15_addr]; // @[CoreArray.scala 175:48]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign dataSPad__T_9_data = io_dataPath_write_in_data_bits;
  assign dataSPad__T_9_addr = padWriteIndexReg;
  assign dataSPad__T_9_mask = 1'h1;
  assign dataSPad__T_9_en = io_dataPath_write_in_data_ready & io_dataPath_write_in_data_valid;
  assign io_dataPath_write_in_data_ready = 1'h1; // @[CoreArray.scala 183:25]
  assign io_dataPath_read_out_Data = dataSPad__T_15_data; // @[CoreArray.scala 203:29]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16000; initvar = initvar+1)
    dataSPad[initvar] = _RAND_0[7:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  dataSPad__T_15_en_pipe_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  dataSPad__T_15_addr_pipe_0 = _RAND_3[13:0];
  _RAND_4 = {1{`RANDOM}};
  padWriteIndexReg = _RAND_4[13:0];
  _RAND_5 = {1{`RANDOM}};
  padReadIndexReg = _RAND_5[13:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
  always @(posedge clock) begin
    if(dataSPad__T_9_en & dataSPad__T_9_mask) begin
      dataSPad[dataSPad__T_9_addr] <= dataSPad__T_9_data; // @[CoreArray.scala 175:48]
    end
    dataSPad__T_15_en_pipe_0 <= io_ctrlPath_read_en;
    if (io_ctrlPath_read_en) begin
      dataSPad__T_15_addr_pipe_0 <= padReadIndexReg;
    end
    if (reset) begin
      padWriteIndexReg <= 14'h0;
    end else if (writeFire) begin
      if (io_ctrlPath_write_fin) begin
        padWriteIndexReg <= 14'h0;
      end else begin
        padWriteIndexReg <= _T_6;
      end
    end
    if (reset) begin
      padReadIndexReg <= 14'h0;
    end else if (io_ctrlPath_read_index_inc) begin
      if (readWrapWire) begin
        padReadIndexReg <= 14'h0;
      end else begin
        padReadIndexReg <= _T_11;
      end
    end
  end
endmodule