N -> 2N bit stream converter

converter.v

module converter (
  input clk,
  input nrst,
  input [N-1:0] in,
  input in_valid,
  output in_ready,
  output [2*N-1:0] out,
  output out_valid,
  input out_ready
);
  
  parameter N = 8;
  
  reg [N-1:0] data;
  reg data_valid;
  
  assign out = {data, in};
  assign out_valid = data_valid & in_valid;
  assign in_ready = out_ready | !data_valid;
  
  always @(posedge clk) begin
    if(!nrst) begin
      data_valid <= 1'b0;
    end
    else if(in_valid) begin
      data <= in;
      data_valid <= !data_valid;
    end
  end
endmodule