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HackerFoo/vexriscv-verilog_nextpnr_xc7_a35tcpg236-1_basys3_xdc_carry-n.log

Created June 10, 2020 02:15
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vexriscv/nextpnr-xilinx log
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vexriscv-verilog_nextpnr_xc7_a35tcpg236-1_basys3_xdc_carry-n.log
Info: Packing constants..
Info: Inserting IO buffers..
Info: IO port 'clk' driven by IBUF '$iopadmap$top.clk'
Info: IO port 'di' driven by IBUF '$iopadmap$top.di'
Info: IO port 'do' driven by OBUF '$iopadmap$top.do'
Info: IO port 'stb' driven by IBUF '$iopadmap$top.stb'
Info: Constraining 'clk' to site 'IOB_X1Y26'
Info: Constraining 'di' to site 'IOB_X0Y11'
Info: Constraining 'do' to site 'IOB_X0Y43'
Info: Constraining 'stb' to site 'IOB_X0Y3'
Info: Generating input buffer for '$iopadmap$top.clk'
Info: Generating input buffer for '$iopadmap$top.di'
Info: Generating output buffer for '$iopadmap$top.do'
Info: Generating input buffer for '$iopadmap$top.stb'
Info: Created 3 IOB33_INBUF_EN cells from:
Info: 3x IBUF
Info: Created 1 IOB33_OUTBUF cells from:
Info: 1x OBUF
Info: Created 4 PAD cells from:
Info: 4x PAD
Info: Preparing clocking...
Info: Packing constants..
Info: Packing PLLs...
Info: Packing global buffers...
Info: Packing MUX[789]s..
Info: Packing carries..
Info: Grouped 528 MUXCYs and 528 XORCYs into 22 chains.
Info: Blasted 0 non-chain MUXCYs and 0 non-chain XORCYs to soft logic
Info: Packing LUTs..
Info: Created 5072 SLICE_LUTX cells from:
Info: 679x LUT1
Info: 878x LUT2
Info: 757x LUT3
Info: 726x LUT4
Info: 1488x LUT5
Info: 544x LUT6
Info: Packing DRAM..
Info: Transformed 0 tied-low DRAM address inputs to be tied-high
Info: Packing BRAM..
Info: Packing flipflops..
Info: Created 1918 SLICE_FFX cells from:
Info: 1909x FDRE
Info: 9x FDSE
Info: Constrained 726 LUTFF pairs.
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x6d910ac1
Info: Device utilisation:
Info: SLICE_LUTX: 5072/65200 7%
Info: SLICE_FFX: 1918/65200 2%
Info: CARRY4: 132/ 8150 1%
Info: PSEUDO_GND: 1/18055 0%
Info: PSEUDO_VCC: 1/18055 0%
Info: HARD0: 0/ 1980 0%
Info: RAMB18E1_RAMB18E1: 8/ 150 5%
Info: FIFO18E1_FIFO18E1: 0/ 75 0%
Info: RAMBFIFO36E1_RAMBFIFO36E1: 0/ 75 0%
Info: RAMB36E1_RAMB36E1: 1/ 75 1%
Info: DSP48E1_DSP48E1: 0/ 120 0%
Info: PAD: 4/ 730 0%
Info: IOB33M_OUTBUF: 0/ 120 0%
Info: IOB33S_OUTBUF: 0/ 120 0%
Info: IOB33_OUTBUF: 1/ 250 0%
Info: IOB33M_INBUF_EN: 0/ 120 0%
Info: IOB33S_INBUF_EN: 0/ 120 0%
Info: IOB33_INBUF_EN: 3/ 250 1%
Info: IOB33M_TERM_OVERRIDE: 0/ 120 0%
Info: IOB33S_TERM_OVERRIDE: 0/ 120 0%
Info: IOB33_TERM_OVERRIDE: 0/ 250 0%
Info: PULL_OR_KEEP1: 0/ 490 0%
Info: IDELAYE2_IDELAYE2: 0/ 250 0%
Info: OLOGICE3_TFF: 0/ 250 0%
Info: OLOGICE3_OUTFF: 0/ 250 0%
Info: OLOGICE3_MISR: 0/ 250 0%
Info: OSERDESE2_OSERDESE2: 0/ 250 0%
Info: ILOGICE3_IFF: 0/ 250 0%
Info: ILOGICE3_ZHOLD_DELAY: 0/ 250 0%
Info: ISERDESE2_ISERDESE2: 0/ 250 0%
Info: BUFIO_BUFIO: 0/ 20 0%
Info: IDELAYCTRL_IDELAYCTRL: 0/ 5 0%
Info: BUFGCTRL: 0/ 32 0%
Info: SELMUX2_1: 0/25450 0%
Info: BUFG_BUFG: 0/ 32 0%
Info: BUFHCE_BUFHCE: 0/ 72 0%
Info: PLLE2_ADV_PLLE2_ADV: 0/ 5 0%
Info: INVERTER: 0/ 120 0%
Info: BUFFER: 0/ 240 0%
Info: ILOGICE2_IFF: 0/ 250 0%
Info: OLOGICE2_MISR: 0/ 250 0%
Info: OLOGICE2_OUTFF: 0/ 250 0%
Info: OLOGICE2_TFF: 0/ 250 0%
Info: Placed 8 cells based on constraints.
Info: Creating initial analytic placement for 5239 cells, random placement wirelen = 1191778.
Info: at initial placer iter 0, wirelen = 11362
Info: at initial placer iter 1, wirelen = 11340
Info: at initial placer iter 2, wirelen = 11320
Info: at initial placer iter 3, wirelen = 11324
Info: Running main analytical placer.
Info: at iteration #1, type ALL: wirelen solved = 11324, spread = 201055, legal = 200757; time = 0.24s
Info: at iteration #2, type ALL: wirelen solved = 17483, spread = 137698, legal = 134455; time = 0.26s
Info: at iteration #3, type ALL: wirelen solved = 28819, spread = 121860, legal = 126460; time = 0.24s
Info: at iteration #4, type ALL: wirelen solved = 38640, spread = 104569, legal = 112621; time = 0.24s
Info: at iteration #5, type ALL: wirelen solved = 44545, spread = 97342, legal = 104431; time = 0.23s
Info: at iteration #6, type ALL: wirelen solved = 48908, spread = 92018, legal = 100183; time = 0.23s
Info: at iteration #7, type ALL: wirelen solved = 50607, spread = 88162, legal = 96214; time = 0.22s
Info: at iteration #8, type ALL: wirelen solved = 54483, spread = 93968, legal = 99083; time = 0.21s
Info: at iteration #9, type ALL: wirelen solved = 63198, spread = 95264, legal = 106793; time = 0.22s
Info: at iteration #10, type ALL: wirelen solved = 64258, spread = 93923, legal = 101948; time = 0.23s
Info: at iteration #11, type ALL: wirelen solved = 65785, spread = 101552, legal = 107773; time = 0.22s
Info: at iteration #12, type ALL: wirelen solved = 72488, spread = 106848, legal = 116363; time = 0.24s
Info: HeAP Placer Time: 3.97s
Info: of which solving equations: 2.24s
Info: of which spreading cells: 0.55s
Info: of which strict legalisation: 0.41s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1332, wirelen = 96214
Info: at iteration #5: temp = 0.000000, timing cost = 2507, wirelen = 85097
Info: at iteration #10: temp = 0.000000, timing cost = 2219, wirelen = 82959
Info: at iteration #15: temp = 0.000000, timing cost = 2154, wirelen = 82596
Info: at iteration #17: temp = 0.000000, timing cost = 2262, wirelen = 82550
Info: SA placement time 5.96s
Info: Max frequency for clock 'dut.clk': 68.14 MHz (PASS at 12.00 MHz)
Info: Slack histogram:
Info: legend: * represents 9 endpoint(s)
Info: + represents [1,9) endpoint(s)
Info: [ 68658, 69376) |**+
Info: [ 69376, 70094) |*****+
Info: [ 70094, 70812) |***+
Info: [ 70812, 71530) |************+
Info: [ 71530, 72248) |********+
Info: [ 72248, 72966) |*******+
Info: [ 72966, 73684) |*************+
Info: [ 73684, 74402) |*********************+
Info: [ 74402, 75120) |********************************+
Info: [ 75120, 75838) |******************+
Info: [ 75838, 76556) |***********+
Info: [ 76556, 77274) |******************+
Info: [ 77274, 77992) |*********+
Info: [ 77992, 78710) |*********+
Info: [ 78710, 79428) |*******+
Info: [ 79428, 80146) |**********+
Info: [ 80146, 80864) |************+
Info: [ 80864, 81582) |********************+
Info: [ 81582, 82300) |*****************************************+
Info: [ 82300, 83018) |************************************************************
Info: Checksum: 0xeb2bb03b
Info: Running post-placement legalisation...
Info: Routing global clocks...
Info: Running router2...
Info: Setting up routing resources...
Info: Running main router loop...
Info: iter=1 wires=127888 overused=7478 overuse=7722 archfail=NA
Info: iter=2 wires=131489 overused=2193 overuse=2201 archfail=NA
Info: iter=3 wires=132841 overused=220 overuse=220 archfail=NA
Info: iter=4 wires=133026 overused=15 overuse=15 archfail=NA
Info: iter=5 wires=133050 overused=3 overuse=3 archfail=NA
Info: iter=6 wires=133044 overused=2 overuse=2 archfail=NA
Info: iter=7 wires=133049 overused=1 overuse=1 archfail=NA
Info: iter=8 wires=133047 overused=1 overuse=1 archfail=NA
Info: iter=9 wires=133046 overused=1 overuse=1 archfail=NA
Info: iter=10 wires=133049 overused=1 overuse=1 archfail=NA
Info: iter=11 wires=133053 overused=0 overuse=0 archfail=0
Info: Router2 time 28.73s
Info: Running router1 to check that route is legal...
Info: Routing..
Info: Setting up routing queue.
Info: Routing 0 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 0 | 0 0 | 0 0 | 0| 0.27 0.27|
Info: Routing complete.
Info: Router1 time 0.27s
Info: Checksum: 0xfe6c3cea
Info: Critical path report for clock 'dut.clk' (posedge -> posedge):
Info: curr total
Info: 0.1 0.1 Source $auto$simplemap.cc:420:simplemap_dff$6776.Q
Info: 0.8 0.9 Net dut.lastStageIsValid budget 5.779000 ns (17,100) -> (14,84)
Info: Sink $abc$139925$lut$aiger139924$3278.A2
Info: 0.1 1.0 Source $abc$139925$lut$aiger139924$3278.O6
Info: 0.4 1.4 Net $techmap141674$abc$139925$lut\dut._zz_89_[18].A[2] budget 5.621000 ns (14,84) -> (17,85)
Info: Sink $abc$139925$lut$aiger139924$3285.A5
Info: 0.1 1.6 Source $abc$139925$lut$aiger139924$3285.O6
Info: 1.1 2.7 Net $techmap140923$abc$139925$lut$aiger139924$3288.A[3] budget 5.779000 ns (17,85) -> (13,100)
Info: Sink $abc$139925$lut$aiger139924$3288.A2
Info: 0.2 2.9 Source $abc$139925$lut$aiger139924$3288.O5
Info: 0.6 3.4 Net $techmap140925$abc$139925$lut$aiger139924$3303.A[4] budget 5.096000 ns (13,100) -> (13,100)
Info: Sink $auto$abc9_ops.cc:1514:reintegrate$140176.A2
Info: 0.1 3.6 Source $auto$abc9_ops.cc:1514:reintegrate$140176.O5
Info: 1.8 5.3 Net $techmap142230$abc$139925$lut\dut.dataCache_1_._zz_17_.A[0] budget 5.779000 ns (13,100) -> (52,90)
Info: Sink $abc$139925$lut$auto$dff2dffe.cc:158:make_patterns_logic$13019.A1
Info: 0.2 5.5 Source $abc$139925$lut$auto$dff2dffe.cc:158:make_patterns_logic$13019.O5
Info: 0.8 6.3 Net $techmap141738$auto$abc9_ops.cc:1514:reintegrate$140246.A[1] budget 5.779000 ns (52,90) -> (17,90)
Info: Sink $abc$139925$lut$auto$dff2dffe.cc:158:make_patterns_logic$19976.A4
Info: 0.1 6.4 Source $abc$139925$lut$auto$dff2dffe.cc:158:make_patterns_logic$19976.O5
Info: 0.6 7.0 Net $techmap143963$auto$abc9_ops.cc:1514:reintegrate$140006.A[1] budget 5.666000 ns (17,90) -> (17,93)
Info: Sink $abc$139925$lut$aiger139924$3464.A5
Info: 0.1 7.1 Source $abc$139925$lut$aiger139924$3464.O5
Info: 0.9 8.0 Net $techmap141002$auto$abc9_ops.cc:1514:reintegrate$140647.A[4] budget 5.779000 ns (17,93) -> (17,101)
Info: Sink $auto$abc9_ops.cc:1514:reintegrate$140647.A2
Info: 0.2 8.1 Source $auto$abc9_ops.cc:1514:reintegrate$140647.O5
Info: 0.3 8.4 Net $abc$139925$aiger139924$3604b budget 5.096000 ns (17,101) -> (17,101)
Info: Sink $abc$139925$aiger139924$3604b$LUT$790.A2
Info: 0.1 8.6 Source $abc$139925$aiger139924$3604b$LUT$790.O6
Info: 0.0 8.6 Net $abc$139925$aiger139924$3604b$legal$789 budget 4.946000 ns (17,101) -> (17,101)
Info: Sink $auto$alumacc.cc:485:replace_alu$4757.slice[1].carry4$split$muxcy0$PACKED_CARRY4$.S0
Info: 0.2 8.8 Source $auto$alumacc.cc:485:replace_alu$4757.slice[1].carry4$split$muxcy0$PACKED_CARRY4$.O0
Info: 1.9 10.7 Net $techmap141945$auto$abc9_ops.cc:1514:reintegrate$139978.A[2] budget 5.794000 ns (17,101) -> (23,125)
Info: Sink $abc$139925$lut$aiger139924$29335.A6
Info: 0.1 10.8 Source $abc$139925$lut$aiger139924$29335.O6
Info: 0.3 11.1 Net $techmap144375$abc$139925$lut$aiger139924$29351.A[4] budget 5.100000 ns (23,125) -> (23,125)
Info: Sink $abc$139925$lut$aiger139924$29351.A3
Info: 0.2 11.2 Source $abc$139925$lut$aiger139924$29351.O5
Info: 0.8 12.1 Net $techmap144376$abc$139925$lut$flatten\dut.$0\IBusCachedPlugin_fetchPc_pcReg[31:0][21].A[4] budget 5.445000 ns (23,125) -> (24,125)
Info: Sink $abc$139925$lut$flatten\dut.$0\IBusCachedPlugin_fetchPc_pcReg[31:0][21].A2
Info: 0.2 12.3 Source $abc$139925$lut$flatten\dut.$0\IBusCachedPlugin_fetchPc_pcReg[31:0][21].O5
Info: 0.0 12.3 Net $abc$139925$flatten\dut.$0\IBusCachedPlugin_fetchPc_pcReg[31:0][21] budget 4.949000 ns (24,125) -> (24,125)
Info: Sink $auto$simplemap.cc:420:simplemap_dff$6798.D
Info: 0.1 12.4 Setup $auto$simplemap.cc:420:simplemap_dff$6798.D
Info: 2.1 ns logic, 10.3 ns routing
Info: Max frequency for clock 'dut.clk': 80.80 MHz (PASS at 12.00 MHz)
Info: Slack histogram:
Info: legend: * represents 13 endpoint(s)
Info: + represents [1,13) endpoint(s)
Info: [ 70957, 71547) |+
Info: [ 71547, 72137) |**+
Info: [ 72137, 72727) |****+
Info: [ 72727, 73317) |**+
Info: [ 73317, 73907) |*****+
Info: [ 73907, 74497) |******+
Info: [ 74497, 75087) |******+
Info: [ 75087, 75677) |********+
Info: [ 75677, 76267) |******************+
Info: [ 76267, 76857) |*****************************+
Info: [ 76857, 77447) |*********+
Info: [ 77447, 78037) |*********+
Info: [ 78037, 78627) |*************+
Info: [ 78627, 79217) |*********+
Info: [ 79217, 79807) |******+
Info: [ 79807, 80397) |****+
Info: [ 80397, 80987) |********+
Info: [ 80987, 81577) |********+
Info: [ 81577, 82167) |***************************+
Info: [ 82167, 82757) |************************************************************
Info: Running post-routing legalisation...
real 0m42.128s
user 1m0.363s
sys 0m1.102s
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