gcd.v

module algorithm_gcd (
  `sync_ports,
  `input(int, 0),
  `input(int, 1),
  `output(int, 0)
);

  `alias(int, int1, in1);
  `alias(int, int2, in0);
  wire inst3_in_ready;
  `wire(int, int3);

  `top_sync(inst3_in_ready);

  `start_block(block1)
    `inst_sync(algorithm_gcd_r0, inst3)(
      `sync(in_valid, out_ready),
      `in(int, 0, int2), 
      `in(int, 1, int1), 
      `out(int, 0, int3)
    );
    wire block1_valid = inst3_out_valid;
  `end_block(block1)

  wire valid = (block1_valid);
  assign out_valid = valid;

  assign out0 = int3;

endmodule

module algorithm_gcd_r0 (
  `sync_ports,
  `input(int, 0),
  `input(int, 1),
  `output(int, 0)
);

  `variable(int, int1, in1);
  `variable(int, int2, in0);
  `wire(sym, sym3);
  `const(int, int4, 0);
  `wire(sym, sym5);
  `wire(int, int6);
  `wire(sym, sym8);
  `wire(int, int9);
  `wire(int, int10);

  `loop_sync(out_ready);

  `start_block(block1)
    `inst(__primitive_neq_yii, inst3)(
      `in(int, 0, int1), 
      `in(int, 1, int4), 
      `out(sym, 0, sym3)
    );
    `inst(__primitive_not_yy, inst5)(
      `in(sym, 0, sym3), 
      `out(sym, 0, sym5)
    );
    `assert(inst6, sym5);
    wire block1_valid = inst6_out_valid & active;
  `end_block(block1)

  `start_block(block8)
    `inst(__primitive_neq_yii, inst8)(
      `in(int, 0, int1), 
      `in(int, 1, int4), 
      `out(sym, 0, sym8)
    );
    `assert(inst9, sym8);
    `inst(__primitive_mod_iii, inst10)(
      `in(int, 0, int2), 
      `in(int, 1, int1), 
      `out(int, 0, int10)
    );
    wire block8_valid = inst9_out_valid;
  `end_block(block8)

  wire not_valid = block8_valid;
  wire valid = !not_valid & (block1_valid);
  assign out_valid = active & valid;

  always @(posedge clk) begin
    if(in_valid & ~active) begin
      int1 <= in1;
      int2 <= in0;
      `set(active);
    end
    else if(valid) begin
       if(out_ready) `reset(active);
    end
    else begin
      if(block8_valid) begin
        int2 <= int1;
        int1 <= int10;
      end
    end
  end

  assign out0 = int2;

endmodule