2024 交大DCS(數電)助教 - HW02 Convolutional Neural Network (大幅簡化iclab 2023 fall lab04 SNN題目)

readme.md

2024 NYCU DCS HW02 Convolution Neural Network

Overview

• input feature image 6*6
• convolution layer (kernel 3*3) 4*4
• ReLU layer 4*4 (option signal choose to donot / do ReLU)
• max pooling layer 2*2

Input

Input Signals	Bit Width	Definition
clk	1	Clock signal
rst_n	1	Asynchronous active-low reset
in_valid	1	Be high when input signals are valid.
in_data	16	The input signals for image and kernel which sent in raster ordering. The arithmetic representation follows the signed 2's complement format.
opt	1	The option signal. 1'b0: Activation function: ReLU; 1'b1: No Activation function

1. When in_valid is high, the 16-bit signed in_data is delivered in raster scan order with $6 \times 6 + 3 \times 3 = 45$ cycles continuously.
2. When in_valid is low after 45 cycles, the in_data is tied to unknown state.
3. The in_data is for a $6 \times 6$ input image and $3 \times3$ kernel. The kernel signal follows the input image.
4. The opt is delivered in the first cycle of in_valid tied to high and it is only valid for 1 cycle.
5. All input signals are synchronized at negative edge of the clock.
6. The next in_valid will be valid after 3-5 cycles when previous out_valid falls.

Output

Output Signals	Bit Width	Definition
out_valid	1	Be high when output signals are valid.
out_data	16	The output signals for feature map which must be sent in raster ordering. The arithmetic representation follows the signed 2's complement format.

1. The out_valid must be low with the asynchronous reset when rst_n is low.
2. The out_valid must be high for exact 4 consecutive cycles.
3. The out_data must be zero with the asynchronous reset when rst_n is low.
4. The out_data must be delivered for exact 4 consecutive cycles and out_valid should be high simultaneously.
5. The out_data recommend being zero when out_valid is low.
6. The out_valid cannot overlap with in_valid at any time.

CNN.v

//############################################################################
//   2024 Digital Circuit and System Lab
//   HW02        : Convolutional Neural Network (CNN) 
//   Author      : HsuChiChen (chenneil90121@gmail.com)
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   Date        : 2024.04.14
//   Version     : v1.0
//   File Name   : CNN.v
//   Module Name : CNN
//############################################################################

module CNN(
    // Output Ports
    input                    clk,
    input                    rst_n,
    input                    in_valid,
    input      signed [15:0] in_data,
    input                    opt,
    // Input Ports
    output reg               out_valid, 
    output reg signed [15:0] out_data	
);

//==============================================//
//             Parameter and Integer            //
//==============================================//
parameter   IDLE = 0,
            READ = 1,
            CALC = 2,
            OUT  = 3;

genvar i;
//==============================================//
//       Wire and Register Declaration          //
//==============================================//
// state
reg [1:0] current_state, next_state;

// counter
reg [5:0] counter;

// row and column coordinate
reg [2:0] row,col;

// input register
reg opt_reg;
reg signed [15:0] feature_map[0:35];   
reg signed [15:0] kernel[0:8];  

// convolution result
reg signed [15:0] cnn_layer[0:15];

// relu result
reg signed [15:0] relu_layer[0:15];

// max pooling result
wire signed [15:0] pooling1 [0:7];
wire signed [15:0] pooling2 [0:3];

//==============================================//
//             Update Current State             //
//==============================================//
always @(posedge clk , negedge rst_n) begin
    if(!rst_n) current_state <= IDLE;
    else current_state <= next_state;
end

//==============================================//
//             Calculate Next State             //
//==============================================//
always @(*) begin
    case(current_state)
        IDLE: begin
            if(in_valid) next_state <= READ;
            else next_state <= IDLE;
        end
        // read (6*6 image) + (3*3 kernel) = 45 cycles
        READ: begin
            if(counter == 44) next_state <= CALC;
            else next_state <= READ;
        end
        // do convolution in 16 cycles
        CALC: begin
            if(counter == 16) next_state <= OUT;
            else next_state <= CALC;
        end
        // output in 4 cycles
        OUT: begin
            if(counter == 3) next_state <= IDLE;
            else next_state <= OUT;
        end
    // default: next_state <= IDLE; // illigal state
    endcase
end

//==============================================//
//                Counter                       //
//==============================================//
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		counter <= 0;
    // READ -> CALC state
	end else if(counter == 44 && current_state == READ) begin
		counter <= 0;
    // CALC -> OUT state
	end else if(counter == 16 && current_state == CALC) begin
		counter <= 0;
    end else if(in_valid) begin
		counter <= counter + 1;
	end else if(current_state == CALC || current_state == OUT) begin
		counter <= counter + 1;
    // OUT -> IDLE state
    end else begin
		counter <= 0;
	end
end

//==============================================//
//                  Read Data                   //
//==============================================//
// 1-bit option
always @(posedge clk) begin
    if(in_valid && counter == 0)begin
        opt_reg <= opt;
    end
end

// 6*6 feature map
always @(posedge clk) begin
	if(in_valid && (counter < 36 && counter >= 0))begin
        feature_map[counter] <= in_data;
    end
end

// 3*3 kernel
always @(posedge clk) begin
    if(in_valid && (counter < 45 && counter >= 36))begin
        kernel[counter - 36] <= in_data;
    end
end

//==============================================//
//           Update Current Position            //
//==============================================//
always @(posedge clk) begin
	if(current_state == IDLE)begin
        row <= 0;
        col <= 0;
    // next row
    end else if(col == 3 && current_state == CALC)begin
        row <= row + 1;
        col <= 0;
    // shift right
	end else if(current_state == CALC)begin
		row <= row;
        col <= col + 1;
	end
end

//==============================================//
//        Convoultion in 9 * 9 block            //
//==============================================//
always @(posedge clk) begin
    if(counter < 16 && current_state == CALC)begin
        cnn_layer[counter] <=   kernel[0] * feature_map[row    *6 + col]
                            +   kernel[1] * feature_map[row    *6 + col+1]
                            +   kernel[2] * feature_map[row    *6 + col+2]
                            +   kernel[3] * feature_map[(row+1)*6 + col]
                            +   kernel[4] * feature_map[(row+1)*6 + col+1]
                            +   kernel[5] * feature_map[(row+1)*6 + col+2]
                            +   kernel[6] * feature_map[(row+2)*6 + col]
                            +   kernel[7] * feature_map[(row+2)*6 + col+1]
                            +   kernel[8] * feature_map[(row+2)*6 + col+2];
    end
end

//==============================================//
//           ReLu Activation Function           //
//==============================================//
generate
for(i = 0; i < 16; i = i + 1)begin
    always @(posedge clk) begin
        if(opt_reg == 0 && cnn_layer[i][15] == 1)begin
            relu_layer[i] <= 0;
        end else begin
            relu_layer[i] <= cnn_layer[i];      
        end
    end
end
endgenerate

//==============================================//
//                 Max Pooling                  //
//==============================================//
// first compare
assign pooling1[0] = (relu_layer[ 0] > relu_layer[ 1])? relu_layer[ 0]:relu_layer[ 1];
assign pooling1[1] = (relu_layer[ 2] > relu_layer[ 3])? relu_layer[ 2]:relu_layer[ 3];
assign pooling1[2] = (relu_layer[ 4] > relu_layer[ 5])? relu_layer[ 4]:relu_layer[ 5];
assign pooling1[3] = (relu_layer[ 6] > relu_layer[ 7])? relu_layer[ 6]:relu_layer[ 7];
assign pooling1[4] = (relu_layer[ 8] > relu_layer[ 9])? relu_layer[ 8]:relu_layer[ 9];
assign pooling1[5] = (relu_layer[10] > relu_layer[11])? relu_layer[10]:relu_layer[11];
assign pooling1[6] = (relu_layer[12] > relu_layer[13])? relu_layer[12]:relu_layer[13];
assign pooling1[7] = (relu_layer[14] > relu_layer[15])? relu_layer[14]:relu_layer[15];

// second compare
assign pooling2[0] = (pooling1[0] > pooling1[2])? pooling1[0]:pooling1[2];
assign pooling2[1] = (pooling1[1] > pooling1[3])? pooling1[1]:pooling1[3];
assign pooling2[2] = (pooling1[4] > pooling1[6])? pooling1[4]:pooling1[6];
assign pooling2[3] = (pooling1[5] > pooling1[7])? pooling1[5]:pooling1[7];

//==============================================//
//             Output Logic                     //
//==============================================//
// output valid
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        out_valid <= 0;
    end else if(current_state == OUT)begin
        out_valid <= 1;
    end else begin
        out_valid <= 0;
    end
end

// output data
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        out_data <= 0;
    end else if(current_state == OUT)begin
        out_data <= pooling2[counter];
    end else begin
        out_data <= 0;
    end
end

endmodule

PATTERN.v

//############################################################################
//   2024 Digital Circuit and System Lab
//   HW02        : Convolutional Neural Network (CNN) 
//   Author      : HsuChiChen (chenneil90121@gmail.com)
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   Date        : 2024.04.27
//   Version     : v2.0
//   File Name   : PATTERN.v
//   Module Name : PATTERN
//############################################################################
// specification
// input feature map [6, 6], kernel [3, 3] and 1-bit option
// input feature map do convolution (kernel [3,3]), result will be [4, 4]
// do max pooling, result will be [2, 2]
// opt == 0, do ReLU, opt == 1, do not ReLU, result will be [2, 2]
// consecutively output data in 4 cycles

// cycle time = 100 ns
`define CYCLE_TIME 100

module PATTERN(
    // Output Ports
    clk,
    rst_n,
    in_valid,
    in_data,
    opt,
    // Input Ports
	out_valid,
    out_data
);
//==============================================//
//          Input & Output Declaration          //
//==============================================//
output reg clk, rst_n, in_valid;
output reg signed [15:0] in_data;
output reg opt;
input out_valid;
input signed [15:0] out_data;

//==============================================//
//               Parameter & Integer            //
//==============================================//
// User modification
parameter PATTERN_NUM = 1000;
integer   SEED = 587;
integer   MAX_LATENCY = 1000;

// PATTERN operation
parameter CYCLE = `CYCLE_TIME;

// PATTERN CONTROL
integer total_latency;
integer latency;
integer i_pat;
integer i, j, k, l;
integer out_valid_count;

//==============================================//
//                 Signal Declaration           //
//==============================================//
// 6*6 image
reg signed [15:0] image[0:5][0:5];
// 3*3 kernel
reg signed [15:0] kernel[0:2][0:2];
// 1-bit option
reg opt_reg;

// 4*4 convolution result
reg signed [15:0] conv_result[0:3][0:3];

// 4*4 ReLU result
reg signed [15:0] relu_result[0:3][0:3];

// 2*2 pooling result
reg signed [15:0] pooling_result[0:1][0:1];

//==============================================//
//                 String control               //
//==============================================//
// Should use %0s
string reset_color          = "\033[1;0m";
string txt_black_prefix     = "\033[1;30m";
string txt_red_prefix       = "\033[1;31m";
string txt_green_prefix     = "\033[1;32m";
string txt_yellow_prefix    = "\033[1;33m";
string txt_blue_prefix      = "\033[1;34m";
string txt_magenta_prefix   = "\033[1;35m";
string txt_cyan_prefix      = "\033[1;36m";

string bkg_black_prefix     = "\033[40;1m";
string bkg_red_prefix       = "\033[41;1m";
string bkg_green_prefix     = "\033[42;1m";
string bkg_yellow_prefix    = "\033[43;1m";
string bkg_blue_prefix      = "\033[44;1m";
string bkg_white_prefix     = "\033[47;1m";

//==============================================//
//                main function                 //
//==============================================//
initial begin
	reset_task;

	// initial variable
	total_latency = 0;
	
	// start to test
	for(i_pat = 0; i_pat < PATTERN_NUM; i_pat = i_pat + 1) begin
		gen_pattern; // generate image, kernel and opt
		input_task;  // input by cycle
		cal_task;    // calculate convolution, ReLU and pooling
		wait_out_valid_task; // wait out_valid pull high
		check_ans_task; // check answer
		$display("%0s Pattern %3d Pass %0s Latency = %3d Cycles %0s", txt_green_prefix, i_pat, txt_yellow_prefix, latency, reset_color);
		total_latency = total_latency + latency;
	end
	pass_task;
end

//==============================================//
//    out_valid cannot overlap with in_valid    //
//==============================================//
// The out_valid cannot overlap with in_valid at any time
always @(posedge clk) begin
	if(in_valid === 1 && out_valid === 1) begin
		$display("%0s=========================================================", txt_red_prefix);
		$display("                        FAIL 						");
		$display("    out_valid and in_valid cannot overlap at %-8d ps  ", $time*1000);
		$display("=========================================================%0s", reset_color);
		repeat(3) #(CYCLE);
		$finish;
	end
end

//==============================================//
//            Clock and Reset Function          //
//==============================================//
// clock
always begin
	#(CYCLE/2.0);
	clk = ~clk;
end

// reset task
task reset_task; begin	
	// initiaize signal
	clk = 0;
	rst_n = 1;
	in_valid = 0;
	in_data = 'dx;
	opt = 'dx;
	// force clock to be 0, do not flip in half cycle
	force clk = 0;

	#(CYCLE*3);
	
	// reset
	rst_n = 0;  #(CYCLE*4); // wait 4 cycles to check output signal
	// check reset
	if(out_data !== 0 || out_valid !== 0) begin
		$display("%0s=========================================================", txt_red_prefix);
		$display("                        FAIL 						");
        $display("    Output signal should be 0 after reset at %-8d ps  ", $time*1000);
        $display("=========================================================%0s", reset_color);
        repeat(3) #(CYCLE);
        $finish;
	end

	// release reset
	rst_n = 1; #(CYCLE*3);
	
	// release clock
	release clk; repeat(5) @ (negedge clk);
end endtask

//==============================================//
//      Generate Pattern and Input Function     //
//==============================================//
// generate pattern
task gen_pattern; begin
	// generate image from -9 to 9
	for(i = 0; i < 6; i = i + 1) begin
		for(j = 0; j < 6; j = j + 1) begin
			image[i][j] = {$random(SEED)} % 19 - 9;
		end
	end

	// generate kernel from -9 to 9
	for(i = 0; i < 3; i = i + 1) begin
		for(j = 0; j < 3; j = j + 1) begin
			kernel[i][j] = {$random(SEED)} % 19 - 9;
		end
	end

	// generate opt from 0 to 1
	opt_reg = {$random(SEED)} % 2;
end endtask

// input task
task input_task; begin
	// input image
	in_valid = 1;
	// ouput opt in first cycle
	opt = opt_reg;
	for(i = 0; i < 6; i = i + 1) begin
		for(j = 0; j < 6; j = j + 1) begin
			in_data = image[i][j];
			@ (negedge clk);
			opt = 'bx;
		end
	end

	// input kernel
	for(i = 0; i < 3; i = i + 1) begin
		for(j = 0; j < 3; j = j + 1) begin
			in_data = kernel[i][j];
			@ (negedge clk);
		end
	end
	
	// release input
	in_valid = 0;
	in_data = 'dx;
end endtask

//==============================================//
//          Calculate and Check Function        //
//==============================================//
// calculate task
task cal_task; begin
	// calculate convolution
	for(i = 0; i < 4; i = i + 1) begin
		for(j = 0; j < 4; j = j + 1) begin
			conv_result[i][j] = 0;
			for(k = 0; k < 3; k = k + 1) begin
				for(l = 0; l < 3; l = l + 1) begin
					conv_result[i][j] = conv_result[i][j] + image[i+k][j+l] * kernel[k][l];
				end
			end
		end
	end

	// calculate ReLU
	for(i = 0; i < 4; i = i + 1) begin
		for(j = 0; j < 4; j = j + 1) begin
			if(opt_reg == 0 && conv_result[i][j] < 0) begin
				relu_result[i][j] = 0;
			end else begin
				relu_result[i][j] = conv_result[i][j];
			end
		end
	end

	// calculate pooling
	for (i = 0; i < 2; i = i + 1) begin
		for (j = 0; j < 2; j = j + 1) begin
			// initialize pooling result to be the first element
			pooling_result[i][j] = relu_result[i*2][j*2]; 
			for (k = 0; k < 2; k = k + 1) begin
				for (l = 0; l < 2; l = l + 1) begin
					// update pooling result to be the maximum value
					if(pooling_result[i][j] < relu_result[i*2+k][j*2+l]) begin
						pooling_result[i][j] = relu_result[i*2+k][j*2+l];
					end
				end
			end
		end
	end
end endtask

// wait out valid task
task wait_out_valid_task; begin
	latency = 0;
	// wait out valid
	while(out_valid === 0) begin
		@ (negedge clk);
		latency = latency + 1;
		// check latency is over MAX_LATENCY
		if(latency > MAX_LATENCY) begin
			$display("%0s================================================================", txt_red_prefix);
			$display("                             FAIL"                           );
			$display("    the execution latency is over %4d cycles at %-8d ps  ", MAX_LATENCY, $time*1000);
			$display("================================================================%0s", reset_color);
			$finish;
		end
	end
end endtask

// check answer task in 4 cycle
task check_ans_task ; begin
	out_valid_count = 0;
	// check answer
	while(out_valid === 1) begin
		if(out_valid_count === 0) begin
			if(pooling_result[0][0] !== out_data) begin
				out_data_error();
			end
		end else if(out_valid_count === 1) begin
			if(pooling_result[0][1] !== out_data) begin
				out_data_error();
			end
		end else if(out_valid_count === 2) begin
			if(pooling_result[1][0] !== out_data) begin
				out_data_error();
			end
		end else if(out_valid_count === 3) begin
			if(pooling_result[1][1] !== out_data) begin
				out_data_error();
			end
		end
		
		out_valid_count = out_valid_count + 1;
		if(out_valid_count > 4) begin
			$display("%0s====================================================================", txt_red_prefix);
			$display("                         FAIL"                           );
			$display("    out_valid consecutively pull high over 4 cycles at %-8d ps  ", $time*1000);
			$display("====================================================================%0s", reset_color);
			// wait for 5 cycles to terminate the program
			repeat(5) @ (negedge clk);
			$finish;
		end
		@ (negedge clk);
	end

	if(out_valid_count != 4) begin
		$display("%0s=========================================================================", txt_red_prefix);
		$display("                         FAIL"                           );
		$display("    out_valid should consecutively pull high in 4 cycles at %-8d ps  ", $time*1000);
		$display("=========================================================================%0s", reset_color);
		// wait for 5 cycles to terminate the program
		repeat(5) @ (negedge clk);
		$finish;
	end

	// next input wait random 3~5 cycles
	repeat({$random(SEED)} % 3 + 2) @ (negedge clk);
end endtask

//================================================================//
//   Print Calculation Value for Debugging when Output Error     //
//================================================================//
task out_data_error; begin
	$display("%0s========================================================", txt_red_prefix);
	$display("                   PATTERN %3d FAIL", i_pat);
	$display("                out_data in Cycle No. %1d", out_valid_count);
	$display("          Your answer = %3d, Correct answer = %3d", out_data, pooling_result[out_valid_count/2][out_valid_count%2]);
	$display("========================================================\033[m");	

	// print image
	$display("%0s[=================]", txt_blue_prefix);
	$display("[Input Feature Map]");
	$display("[=================] %0s", reset_color);
	
	$write("   ");
	for(i = 0; i < 6; i = i + 1) begin
		$write("%4d ", i); // print index
	end
	$write("\n");
	$display("_________________________________");
	for(i = 0; i < 6; i = i + 1) begin
    	$write("%1d |", i); 
		for(j = 0; j < 6; j = j + 1) begin
        	$write("%4d ", image[i][j]);
    	end
    	$write("\n"); // new line for next row
	end
	$write("\n");

	// print kernel
	$display("%0s[======]", txt_blue_prefix);
	$display("[Kernel]");
	$display("[======] %0s", reset_color);
	
	$write("   ");
	for(i = 0; i < 3; i = i + 1) begin
		$write("%4d ", i); // print index
	end
	$write("\n");
	$display("_________________");
	for(i = 0; i < 3; i = i + 1) begin
    	$write("%1d |", i); 
		for(j = 0; j < 3; j = j + 1) begin
        	$write("%4d ", kernel[i][j]);
    	end
    	$write("\n"); // new line for next row
	end
	$write("\n");

	// print opt
	$display("%0s[======]", txt_blue_prefix);
	$display("[Option]");
	$display("[======] %0s", reset_color);

	if(opt_reg == 0) begin
		$display("0 {Do ReLU}");
	end else begin
		$display("1 {Do Not ReLU}");
	end
	$write("\n");

	// print convolution result
	$display("%0s[==================]", txt_blue_prefix);
	$display("[Convolution Result]");
	$display("[==================] %0s", reset_color);
	
	$write("   ");
	for(i = 0; i < 4; i = i + 1) begin
		$write("%4d ", i); // print index
	end
	$write("\n");
	$display("_______________________");
	for(i = 0; i < 4; i = i + 1) begin
    	$write("%1d |", i); 
		for(j = 0; j < 4; j = j + 1) begin
        	$write("%4d ", conv_result[i][j]);
    	end
    	$write("\n"); // new line for next row
	end
	$write("\n");

	// print ReLU result
	$display("%0s[===========]", txt_blue_prefix);
	$display("[ReLU Result]");
	$display("[===========] %0s", reset_color);

	$write("   ");
	for(i = 0; i < 4; i = i + 1) begin
		$write("%4d ", i); // print index
	end
	$write("\n");
	$display("_______________________");
	for(i = 0; i < 4; i = i + 1) begin
    	$write("%1d |", i); 
		for(j = 0; j < 4; j = j + 1) begin
        	$write("%4d ", relu_result[i][j]);
    	end
    	$write("\n"); // new line for next row
	end
	$write("\n");

	// print pooling result
	$display("%0s[==============]", txt_blue_prefix);
	$display("[Pooling Result]");
	$display("[==============] %0s", reset_color);

	$write("   ");
	for(i = 0; i < 2; i = i + 1) begin
		$write("%4d ", i); // print index
	end
	$write("\n");
	$display("_____________");
	for(i = 0; i < 2; i = i + 1) begin
    	$write("%1d |", i); 
		for(j = 0; j < 2; j = j + 1) begin
        	$write("%4d ", pooling_result[i][j]);
    	end
    	$write("\n"); // new line for next row
	end
	$write("\n");

	// print pooling result
	$display("%0s[===============]", txt_blue_prefix);
	$display("[Expected Output]");
	$display("[===============] %0s", reset_color);
	$display("%0sIn Cycle 1, golden output_data = %4d", txt_cyan_prefix, pooling_result[0][0]);
	$display("In Cycle 2, golden output_data = %4d", pooling_result[0][1]);
	$display("In Cycle 3, golden output_data = %4d", pooling_result[1][0]);
	$display("In Cycle 4, golden output_data = %4d %0s", pooling_result[1][1],reset_color);

	// wait for 5 cycles to terminate the program
	repeat(5) @ (negedge clk);
	$finish;
end endtask

//==============================================//
//            Pass and Finish Function          //
//==============================================//
// pass task
task pass_task; begin
	$display("%0s========================================================", txt_magenta_prefix);
	$display("                      Congratulations!!");
    $display("                     All Pattern Test Pass");
	$display("                       Cycle time = %.1f ns", CYCLE);
	$display("          Your execution cycles = %-4d cycles", total_latency);
	$display("======================================================== %0s", reset_color);
	$finish;
end	endtask

endmodule

syn.log

#======================================================
#
# Synopsys Synthesis Scripts (Design Vision dctcl mode)
#
#======================================================
#======================================================
# (A) Global Parameters
#======================================================
set DESIGN "CNN"
CNN
set CYCLE 100
100
set INPUT_DLY [expr 0.5*$CYCLE]
50.0
set OUTPUT_DLY [expr 0.5*$CYCLE]
50.0
#======================================================
# (B) Read RTL Code
#======================================================
# (B-1) analyze + elaborate
set hdlin_auto_save_templates TRUE
TRUE
analyze -f sverilog $DESIGN\.v 
Running PRESTO HDLC
Compiling source file ./CNN.v
Presto compilation completed successfully.
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ss1p62v125c.db'
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ff1p98vm40c.db'
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_ss1p62v125c.db'
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_tt1p8v25c.db'
Loading db file '/usr/cad/synopsys/synthesis/cur/libraries/syn/dw_foundation.sldb'
Loading db file '/usr/cad/synopsys/synthesis/cur/libraries/syn/standard.sldb'
1
elaborate $DESIGN  
Loading db file '/usr/cad/synopsys/synthesis/2022.03/libraries/syn/gtech.db'
Loading db file '/usr/cad/synopsys/synthesis/2022.03/libraries/syn/standard.sldb'
  Loading link library 'fsa0m_a_generic_core_ss1p62v125c'
  Loading link library 'fsa0m_a_generic_core_ff1p98vm40c'
  Loading link library 'fsa0m_a_t33_generic_io_ss1p62v125c'
  Loading link library 'fsa0m_a_t33_generic_io_tt1p8v25c'
  Loading link library 'gtech'
Running PRESTO HDLC

Statistics for case statements in always block at line 71 in file
        './CNN.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            72            |    auto/auto     |
===============================================

Inferred memory devices in process
        in routine CNN line 63 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  current_state_reg  | Flip-flop |   2   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 99 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     counter_reg     | Flip-flop |   6   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 122 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opt_reg_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 129 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   feature_map_reg   | Flip-flop |  576  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 136 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     kernel_reg      | Flip-flop |  144  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 145 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       col_reg       | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
|       row_reg       | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 163 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    cnn_layer_reg    | Flip-flop |  256  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 182 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   relu_layer_reg    | Flip-flop |  256  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 215 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    out_valid_reg    | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine CNN line 226 in file
                './CNN.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    out_data_reg     | Flip-flop |  16   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
======================================================
| block name/line  | Inputs | Outputs | # sel inputs |
======================================================
|     CNN/230      |   4    |   16    |      2       |
======================================================
Presto compilation completed successfully. (CNN)
Elaborated 1 design.
Current design is now 'CNN'.
1
# (B-2) read_sverilog
#read_sverilog $DESIGN\.v
# (B-3) set current design
current_design $DESIGN
Current design is 'CNN'.
{CNN}
link

  Linking design 'CNN'
  Using the following designs and libraries:
  --------------------------------------------------------------------------
  CNN                         /RAID2/COURSE/DCS/DCS150/HW02/02_SYN/CNN.db
  fsa0m_a_generic_core_ss1p62v125c (library) /RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ss1p62v125c.db
  fsa0m_a_generic_core_ff1p98vm40c (library) /RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ff1p98vm40c.db
  fsa0m_a_t33_generic_io_ss1p62v125c (library) /RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_ss1p62v125c.db
  fsa0m_a_t33_generic_io_tt1p8v25c (library) /RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_tt1p8v25c.db
  dw_foundation.sldb (library) /usr/cad/synopsys/synthesis/cur/libraries/syn/dw_foundation.sldb

1
#======================================================
#  (C) Global Setting
#======================================================
set_wire_load_mode top
1
set_operating_conditions -max WCCOM -min BCCOM
Using operating conditions 'WCCOM' found in library 'fsa0m_a_generic_core_ss1p62v125c'.
Using operating conditions 'BCCOM' found in library 'fsa0m_a_generic_core_ff1p98vm40c'.
1
# set_wire_load_model -name umc18_wl10 -library slow
#======================================================
#  (D) Set Design Constraints
#======================================================
# (D-1) Setting Clock Constraints
create_clock -name clk -period $CYCLE [get_ports clk] 
1
set_dont_touch_network             [get_clocks clk]
1
set_fix_hold                       [get_clocks clk]
1
set_clock_uncertainty       0.1    [get_clocks clk]
1
# set_clock_latency   -source 0      [get_clocks clk]
# set_clock_latency           1      [get_clocks clk] 
set_input_transition        0.5    [all_inputs] 
1
set_clock_transition        0.1    [all_clocks] 
1
# (D-2) Setting in/out Constraints
set_input_delay   -max  $INPUT_DLY  -clock clk   [all_inputs] ;  # set_up time check 
1
set_input_delay   -min  0           -clock clk   [all_inputs] ;  # hold   time check 
1
set_output_delay  -max  $OUTPUT_DLY -clock clk   [all_outputs] ; # set_up time check 
1
set_output_delay  -min  0           -clock clk   [all_outputs] ; # hold   time check 
1
set_input_delay 0 -clock clk clk
1
set_input_delay 0 -clock clk rst_n
1
#set_max_delay $CYCLE -from [all_inputs] -to [all_outputs]
# (D-3) Setting Design Environment
# set_driving_cell -library umc18io3v5v_slow -lib_cell P2C    -pin {Y}  [get_ports clk]
# set_driving_cell -library umc18io3v5v_slow -lib_cell P2C    -pin {Y}  [remove_from_collection [all_inputs] [get_ports clk]]
# set_load  [load_of "umc18io3v5v_slow/P8C/A"]       [all_outputs] ; # ~= 0.038
set_load 0.05 [all_outputs]
1
# (D-4) Setting DRC Constraint
#set_max_delay           0     ; # Optimize delay max effort                 
#set_max_area            0      ; # Optimize area max effort           
set_max_transition      3       [all_inputs]   ; # U18 LUT Max Transition Value  
1
set_max_capacitance     0.15    [all_inputs]   ; # U18 LUT Max Capacitance Value
1
set_max_fanout          10      [all_inputs]
1
# set_dont_use slow/JKFF*
#set_dont_touch [get_cells core_reg_macro]
#set hdlin_ff_always_sync_set_reset true
# (D-5) Report Clock skew
report_clock -skew clk
Information: Checking out the license 'DesignWare'. (SEC-104)
Information: Changed wire load model for 'alt1' from '(none)' to 'G5K'. (OPT-170)
Information: Changed wire load model for 'apparch' from '(none)' to 'G5K'. (OPT-170)
Information: Changed wire load model for 'alt1' from '(none)' to 'G5K'. (OPT-170)
Information: Changed wire load model for 'apparch' from '(none)' to 'G5K'. (OPT-170)
Information: Changed wire load model for 'alt1' from '(none)' to 'G5K'. (OPT-170)
Information: Changed wire load model for 'apparch' from '(none)' to 'G5K'. (OPT-170)
Information: Updating design information... (UID-85)
Warning: Design 'CNN' contains 2 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
 
****************************************
Report : clock_skew
Design : CNN
Version: T-2022.03
Date   : Sun Apr 14 04:41:29 2024
****************************************

                 Rise      Fall  Min Rise  Min fall        Uncertainty
Object          Delay     Delay     Delay     Delay     Plus      Minus
--------------------------------------------------------------------------------
clk                 -         -         -         -      0.10      0.10

                 Max Transition      Min Transition
Object           Rise      Fall      Rise      Fall
-------------------------------------------------------
clk              0.10      0.10      0.10      0.10
1
check_timing

Information: Checking generated_clocks...

Information: Checking loops...

Information: Checking no_input_delay...

Information: Checking unconstrained_endpoints...

Information: Checking pulse_clock_cell_type...

Information: Checking no_driving_cell...

Information: Checking partial_input_delay...
1
#======================================================
#  (E) Optimization
#======================================================
check_design > Report/$DESIGN\.check
set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
1
set_fix_hold [all_clocks]
1
compile_ultra
Information: Performing power optimization. (PWR-850)
Analyzing: "/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_ss1p62v125c.db"
Analyzing: "/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_tt1p8v25c.db"
Analyzing: "/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ss1p62v125c.db"
Analyzing: "/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ff1p98vm40c.db"
Library analysis succeeded.
Information: Running optimization using a maximum of 8 cores. (OPT-1500)
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | S-2021.06-DWBB_202106.0 |     *     |
| Licensed DW Building Blocks        | S-2021.06-DWBB_202106.0 |     *     |
============================================================================

====================================================================================================
| Flow Information                                                                                 |
----------------------------------------------------------------------------------------------------
| Flow         | Design Compiler NXT WLM                                                           |
| Comand line  | compile_ultra                                                                     |
====================================================================================================
| Design Information                                      | Value                                  |
====================================================================================================
| Number of Scenarios                                     | 0                                      |
| Leaf Cell Count                                         | 3452                                   |
| Number of User Hierarchies                              | 0                                      |
| Sequential Cell Count                                   | 1264                                   |
| Macro Count                                             | 0                                      |
| Number of Power Domains                                 | 0                                      |
| Number of Path Groups                                   | 2                                      |
| Number of VT class                                      | 0                                      |
| Number of Clocks                                        | 1                                      |
| Number of Dont Touch cells                              | 432                                    |
| Number of Dont Touch nets                               | 1                                      |
| Number of size only cells                               | 0                                      |
| Design with UPF Data                                    | false                                  |
----------------------------------------------------------------------------------------------------
| Variables                                               | Value                                  |
----------------------------------------------------------------------------------------------------
| set_fix_multiple_port_nets                              | -all -buffer_constants                 |
====================================================================================================
Information: Sequential output inversion is enabled.  SVF file must be used for formal verification. (OPT-1208)

Information: There are 6 potential problems in your design. Please run 'check_design' for more information. (LINT-99)

  Simplifying Design 'CNN'

  Loading target library 'fsa0m_a_generic_core_ff1p98vm40c'
  Loading target library 'fsa0m_a_t33_generic_io_ss1p62v125c'
  Loading target library 'fsa0m_a_t33_generic_io_tt1p8v25c'
Loaded alib file './alib-52/fsa0m_a_generic_core_ss1p62v125c.db.alib'
Loaded alib file './alib-52/fsa0m_a_generic_core_ff1p98vm40c.db.alib'
Loaded alib file './alib-52/fsa0m_a_t33_generic_io_ss1p62v125c.db.alib' (placeholder)
Loaded alib file './alib-52/fsa0m_a_t33_generic_io_tt1p8v25c.db.alib' (placeholder)
Warning: Operating condition WCCOM set on design CNN has different process,
voltage and temperatures parameters than the parameters at which target library 
fsa0m_a_generic_core_ff1p98vm40c is characterized. Delays may be inaccurate as a result. (OPT-998)
  Building model 'DW01_NAND2'
Information: Ungrouping 0 of 1 hierarchies before Pass 1 (OPT-775)
Information: State dependent leakage is now switched from on to off.

  Beginning Pass 1 Mapping
  ------------------------
  Processing 'CNN'
Information: Added key list 'DesignWare' to design 'CNN'. (DDB-72)
 Implement Synthetic for 'CNN'.

  Updating timing information
Information: Updating design information... (UID-85)
Information: The library cell 'TIE1' in the library 'fsa0m_a_generic_core_ss1p62v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'TIE0' in the library 'fsa0m_a_generic_core_ss1p62v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'BHD1' in the library 'fsa0m_a_generic_core_ss1p62v125c' is not characterized for internal power. (PWR-536)
Information: The target library(s) contains cell(s), other than black boxes, that are not characterized for internal power. (PWR-24)

  Beginning Mapping Optimizations  (Ultra High effort)
  -------------------------------
Information: There is no timing violation in design CNN. Delay-based auto_ungroup will not be performed. (OPT-780)
Information: The register 'col_reg[2]' is a constant and will be removed. (OPT-1206)

                                  TOTAL                                                            
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE   MIN DELAY 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER      COST    
  --------- --------- --------- --------- --------- ------------------------- --------- -----------
    0:00:44  311676.9      0.00       0.0      73.9                           19743174.0000      0.00  
    0:00:44  300265.2      0.00       0.0    1987.7                           19098924.0000      0.00  

  Beginning Constant Register Removal
  -----------------------------------
    0:00:44  299071.5      0.00       0.0     389.5                           18858118.0000      0.00  
    0:00:45  299052.7      0.00       0.0     389.5                           18857964.0000      0.00  

  Beginning Global Optimizations
  ------------------------------
  Numerical Synthesis (Phase 1)
  Numerical Synthesis (Phase 2)
  Global Optimization (Phase 1)
  Global Optimization (Phase 2)
  Global Optimization (Phase 3)
  Global Optimization (Phase 4)
  Global Optimization (Phase 5)
  Global Optimization (Phase 6)
  Global Optimization (Phase 7)
  Global Optimization (Phase 8)
  Global Optimization (Phase 9)
  Global Optimization (Phase 10)
  Global Optimization (Phase 11)
  Global Optimization (Phase 12)
  Global Optimization (Phase 13)
  Global Optimization (Phase 14)
  Global Optimization (Phase 15)
  Global Optimization (Phase 16)
  Global Optimization (Phase 17)
  Global Optimization (Phase 18)
  Global Optimization (Phase 19)
  Global Optimization (Phase 20)
  Global Optimization (Phase 21)
  Global Optimization (Phase 22)
  Global Optimization (Phase 23)
  Global Optimization (Phase 24)
  Global Optimization (Phase 25)
  Global Optimization (Phase 26)
  Global Optimization (Phase 27)
  Global Optimization (Phase 28)
  Global Optimization (Phase 29)
  Global Optimization (Phase 30)
  Global Optimization (Phase 31)
  Global Optimization (Phase 32)

  Beginning Isolate Ports
  -----------------------

  Beginning Delay Optimization
  ----------------------------
    0:00:46  234441.2      0.00       0.0      80.4                           11640654.0000      0.00  
    0:00:46  234441.2      0.00       0.0      80.4                           11640654.0000      0.00  
    0:00:46  234441.2      0.00       0.0      80.4                           11640654.0000      0.00  
    0:00:47  233681.9      0.00       0.0      80.4                           11623105.0000      0.00  
    0:00:48  227860.4      0.00       0.0       6.6                           11458645.0000      0.00  
    0:00:48  227860.4      0.00       0.0       6.6                           11458645.0000      0.00  

  Beginning WLM Backend Optimization
  --------------------------------------
    0:00:49  227301.1      0.00       0.0       6.6                           11406694.0000      0.00  
    0:00:49  227301.1      0.00       0.0       6.6                           11406694.0000      0.00  
    0:00:49  227301.1      0.00       0.0       6.6                           11406694.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  


  Beginning Design Rule Fixing  (max_transition)  (max_capacitance)
  ----------------------------

                                  TOTAL                                                            
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE   MIN DELAY 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER      COST    
  --------- --------- --------- --------- --------- ------------------------- --------- -----------
    0:00:50  227273.0      0.00       0.0       6.6                           11246510.0000      0.00  
  Global Optimization (Phase 33)
  Global Optimization (Phase 34)
  Global Optimization (Phase 35)
    0:00:50  227279.2      0.00       0.0       0.0                           11247010.0000      0.00  
    0:00:50  227279.2      0.00       0.0       0.0                           11247010.0000      0.00  


  Beginning Leakage Power Optimization  (max_leakage_power 0)
  ------------------------------------

                                  TOTAL                                                            
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE   MIN DELAY 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER      COST    
  --------- --------- --------- --------- --------- ------------------------- --------- -----------
    0:00:50  227279.2      0.00       0.0       0.0                           11247010.0000      0.00  
  Global Optimization (Phase 36)
  Global Optimization (Phase 37)
  Global Optimization (Phase 38)
  Global Optimization (Phase 39)
  Global Optimization (Phase 40)
  Global Optimization (Phase 41)
  Global Optimization (Phase 42)
  Global Optimization (Phase 43)
  Global Optimization (Phase 44)
  Global Optimization (Phase 45)
  Global Optimization (Phase 46)
  Global Optimization (Phase 47)
  Global Optimization (Phase 48)
  Global Optimization (Phase 49)
    0:00:50  226785.5      0.00       0.0       0.0                           11188116.0000      0.00  
    0:00:50  226785.5      0.00       0.0       0.0                           11188116.0000      0.00  
    0:00:50  226785.5      0.00       0.0       0.0                           11188116.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  

                                  TOTAL                                                            
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE   MIN DELAY 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER      COST    
  --------- --------- --------- --------- --------- ------------------------- --------- -----------
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:51  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:52  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:52  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:52  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:52  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:52  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
    0:00:52  226785.5      0.00       0.0       0.0                           11186609.0000      0.00  
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ss1p62v125c.db'
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ff1p98vm40c.db'
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_ss1p62v125c.db'
Loading db file '/RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_t33_generic_io_tt1p8v25c.db'


Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios 


  Optimization Complete
  ---------------------
Warning: Design 'CNN' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
     Net 'clk': 1263 load(s), 1 driver(s)
  Loading target library 'fsa0m_a_generic_core_ff1p98vm40c'
  Loading target library 'fsa0m_a_t33_generic_io_ss1p62v125c'
  Loading target library 'fsa0m_a_t33_generic_io_tt1p8v25c'
Information: State dependent leakage is now switched from off to on.
Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)
1
#uniquify
#compile
#======================================================
#  (F) Output Reports 
#======================================================
report_design  >  Report/$DESIGN\.design
report_resource >  Report/$DESIGN\.resource
report_timing -max_paths 3 >  Report/$DESIGN\.timing
report_area >  Report/$DESIGN\.area
report_power > Report/$DESIGN\.power
report_clock > Report/$DESIGN\.clock
report_port >  Report/$DESIGN\.port
report_power >  Report/$DESIGN\.power
#report_reference > Report/$DESIGN\.reference
#======================================================
#  (G) Change Naming Rule
#======================================================
set bus_inference_style "%s\[%d\]"
%s[%d]
set bus_naming_style "%s\[%d\]"
%s[%d]
set hdlout_internal_busses true
true
change_names -hierarchy -rule verilog
1
define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
1
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
1
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
1
define_name_rules name_rule -case_insensitive
1
change_names -hierarchy -rules name_rule
1
#======================================================
#  (H) Output Results
#======================================================
set verilogout_higher_designs_first true
true
write -format verilog -output Netlist/$DESIGN\_SYN.v -hierarchy
Writing verilog file '/RAID2/COURSE/DCS/DCS150/HW02/02_SYN/Netlist/CNN_SYN.v'.
1
write -format ddc     -hierarchy -output $DESIGN\_SYN.ddc
Writing ddc file 'CNN_SYN.ddc'.
1
write_sdf -version 3.0 -context verilog -load_delay cell Netlist/$DESIGN\_SYN.sdf -significant_digits 6
Information: Writing timing information to file '/RAID2/COURSE/DCS/DCS150/HW02/02_SYN/Netlist/CNN_SYN.sdf'. (WT-3)
Information: Updating design information... (UID-85)
Warning: Design 'CNN' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
1
write_sdc Netlist/$DESIGN\_SYN.sdc
1
#======================================================
#  (I) Finish and Quit
#======================================================
report_area -designware -hierarchy
 
****************************************
Report : area
Design : CNN
Version: T-2022.03
Date   : Sun Apr 14 04:44:31 2024
****************************************

Library(s) Used:

    fsa0m_a_generic_core_ss1p62v125c (File: /RAID2/COURSE/BackUp/2023_Spring/iclab/iclabta01/UMC018_CBDK/CIC/SynopsysDC/db/fsa0m_a_generic_core_ss1p62v125c.db)

Number of ports:                           37
Number of nets:                         10480
Number of cells:                         9669
Number of combinational cells:           8406
Number of sequential cells:              1263
Number of macros/black boxes:               0
Number of buf/inv:                        667
Number of references:                      57

Combinational area:             156358.743834
Buf/Inv area:                     4790.318348
Noncombinational area:           70426.742535
Macro/Black Box area:                0.000000
Net Interconnect area:      undefined  (Wire load has zero net area)

Total cell area:                226785.486369
Total area:                 undefined

Hierarchical area distribution
------------------------------

                                  Global cell area              Local cell area
                                  --------------------  ------------------------------- 
Hierarchical cell                 Absolute     Percent  Combi-       Noncombi-   Black-
                                  Total        Total    national     national    boxes   Design
--------------------------------  -----------  -------  -----------  ----------  ------  ---------
CNN                               226785.4864    100.0  156358.7438  70426.7425  0.0000  CNN
--------------------------------  -----------  -------  -----------  ----------  ------  ---------
Total                                                   156358.7438  70426.7425  0.0000


Area of detected synthetic parts
--------------------------------
  No DW parts to report!

Estimated area of ungrouped synthetic parts
-------------------------------------------
                                        Estimated  Perc. of
  Module               Implem.  Count        Area cell area
  -------------------- -------  ----- ----------- ---------
  DP_OP_936J1_122_9795     str      1    690.3237      0.3%
  DP_OP_937J1_123_5115     str      1    653.5441      0.3%
  DP_OP_938J1_124_6072     str      1    246.1400      0.1%
  DP_OP_939J1_125_3351     str      1    209.3605      0.1%
  DP_OP_940J1_126_2977     str      1  67386.1748     29.7%
  DW01_add             apparch      3    618.7104      0.3%
  DW01_inc             apparch      1    169.7517      0.1%
  DW01_sub             apparch      1    115.6176      0.1%
  DW_cmp               apparch     15   8068.2316      3.6%
  DW_mult_uns          apparch      1    127.3138      0.1%
  -------------------- -------  ----- ----------- ---------
  DP_OP Subtotal:                   5  69185.5432     30.5%
  Total:                           26  78285.1683     34.5%

Subtotal of datapath(DP_OP) cell area:  69185.5432  30.5%  (estimated)
Total synthetic cell area:              78285.1683  34.5%  (estimated)

1
report_timing 
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : CNN
Version: T-2022.03
Date   : Sun Apr 14 04:44:31 2024
****************************************

 # A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: WCCOM   Library: fsa0m_a_generic_core_ss1p62v125c
Wire Load Model Mode: top

  Startpoint: in_valid (input port clocked by clk)
  Endpoint: feature_map_reg_28__0_
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  CNN                enG30K                fsa0m_a_generic_core_ss1p62v125c

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock clk (rise edge)                    0.00       0.00
  clock network delay (ideal)              0.00       0.00
  input external delay                    50.00      50.00 r
  in_valid (in)                            0.00      50.00 r
  U6894/O (INV1S)                          0.49      50.49 f
  U7297/O (NR2)                            0.52      51.00 r
  U7298/O (INV1S)                          0.25      51.25 f
  U10543/O (NR3)                           1.11      52.36 r
  U10612/O (ND2)                           1.43      53.79 f
  U10628/O (MOAI1S)                        0.84      54.63 r
  feature_map_reg_28__0_/D (QDFFS)         0.00      54.63 r
  data arrival time                                  54.63

  clock clk (rise edge)                  100.00     100.00
  clock network delay (ideal)              0.00     100.00
  clock uncertainty                       -0.10      99.90
  feature_map_reg_28__0_/CK (QDFFS)        0.00      99.90 r
  library setup time                      -0.15      99.75
  data required time                                 99.75
  -----------------------------------------------------------
  data required time                                 99.75
  data arrival time                                 -54.63
  -----------------------------------------------------------
  slack (MET)                                        45.11


1
exit

Memory usage for this session 456 Mbytes.
Memory usage for this session including child processes 724 Mbytes.
CPU usage for this session 191 seconds ( 0.05 hours ).
Elapsed time for this session 191 seconds ( 0.05 hours ).

Thank you...