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2019 IC Contest Cell-Based 研究所決賽 - 題目 : IoT Data Filtering (優化版本，原版本register開太多，但本題目運算沒有很多，因此可以放在同一個cycle運算，就不需要浪費多餘的register存資料)
Raw
IOTDF.v
//############################################################################
// 2019 IC Contest graduate group final round
// Topic : IoT Data Filtering
// Author : HsuChiChen (chenneil90121@gmail.com)
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Date : 2024.03.23
// Version : v2.0
// File Name : IOTDF.v
// Module Name : IOTDF
//############################################################################
// In TSMC 0.13um technology, latency is 10764 cycles, cycle time is 2.5ns, total cell area 60483 um^2
// latency is sum of TB1 + TB2 + TB3 + TB4 + TB5 + TB6 + TB7 = 1539 + 1539 + 1539 + 1536 + 1539 + 153 6+ 1536 = 10764 cycles
// latency is minimum value because busy is always 0
// IoT data filtering module
module IOTDF( clk, rst, in_en, iot_in, fn_sel, busy, valid, iot_out);
//==============================================//
// Input & Output Declaration //
//==============================================//
// Input Ports
input clk;
input rst;
input in_en;
input [7:0] iot_in;
input [2:0] fn_sel;
// Output Ports
output busy;
output reg valid;
output reg [127:0] iot_out;
//==============================================//
// Parameter and Integer //
//==============================================//
// 7 functions for data filtering
parameter MAX = 3'b001; // Max(N)
parameter MIN = 3'b010; // Min(N)
parameter AVG = 3'b011; // Avg(N)
parameter EXTRACT = 3'b100; // Extract (low < data < high)
parameter EXCLUDE = 3'b101; // Exclude (data < low || high < data)
parameter PEAK_MAX = 3'b110; // PeakMax (the data is greater than any previously output values)
parameter PEAK_MIN = 3'b111; // PeakMin (the data is smaller than any previously output values)
// In peak max / min mode, initial peak max / min value
parameter MIN_VALUE = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
parameter MAX_VALUE = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
// In extract mode, low < data < high
parameter EXTRACT_LOW = 128'h6FFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
parameter EXTRACT_HIGH = 128'hAFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
// In exclude mode, data < low || high < data
parameter EXCLUDE_LOW = 128'h7FFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
parameter EXCLUDE_HIGH = 128'hBFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
//==============================================//
// Reg declaration //
//==============================================//
// 16 byte * 8 data * 12 round = 1536 < 2^11
// 4-bit counter_byte counter[3:0] for iot_in , max value is 15
// 3-bit counter_data counter[6:4] for iot_data, max value is 7
// 4-bit counter_round counter[10:7] for round, max value is 12
reg [10:0] counter;
reg [10:0] counter_delay1;
reg [10:0] counter_delay2;
// 128-bit data register
reg [127:0] iot_data;
// max, min value
reg [127:0] extreme;
reg [130:0] sum; // max 127*8 = 1016, more 3 bits
// peak max, peak min value
reg [127:0] peak_extreme;
//==============================================//
// Wire Declaration //
//==============================================//
// whether the data is in the range of extract or exclude
wire extract_flag;
wire exclude_flag;
// whether the data is peak max or peak min
wire peak_max_flag;
wire peak_min_flag;
//==============================================//
// Delayed Signal Declaration //
//==============================================//
always @(posedge clk) begin
// add dummy mux to avoid timing violation
if(in_en) begin
counter_delay1 <= counter;
counter_delay2 <= counter_delay1;
end
end
//==============================================//
// counter for iot_in //
//==============================================//
always @(posedge clk or posedge rst) begin
if(rst) begin
counter <= 0;
end else if(in_en) begin
// 16 byte * 8 data * 12 round = 1536
if (counter == 1535) counter <= 0;
else counter <= counter + 1;
end
end
//==============================================//
// Read iot_in data //
//==============================================//
always @(posedge clk or posedge rst) begin
if(rst) begin
iot_data <= 0;
end else if(in_en) begin
// each iot_in data is 8-bit
iot_data[7:0] <= iot_in;
// shift register
iot_data[127:8] <= iot_data[119:0];
end
end
//==============================================//
// Update Max or Min Value //
//==============================================//
// update extreme value
always @(posedge clk or posedge rst) begin
if(rst) begin
extreme <= 0;
// input enable
end else if(in_en) begin
// In max mode
if(fn_sel == MAX || fn_sel == PEAK_MAX) begin
// read iot_data every 16 cycles
if (counter_delay1[3:0] == 15) begin
// update max value in the first round or iot_data > max
if(counter_delay1[6:4] == 0 || iot_data > extreme) extreme <= iot_data;
end
// In min mode
end else if(fn_sel == MIN || fn_sel == PEAK_MIN) begin
// read iot_data every 16 cycles
if (counter_delay1[3:0] == 15) begin
// update min value in the first round or iot_data < min
if(counter_delay1[6:4] == 0 || iot_data < extreme) extreme <= iot_data;
end
end
end
end
//==============================================//
// Calculate Sum //
//==============================================//
always @(posedge clk or posedge rst) begin
if(rst) begin
sum <= 0;
end else begin
// end else if(in_en) begin
// In avg mode
// if(fn_sel == AVG) begin
// read iot_data every 16 cycles
if (counter_delay1[3:0] == 15) begin
// In the first round, sum = iot_data
if(counter_delay1[6:4] == 0) begin
sum <= iot_data;
// In the other round, sum = sum + iot_data
end else begin
sum <= sum + iot_data;
end
end
// end
end
end
//==============================================//
// Flag for Extract and Exclude //
//==============================================//
assign extract_flag = (EXTRACT_LOW < iot_data) && (iot_data < EXTRACT_HIGH); // low < data < high
assign exclude_flag = (iot_data < EXCLUDE_LOW) || (EXCLUDE_HIGH < iot_data); // data < low || high < data
//==============================================//
// Update Peak Max and Peak Min Value //
//==============================================//
// update peak max / min value
always @(posedge clk) begin
if(in_en) begin
// In peak max mode
if(fn_sel == PEAK_MAX) begin
// initial peak max value to minumum value
if(counter_delay2 == 0) begin
peak_extreme <= MIN_VALUE;
// check each round (ie 16 cycles * 8 data = 128 cycles)
end else if (counter_delay2[6:0] == 127) begin
// update peak max value when max > peak max
if(extreme > peak_extreme) peak_extreme <= extreme;
end
// In peak min mode
end else if(fn_sel == PEAK_MIN) begin
// initial peak min value to maximum value
if(counter_delay2 == 0) begin
peak_extreme <= MAX_VALUE;
// check each round (ie 16 cycles * 8 data = 128 cycles)
end else if (counter_delay2[6:0] == 127) begin
// update peak min value when min < peak min
if(extreme < peak_extreme) peak_extreme <= extreme;
end
end
end
end
// Whether the data is peak max or peak min
assign peak_max_flag = extreme > peak_extreme;
assign peak_min_flag = extreme < peak_extreme;
//==============================================//
// Output Block //
//==============================================//
// busy always 0
assign busy = 0;
// valid
always @(posedge clk or posedge rst) begin
if(rst) begin
valid <= 0;
end else if(in_en) begin
case(fn_sel)
// In max mode
MAX: begin
// output max value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
valid <= 1;
end else begin
valid <= 0;
end
end
// In min mode
MIN: begin
// output min value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
valid <= 1;
end else begin
valid <= 0;
end
end
// In avg mode
AVG: begin
// output avg value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
valid <= 1;
end else begin
valid <= 0;
end
end
// In extract mode
EXTRACT: begin
// output extract value every iot_data (ie 16 cycles)
if (counter_delay1[3:0] == 15) begin
valid <= extract_flag;
end else begin
valid <= 0;
end
end
// In exclude mode
EXCLUDE: begin
// output exclude value every iot_data (ie 16 cycles)
if (counter_delay1[3:0] == 15) begin
valid <= exclude_flag;
end else begin
valid <= 0;
end
end
// In peak max mode
PEAK_MAX: begin
// output peak max value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
valid <= peak_max_flag;
end else begin
valid <= 0;
end
end
// In peak min mode
PEAK_MIN: begin
// output peak min value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
valid <= peak_min_flag;
end else begin
valid <= 0;
end
end
// illegal mode
default: begin
valid <= 0;
end
endcase
end
end
// iot_out
always @(posedge clk or posedge rst) begin
if(rst) begin
iot_out <= 0;
end else if(in_en) begin
case(fn_sel)
// In max mode
MAX: begin
// output max value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
iot_out <= extreme;
end
end
// In min mode
MIN: begin
// output min value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
iot_out <= extreme;
end
end
// In avg mode
AVG: begin
// output avg value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
iot_out <= sum >> 3; // avg = sum / 8
end
end
// In extract mode
EXTRACT: begin
// output extract value every iot_data (ie 16 cycles)
if (counter_delay1[3:0] == 15) begin
iot_out <= iot_data;
end
end
// In exclude mode
EXCLUDE: begin
// output exclude value every iot_data (ie 16 cycles)
if (counter_delay1[3:0] == 15) begin
iot_out <= iot_data;
end
end
// In peak max mode
PEAK_MAX: begin
// output peak max value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
iot_out <= extreme;
end
end
// In peak min mode
PEAK_MIN: begin
// output peak min value every round (ie 16 cycles * 8 data = 128 cycles)
if (counter_delay2[6:0] == 127) begin
iot_out <= extreme;
end
end
// illegal mode
default: begin
iot_out <= 1'b0;
end
endcase
end
end
endmodule
Raw
syn.log
# Read all Files
read_verilog IOTDF.v
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db'
Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/dw_foundation.sldb'
Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/gtech.db'
Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/standard.sldb'
Loading link library 'slow'
Loading link library 'gtech'
Loading verilog file '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'
Detecting input file type automatically (-rtl or -netlist).
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/M12/chenneil90121/ic_contest_mock3/IOTDF.v
Statistics for case statements in always block at line 226 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'
===============================================
| Line | full/ parallel |
===============================================
| 230 | auto/auto |
===============================================
Statistics for case statements in always block at line 303 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'
===============================================
| Line | full/ parallel |
===============================================
| 307 | auto/auto |
===============================================
Inferred memory devices in process
in routine IOTDF line 92 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| counter_delay1_reg | Flip-flop | 11 | Y | N | N | N | N | N | N |
| counter_delay2_reg | Flip-flop | 11 | Y | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 103 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| counter_reg | Flip-flop | 11 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 115 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| iot_data_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 130 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| extreme_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 157 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| sum_reg | Flip-flop | 131 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 188 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| peak_extreme_reg | Flip-flop | 128 | Y | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 226 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| valid_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine IOTDF line 303 in file
'/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| iot_out_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.db:IOTDF'
Loaded 1 design.
Current design is 'IOTDF'.
IOTDF
current_design IOTDF
Current design is 'IOTDF'.
{IOTDF}
link
Linking design 'IOTDF'
Using the following designs and libraries:
--------------------------------------------------------------------------
IOTDF /home/M12/chenneil90121/ic_contest_mock3/IOTDF.db
slow (library) /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db
dw_foundation.sldb (library) /usr/cad/synopsys/synthesis/2022.12/libraries/syn/dw_foundation.sldb
1
# Setting Clock Constraits
source -echo -verbose IOTDF_DC.sdc
# operating conditions and boundary conditions #
create_clock -name clk -period 2.5 [get_ports clk] ;#Modify period by yourself
1
set_dont_touch_network [all_clocks]
1
set_fix_hold [all_clocks]
1
set_clock_uncertainty 0.1 [all_clocks]
1
set_clock_latency 1.0 [all_clocks]
1
set_ideal_network [get_ports clk]
1
#Don't touch the basic env setting as below
set_input_delay -max 1.0 -clock clk [remove_from_collection [all_inputs] {clk}]
1
set_input_delay -min 0.0 -clock clk [remove_from_collection [all_inputs] {clk}]
1
set_output_delay -max 1.0 -clock clk [all_outputs]
1
set_output_delay -min 0.0 -clock clk [all_outputs]
1
set_load 0.01 [all_outputs]
1
set_drive 0.1 [all_inputs]
1
set_operating_conditions -max_library slow -max slow
Using operating conditions 'slow' found in library 'slow'.
1
set_max_fanout 10 [all_inputs]
1
1
# Synthesis all design
compile -map_effort high -area_effort high
Information: Checking out the license 'DesignWare'. (SEC-104)
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | U-2022.12-DWBB_202212.0 | * |
| Licensed DW Building Blocks | U-2022.12-DWBB_202212.0 | * |
============================================================================
====================================================================================================
| Flow Information |
----------------------------------------------------------------------------------------------------
| Flow | Design Compiler NXT |
====================================================================================================
| Design Information | Value |
====================================================================================================
| Number of Scenarios | 0 |
| Leaf Cell Count | 953 |
| Number of User Hierarchies | 0 |
| Sequential Cell Count | 677 |
| Macro Count | 0 |
| Number of Power Domains | 0 |
| Number of Path Groups | 2 |
| Number of VT Class | 0 |
| Number of Clocks | 1 |
| Number of Dont Touch Cells | 63 |
| Number of Dont Touch Nets | 1 |
| Number of Size Only Cells | 0 |
| Design with UPF Data | false |
====================================================================================================
Information: There are 7 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Beginning Pass 1 Mapping
------------------------
Processing 'IOTDF'
Updating timing information
Information: Updating design information... (UID-85)
Beginning Implementation Selection
----------------------------------
Mapping 'IOTDF_DW_cmp_0'
Mapping 'IOTDF_DW_cmp_1'
Mapping 'IOTDF_DW_cmp_2'
Mapping 'IOTDF_DW_cmp_3'
Processing 'IOTDF_DW01_inc_0'
Processing 'IOTDF_DW01_cmp6_0'
Processing 'IOTDF_DW01_cmp6_1'
Building model 'DW01_NAND2'
Processing 'DW01_NAND2'
Building model 'DW01_add_width131' (rpl)
Processing 'DW01_add_width131'
Processing 'IOTDF_DW01_add_0'
Mapping 'IOTDF_DW_mult_uns_0'
Beginning Mapping Optimizations (High effort)
-------------------------------
Information: Added key list 'DesignWare' to design 'IOTDF'. (DDB-72)
Mapping Optimization (Phase 1)
Mapping Optimization (Phase 2)
TOTAL
ELAPSED WORST NEG SETUP DESIGN MIN DELAY
TIME AREA SLACK COST RULE COST ENDPOINT COST
--------- --------- --------- --------- --------- ------------------------- -----------
0:00:21 114778.2 0.27 53.9 4.3 *cell*27396/U74/Y 0.00
0:00:21 114778.2 0.27 53.9 4.3 *cell*27396/U74/Y 0.00
0:00:22 114173.9 0.17 47.5 4.3 *cell*27396/*cell*27641/Y 0.00
0:00:22 114245.2 0.13 45.4 4.3 *cell*27396/*cell*27648/Y 0.00
0:00:22 114039.8 0.13 44.5 4.3 *cell*27396/*cell*27647/Y 0.00
0:00:22 113812.4 0.12 43.7 4.3 *cell*27396/*cell*27725/Y 0.00
0:00:22 113676.6 0.11 43.6 4.3 *cell*27396/*cell*27800/Y 0.00
0:00:23 113610.4 0.11 43.6 4.3 *cell*27396/*cell*27833/Y 0.00
0:00:23 113618.9 0.11 43.3 4.3 *cell*27396/U154/Y 0.00
0:00:23 113493.3 0.11 43.3 4.3 *cell*27396/U173/Y 0.00
0:00:23 113362.6 0.11 43.3 4.3 *cell*27396/U226/Y 0.00
0:00:23 113191.1 0.11 43.3 4.3 *cell*27396/U224/Y 0.00
0:00:23 113004.4 0.11 43.3 4.3 *cell*27396/U183/Y 0.00
0:00:23 112839.8 0.11 43.5 4.3 *cell*27396/U152/Y 0.00
0:00:24 119534.3 0.38 60.2 0.0 *cell*28167/U849/Y 0.00
0:00:24 119064.1 0.16 51.6 0.0 *cell*28167/U778/Y 0.00
0:00:24 118860.4 0.15 49.0 0.0 *cell*28167/U1369/Y 0.00
0:00:24 118556.6 0.15 46.1 0.0 *cell*28167/U776/Y 0.00
0:00:24 118371.6 0.15 45.7 0.0 *cell*28167/U1696/Y 0.00
0:00:24 117894.6 0.15 45.6 0.0 *cell*28167/U1236/Y 0.00
0:00:24 117679.0 0.15 45.1 0.0 *cell*28167/*cell*28420/Y 0.00
0:00:24 117529.7 0.15 44.4 0.0 *cell*28167/U533/Y 0.00
0:00:24 117005.2 0.15 44.3 0.0 *cell*28167/*cell*28571/Y 0.00
0:00:24 116879.6 0.15 44.9 0.0 *cell*28167/*cell*28439/Y 0.00
0:00:24 116582.5 0.15 45.6 0.0 *cell*28167/U487/Y 0.00
0:00:25 116346.6 0.15 45.5 0.0 *cell*28167/*cell*28655/Y 0.00
0:00:25 116148.0 0.15 45.6 0.0 *cell*28167/*cell*28571/Y 0.00
0:00:25 115964.7 0.15 45.5 0.0 *cell*28167/U1034/Y 0.00
0:00:25 115761.0 0.15 45.5 0.0 *cell*28167/*cell*28634/Y 0.00
0:00:25 115452.1 0.15 45.2 0.0 *cell*28167/*cell*28851/Y 0.00
0:00:25 115144.8 0.15 44.2 0.0 *cell*28167/U1124/Y 0.00
0:00:25 114684.8 0.15 44.2 0.0 *cell*28167/U1738/Y 0.00
0:00:25 114425.1 0.15 43.5 0.0 *cell*28167/U1627/Y 0.00
0:00:25 114196.0 0.15 43.3 0.0 *cell*28167/*cell*28391/Y 0.00
0:00:25 113987.2 0.15 43.1 0.0 *cell*28167/*cell*28265/Y 0.00
0:00:25 113734.3 0.15 43.3 0.0 *cell*28167/*cell*29155/Y 0.00
0:00:26 113584.9 0.15 43.5 0.0 *cell*28167/*cell*28901/Y 0.00
0:00:26 113389.7 0.15 43.5 0.0 *cell*28167/U336/Y 0.00
0:00:26 113053.6 0.15 43.7 0.0 *cell*28167/*cell*29310/Y 0.00
0:00:26 112724.3 0.15 43.8 0.0 *cell*28167/*cell*29059/Y 0.00
0:00:26 112415.4 0.15 43.6 0.0 *cell*28167/*cell*29288/Y 0.00
0:00:26 112181.2 0.15 43.6 0.0 *cell*28167/*cell*28243/Y 0.00
0:00:26 111969.0 0.15 43.7 0.0 *cell*28167/U1212/Y 0.00
0:00:26 111638.0 0.15 43.6 0.0 *cell*28167/*cell*29326/Y 0.00
0:00:26 111354.5 0.15 43.9 0.0 *cell*28167/U946/Y 0.00
0:00:26 111099.9 0.15 43.8 0.0 *cell*28167/*cell*29715/Y 0.00
0:00:26 110901.3 0.15 43.8 0.0 *cell*28167/*cell*29734/Y 0.00
0:00:27 110804.6 0.15 43.9 0.0 *cell*28167/U887/Y 0.00
0:00:27 110536.4 0.15 44.2 0.0 *cell*28167/*cell*29847/Y 0.00
0:00:27 110173.1 0.15 43.8 0.0 *cell*28167/U426/Y 0.00
0:00:27 109874.4 0.15 43.8 0.0 *cell*28167/*cell*29953/Y 0.00
0:00:27 109686.0 0.15 43.8 0.0 *cell*28167/*cell*29419/Y 0.00
0:00:27 109375.4 0.15 43.8 0.0 *cell*28167/*cell*30011/Y 0.00
0:00:27 108978.2 0.15 43.8 0.0 *cell*28167/*cell*28908/Y 0.00
0:00:27 108616.6 0.15 43.9 0.0 *cell*28167/U956/Y 0.00
0:00:27 108423.1 0.15 43.9 0.0 *cell*28167/*cell*30200/Y 0.00
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0:00:28 107883.3 0.15 43.9 0.0 *cell*28167/*cell*29464/Y 0.00
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0:00:28 107347.0 0.15 43.8 0.0 *cell*28167/U1701/Y 0.00
0:00:28 107173.8 0.15 43.8 0.0 *cell*28167/*cell*30543/Y 0.00
0:00:28 106880.2 0.15 43.8 0.0 *cell*28167/*cell*30581/Y 0.00
0:00:28 106676.5 0.15 43.8 0.0 *cell*28167/*cell*29459/Y 0.00
0:00:28 106544.1 0.15 43.8 0.0 *cell*28167/*cell*29460/Y 0.00
0:00:28 106406.6 0.15 45.2 0.0 *cell*28167/*cell*29377/Y 0.00
0:00:29 106162.2 0.15 44.7 0.0 *cell*28167/*cell*30606/Y 0.00
0:00:29 105926.2 0.15 44.3 0.0 *cell*28167/*cell*30776/Y 0.00
0:00:29 105797.2 0.15 44.6 0.0 *cell*28167/*cell*30531/Y 0.00
0:00:29 105486.6 0.15 44.6 0.0 *cell*28167/*cell*30837/Y 0.00
0:00:29 105267.7 0.15 44.6 0.0 *cell*28167/*cell*30884/Y 0.00
0:00:29 105101.3 0.15 44.4 0.0 *cell*28167/*cell*30806/Y 0.00
0:00:29 104918.0 0.15 44.4 0.0 *cell*28167/U782/Y 0.00
0:00:29 104811.1 0.15 43.9 0.0 *cell*28167/*cell*29194/Y 0.00
0:00:29 104716.0 0.15 43.9 0.0 *cell*28167/U873/Y 0.00
0:00:29 104570.0 0.15 43.9 0.0 *cell*28167/U811/Y 0.00
0:00:29 104337.5 0.15 44.0 0.0 *cell*28167/U1473/Y 0.00
0:00:30 104071.0 0.15 47.4 0.0 *cell*28167/*cell*31169/Y 0.00
0:00:30 103882.6 0.15 44.0 0.0 *cell*28167/U695/Y 0.00
0:00:30 103614.4 0.15 44.0 0.0 *cell*28167/*cell*30121/Y 0.00
0:00:30 103502.4 0.15 44.0 0.0 *cell*28167/*cell*31167/Y 0.00
0:00:30 103320.7 0.15 44.0 0.0 *cell*28167/U805/Y 0.00
0:00:30 103049.2 0.15 44.0 0.0 *cell*28167/*cell*31380/Y 0.00
0:00:30 102872.6 0.15 44.0 0.0 *cell*28167/*cell*31138/Y 0.00
0:00:30 102626.5 0.15 44.0 0.0 *cell*28167/U1190/Y 0.00
0:00:30 102422.8 0.15 43.9 0.0 *cell*28167/U1431/Y 0.00
0:00:30 102132.6 0.15 43.9 0.0 *cell*28167/U157/Y 0.00
0:00:30 101862.7 0.15 43.9 0.0 *cell*28167/*cell*31557/Y 0.00
0:00:30 101587.7 0.15 43.9 0.0 *cell*28167/*cell*31586/Y 0.00
0:00:30 101326.3 0.13 41.5 0.0 *cell*28167/*cell*31615/Y 0.00
0:00:31 101022.5 0.13 41.5 0.0 *cell*28167/*cell*31653/Y 0.00
0:00:31 100937.6 0.13 41.6 0.0 *cell*28167/*cell*31703/Y 0.00
0:00:31 100815.4 0.13 41.6 0.0 *cell*28167/*cell*31446/Y 0.00
0:00:31 100554.0 0.13 41.5 0.0 *cell*28167/*cell*31768/Y 0.00
0:00:31 100433.5 0.13 41.9 0.0 *cell*28167/U1477/Y 0.00
0:00:31 100150.0 0.11 39.8 0.0 *cell*28167/U674/Y 0.00
0:00:31 99968.4 0.11 39.8 0.0 *cell*28167/*cell*31875/Y 0.00
0:00:31 99734.1 0.11 39.4 0.0 *cell*28167/*cell*31914/Y 0.00
0:00:31 99481.2 0.11 39.4 0.0 *cell*28167/U518/Y 0.00
0:00:31 99365.8 0.11 38.4 0.0 *cell*28167/*cell*31947/Y 0.00
0:00:31 99284.3 0.11 38.5 0.0 *cell*28167/*cell*30010/Y 0.00
0:00:31 99058.6 0.11 38.5 0.0 *cell*28167/*cell*31989/Y 0.00
0:00:32 98933.0 0.11 38.5 0.0 *cell*28167/*cell*31334/Y 0.00
0:00:32 98868.5 0.11 38.1 0.0 *cell*28167/*cell*30284/Y 0.00
0:00:32 98785.3 0.11 38.0 0.0 *cell*28167/*cell*29588/Y 0.00
0:00:32 98663.1 0.11 38.0 0.0 *cell*28167/*cell*30614/Y 0.00
0:00:32 98510.3 0.11 37.4 0.0 *cell*28167/*cell*29422/Y 0.00
0:00:32 98327.0 0.11 37.4 0.0 *cell*28167/*cell*30040/Y 0.00
0:00:32 98069.0 0.11 37.4 0.0 *cell*28167/*cell*28237/Y 0.00
0:00:32 97924.7 0.11 37.3 0.0 *cell*28167/*cell*32160/Y 0.00
0:00:32 97865.3 0.11 37.1 0.0 *cell*28167/*cell*31806/Y 0.00
0:00:32 97771.9 0.11 37.1 0.0 *cell*28167/*cell*29323/Y 0.00
0:00:32 97612.4 0.11 37.1 0.0 *cell*28167/*cell*32208/Y 0.00
0:00:32 97568.2 0.11 37.1 0.0 *cell*28167/*cell*32118/Y 0.00
0:00:32 97481.7 0.11 37.1 0.0 *cell*28167/*cell*31966/Y 0.00
0:00:32 97405.3 0.11 37.2 0.0 *cell*28167/*cell*32148/Y 0.00
0:00:33 97250.8 0.11 37.1 0.0 *cell*28167/*cell*29429/Y 0.00
0:00:33 97081.1 0.11 37.1 0.0 *cell*28167/*cell*32307/Y 0.00
0:00:33 97052.2 0.11 37.1 0.0 *cell*28167/*cell*32277/Y 0.00
0:00:33 96977.6 0.11 37.6 0.0 *cell*28167/*cell*29579/Y 0.00
0:00:33 96923.2 0.11 37.1 0.0 *cell*28167/*cell*31810/Y 0.00
0:00:33 96868.9 0.11 37.1 0.0 *cell*28167/*cell*32376/Y 0.00
0:00:33 96767.1 0.11 37.1 0.0 *cell*28167/*cell*32387/Y 0.00
0:00:33 96656.7 0.11 37.1 0.0 *cell*28167/*cell*32365/Y 0.00
0:00:33 96607.5 0.11 37.2 0.0 *cell*28167/*cell*32388/Y 0.00
0:00:33 96568.5 0.11 37.1 0.0 *cell*28167/*cell*32417/Y 0.00
0:00:34 96509.1 0.11 37.1 0.0 0.00
0:00:34 95456.7 0.12 36.6 0.0 0.00
0:00:34 95456.7 0.12 36.6 0.0 0.00
0:00:35 95432.9 0.12 36.4 0.0 0.00
0:00:35 95432.9 0.12 36.4 0.0 0.00
0:00:37 58044.3 1.07 415.1 0.0 0.00
0:00:38 57496.0 1.20 365.6 0.0 0.00
0:00:39 57431.5 1.01 319.7 0.0 0.00
0:00:39 57433.2 1.02 327.5 0.0 0.00
0:00:40 57428.1 0.98 317.5 0.0 0.00
0:00:40 57490.9 0.98 330.0 0.0 0.00
0:00:40 57474.0 0.90 309.0 0.0 0.00
0:00:41 57518.1 0.89 321.4 0.0 0.00
0:00:41 57497.7 0.94 312.8 0.0 0.00
0:00:42 57550.3 1.10 347.8 0.0 0.00
0:00:42 57552.0 0.87 316.6 0.0 0.00
0:00:42 57567.3 0.86 315.2 0.0 0.00
0:00:42 57572.4 0.83 313.0 0.0 0.00
0:00:42 57606.4 0.82 308.4 0.0 0.00
0:00:42 57633.5 0.82 308.2 0.0 0.00
0:00:42 57667.5 0.81 306.7 0.0 0.00
0:00:43 57638.6 0.80 306.4 0.0 0.00
0:00:43 57650.5 0.80 306.3 0.0 0.00
0:00:43 57682.7 0.80 306.1 0.0 0.00
0:00:43 57682.7 0.80 306.1 0.0 0.00
0:00:43 57682.7 0.80 306.1 0.0 0.00
0:00:43 57682.7 0.80 306.1 0.0 0.00
0:00:43 57682.7 0.80 306.1 0.0 0.00
0:00:43 57682.7 0.80 306.1 0.0 0.00
0:00:43 57874.5 0.58 239.5 0.0 sum_reg[113]/D 0.00
0:00:44 58056.2 0.54 224.0 0.0 sum_reg[84]/D 0.00
0:00:44 58163.1 0.52 220.0 0.0 sum_reg[68]/D 0.00
0:00:44 58332.8 0.49 210.3 0.0 extreme_reg[70]/D 0.00
0:00:44 58533.1 0.47 205.1 0.0 extreme_reg[70]/D 0.00
0:00:45 58687.6 0.46 201.4 0.0 sum_reg[83]/D 0.00
0:00:45 59137.4 0.45 184.9 0.0 peak_extreme_reg[111]/D 0.00
0:00:45 59217.2 0.45 184.4 0.0 extreme_reg[92]/D 0.00
0:00:45 59305.5 0.44 184.1 0.0 extreme_reg[92]/D 0.00
0:00:45 59549.9 0.43 183.0 0.0 extreme_reg[92]/D 0.00
0:00:45 59614.4 0.43 182.7 0.0 extreme_reg[92]/D 0.00
0:00:45 59704.3 0.43 180.9 0.0 extreme_reg[92]/D 0.00
0:00:46 59816.4 0.42 173.2 0.0 extreme_reg[92]/D 0.00
0:00:46 59928.4 0.42 172.8 0.0 extreme_reg[92]/D 0.00
0:00:46 60004.8 0.41 172.1 0.0 extreme_reg[92]/D 0.00
0:00:46 60118.5 0.41 171.7 0.0 extreme_reg[92]/D 0.00
0:00:46 60121.9 0.41 170.8 0.0 extreme_reg[92]/D 0.00
0:00:46 60186.4 0.40 168.7 0.0 extreme_reg[92]/D 0.00
0:00:46 60215.3 0.40 167.2 0.0 extreme_reg[92]/D 0.00
0:00:46 60362.9 0.39 165.9 0.0 extreme_reg[92]/D 0.00
0:00:46 60541.2 0.38 164.4 0.0 extreme_reg[92]/D 0.00
0:00:46 60785.6 0.36 157.6 0.0 iot_out_reg[25]/D 0.00
0:00:47 60839.9 0.35 154.5 0.0 extreme_reg[12]/D 0.00
0:00:47 60873.9 0.34 153.3 0.0 extreme_reg[77]/D 0.00
0:00:47 61028.3 0.33 144.3 0.0 extreme_reg[8]/D 0.00
0:00:47 61145.4 0.32 137.9 0.0 sum_reg[123]/D 0.00
0:00:47 61162.4 0.31 138.0 0.0 extreme_reg[38]/D 0.00
0:00:47 61211.6 0.31 136.6 0.0 extreme_reg[38]/D 0.00
0:00:47 61223.5 0.31 136.3 0.0 iot_out_reg[25]/D 0.00
0:00:47 61401.7 0.30 133.6 0.0 extreme_reg[38]/D 0.00
0:00:48 61554.5 0.30 132.1 0.0 extreme_reg[38]/D 0.00
0:00:48 61580.0 0.30 131.8 0.0 extreme_reg[38]/D 0.00
0:00:48 61654.7 0.29 130.6 0.0 peak_extreme_reg[47]/D 0.00
0:00:48 61771.8 0.29 124.4 0.0 extreme_reg[38]/D 0.00
0:00:48 61894.0 0.29 123.6 0.0 extreme_reg[3]/D 0.00
0:00:48 61980.6 0.27 114.9 0.0 sum_reg[68]/D 0.00
0:00:48 62007.7 0.26 105.0 0.0 sum_reg[68]/D 0.00
0:00:48 62062.0 0.25 102.5 0.0 sum_reg[68]/D 0.00
0:00:49 62094.3 0.24 100.4 0.0 sum_reg[113]/D 0.00
0:00:49 62163.9 0.23 94.8 0.0 extreme_reg[51]/D 0.00
0:00:50 62269.1 0.21 84.0 0.0 0.00
0:00:50 62647.6 0.20 78.2 0.0 0.00
0:00:50 63022.8 0.20 73.4 0.0 0.00
0:00:50 63041.4 0.18 71.7 0.0 0.00
0:00:51 63114.4 0.18 71.0 0.0 0.00
0:00:51 63275.7 0.18 69.0 0.0 0.00
0:00:51 63426.7 0.17 66.8 0.0 0.00
0:00:51 63459.0 0.17 66.2 0.0 0.00
0:00:51 63489.5 0.17 65.6 0.0 0.00
0:00:51 63567.6 0.17 65.0 0.0 0.00
0:00:51 63725.5 0.17 64.0 2.2 0.00
0:00:51 63732.3 0.17 63.9 2.2 0.00
Beginning Delay Optimization Phase
----------------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN MIN DELAY
TIME AREA SLACK COST RULE COST ENDPOINT COST
--------- --------- --------- --------- --------- ------------------------- -----------
0:00:51 63732.3 0.17 63.9 2.2 0.00
0:00:51 63749.3 0.16 63.4 2.2 extreme_reg[126]/D 0.00
0:00:51 63863.0 0.16 62.8 2.2 peak_extreme_reg[24]/D 0.00
0:00:52 63956.3 0.16 61.5 2.2 extreme_reg[126]/D 0.00
0:00:52 63964.8 0.16 61.3 2.2 peak_extreme_reg[24]/D 0.00
0:00:52 64024.2 0.16 60.9 2.2 extreme_reg[126]/D 0.00
0:00:52 64065.0 0.16 58.0 6.1 extreme_reg[126]/D 0.00
0:00:52 64083.6 0.16 57.4 6.1 extreme_reg[126]/D 0.00
0:00:52 64115.9 0.15 56.7 10.1 extreme_reg[126]/D 0.00
0:00:52 64143.0 0.15 54.3 10.1 extreme_reg[12]/D 0.00
0:00:52 64217.7 0.15 53.9 10.1 extreme_reg[126]/D 0.00
0:00:52 64219.4 0.15 53.4 10.1 extreme_reg[126]/D 0.00
0:00:52 64238.1 0.15 53.4 10.1 extreme_reg[126]/D 0.00
0:00:52 64248.3 0.15 53.1 10.1 extreme_reg[126]/D 0.00
0:00:52 64316.2 0.14 52.8 10.1 extreme_reg[126]/D 0.00
0:00:53 64351.8 0.14 52.3 10.1 extreme_reg[126]/D 0.00
0:00:53 64353.5 0.14 52.1 12.7 extreme_reg[126]/D 0.00
0:00:53 64428.2 0.14 51.9 17.8 sum_reg[70]/D 0.00
0:00:53 64450.3 0.14 51.8 17.8 sum_reg[70]/D 0.00
0:00:53 64485.9 0.14 51.6 17.8 extreme_reg[23]/D 0.00
0:00:53 64487.6 0.14 51.1 17.8 extreme_reg[23]/D 0.00
0:00:53 64548.7 0.13 48.4 17.8 sum_reg[119]/D 0.00
0:00:54 64630.2 0.12 42.4 17.8 sum_reg[70]/D 0.00
0:00:54 64670.9 0.12 41.1 17.8 sum_reg[70]/D 0.00
0:00:54 64679.4 0.11 39.2 17.8 extreme_reg[23]/D 0.00
0:00:54 64723.6 0.11 38.2 20.3 extreme_reg[23]/D 0.00
0:00:54 64732.0 0.11 37.6 20.3 extreme_reg[23]/D 0.00
0:00:54 64835.6 0.11 34.5 20.3 iot_out_reg[8]/D 0.00
0:00:54 64864.4 0.10 32.9 20.3 peak_extreme_reg[111]/D 0.00
0:00:54 64869.5 0.10 32.3 20.3 sum_reg[70]/D 0.00
0:00:54 64893.3 0.10 32.3 20.3 extreme_reg[12]/D 0.00
0:00:54 64883.1 0.10 32.2 20.3 extreme_reg[12]/D 0.00
0:00:55 64906.9 0.10 31.6 20.3 extreme_reg[12]/D 0.00
0:00:55 64927.2 0.10 31.4 20.3 extreme_reg[12]/D 0.00
0:00:55 64906.9 0.10 31.3 20.3 extreme_reg[12]/D 0.00
0:00:55 64869.5 0.09 30.6 20.3 extreme_reg[12]/D 0.00
0:00:55 64845.8 0.09 30.3 20.3 peak_extreme_reg[54]/D 0.00
0:00:55 64839.0 0.09 29.9 20.3 counter_reg[10]/D 0.00
0:00:55 64852.6 0.09 29.6 20.3 extreme_reg[12]/D 0.00
0:00:55 64896.7 0.09 28.3 25.7 sum_reg[117]/D 0.00
0:00:55 64952.7 0.09 28.0 29.6 sum_reg[120]/D 0.00
0:00:55 64935.7 0.09 27.6 32.2 extreme_reg[51]/D 0.00
0:00:56 64956.1 0.09 27.4 32.2 extreme_reg[51]/D 0.00
0:00:56 64913.7 0.09 27.0 32.2 extreme_reg[51]/D 0.00
0:00:56 64895.0 0.08 26.2 32.2 sum_reg[70]/D 0.00
0:00:56 64906.9 0.08 26.4 32.2 extreme_reg[51]/D 0.00
0:00:56 64893.3 0.08 26.3 32.2 extreme_reg[51]/D 0.00
0:00:56 64881.4 0.08 25.8 32.2 iot_out_reg[15]/D 0.00
0:00:56 64872.9 0.08 25.4 34.7 peak_extreme_reg[49]/D 0.00
0:00:56 64925.5 0.08 25.2 34.7 extreme_reg[71]/D 0.00
0:00:56 64961.2 0.08 25.0 34.7 extreme_reg[71]/D 0.00
0:00:56 64959.5 0.08 24.2 34.7 extreme_reg[71]/D 0.00
0:00:57 64961.2 0.08 24.1 34.7 iot_out_reg[15]/D 0.00
0:00:57 64978.2 0.08 23.8 34.7 extreme_reg[71]/D 0.00
0:00:57 64959.5 0.07 23.5 34.7 extreme_reg[71]/D 0.00
0:00:57 64964.6 0.07 22.4 34.7 iot_out_reg[118]/D 0.00
0:00:57 64932.3 0.07 22.1 34.7 peak_extreme_reg[53]/D 0.00
0:00:57 64901.8 0.07 22.1 34.7 extreme_reg[71]/D 0.00
0:00:57 64893.3 0.07 22.0 34.7 extreme_reg[71]/D 0.00
0:00:57 64867.8 0.07 22.4 34.7 extreme_reg[71]/D 0.00
0:00:57 64872.9 0.07 22.1 34.7 peak_extreme_reg[0]/D 0.00
0:00:58 64886.5 0.07 21.9 34.7 sum_reg[84]/D 0.00
0:00:58 64903.5 0.07 21.5 34.7 sum_reg[99]/D 0.00
0:00:58 64915.4 0.07 18.7 34.7 extreme_reg[12]/D 0.00
0:00:58 64939.1 0.06 18.5 34.7 peak_extreme_reg[46]/D 0.00
0:00:58 64954.4 0.06 18.6 34.7 extreme_reg[12]/D 0.00
0:00:58 64973.1 0.06 18.5 34.7 peak_extreme_reg[46]/D 0.00
0:00:58 64978.2 0.06 18.3 34.7 peak_extreme_reg[51]/D 0.00
0:00:58 64981.6 0.06 18.5 34.7 extreme_reg[12]/D 0.00
0:00:58 64959.5 0.06 18.3 34.7 extreme_reg[7]/D 0.00
0:00:59 64932.3 0.06 18.0 34.7 peak_extreme_reg[46]/D 0.00
0:00:59 64951.0 0.06 17.8 34.7 peak_extreme_reg[46]/D 0.00
0:00:59 64920.5 0.06 17.8 34.7 extreme_reg[7]/D 0.00
0:00:59 64903.5 0.06 17.7 32.2 extreme_reg[7]/D 0.00
0:00:59 64893.3 0.06 17.5 32.2 extreme_reg[7]/D 0.00
0:00:59 64903.5 0.06 17.2 32.2 sum_reg[70]/D 0.00
0:00:59 64915.4 0.06 17.1 32.2 extreme_reg[7]/D 0.00
0:00:59 64922.2 0.05 16.8 32.2 extreme_reg[7]/D 0.00
0:00:59 64913.7 0.05 15.5 32.2 peak_extreme_reg[46]/D 0.00
0:00:59 64925.5 0.05 15.1 32.2 extreme_reg[7]/D 0.00
0:00:59 64951.0 0.05 15.2 32.2 extreme_reg[7]/D 0.00
0:00:59 64898.4 0.05 14.9 32.2 extreme_reg[7]/D 0.00
0:00:59 64910.3 0.05 14.7 36.1 sum_reg[70]/D 0.00
0:00:59 64913.7 0.05 14.3 36.1 peak_extreme_reg[46]/D 0.00
0:00:59 64928.9 0.05 13.4 36.1 extreme_reg[7]/D 0.00
0:01:00 64947.6 0.05 13.2 36.1 sum_reg[74]/D 0.00
0:01:00 64952.7 0.05 13.2 36.1 extreme_reg[7]/D 0.00
0:01:00 64957.8 0.05 12.9 36.1 extreme_reg[12]/D 0.00
0:01:00 64920.5 0.05 12.9 36.1 extreme_reg[35]/D 0.00
0:01:00 64930.6 0.05 12.9 36.1 extreme_reg[35]/D 0.00
0:01:00 64979.9 0.05 12.6 36.1 extreme_reg[35]/D 0.00
0:01:00 65007.0 0.05 12.4 36.1 sum_reg[70]/D 0.00
0:01:00 65001.9 0.04 11.1 36.1 iot_out_reg[118]/D 0.00
0:01:00 64998.5 0.04 10.8 36.1 sum_reg[120]/D 0.00
0:01:00 64964.6 0.04 10.6 36.1 extreme_reg[35]/D 0.00
0:01:00 64991.7 0.04 10.5 36.1 extreme_reg[35]/D 0.00
0:01:00 65010.4 0.04 10.2 37.5 sum_reg[70]/D 0.00
0:01:01 65080.0 0.04 9.9 37.5 sum_reg[72]/D 0.00
0:01:01 65090.2 0.04 9.9 37.5 sum_reg[70]/D 0.00
0:01:01 65115.7 0.04 9.6 37.5 sum_reg[95]/D 0.00
0:01:01 65141.1 0.04 9.4 37.5 sum_reg[74]/D 0.00
0:01:01 65161.5 0.04 8.9 37.5 sum_reg[124]/D 0.00
0:01:01 65186.9 0.04 8.7 37.5 sum_reg[129]/D 0.00
0:01:01 65215.8 0.04 8.3 37.5 sum_reg[126]/D 0.00
0:01:01 65226.0 0.04 8.6 37.5 sum_reg[126]/D 0.00
0:01:01 65220.9 0.04 8.4 37.5 peak_extreme_reg[46]/D 0.00
0:01:01 65268.4 0.03 7.5 37.5 peak_extreme_reg[46]/D 0.00
0:01:01 65344.8 0.03 6.4 41.5 sum_reg[126]/D 0.00
0:01:02 65353.3 0.03 5.6 41.5 extreme_reg[86]/D 0.00
0:01:02 65387.2 0.03 5.2 41.5 extreme_reg[86]/D 0.00
0:01:02 65441.6 0.02 4.5 41.5 peak_extreme_reg[46]/D 0.00
0:01:02 65438.2 0.02 4.1 41.5 sum_reg[66]/D 0.00
0:01:02 65467.0 0.02 3.8 41.5 sum_reg[84]/D 0.00
0:01:02 65439.9 0.02 3.8 41.5 extreme_reg[35]/D 0.00
0:01:02 65475.5 0.02 3.1 41.5 extreme_reg[35]/D 0.00
0:01:02 65477.2 0.02 2.4 41.5 extreme_reg[35]/D 0.00
0:01:02 65458.5 0.01 2.3 41.5 extreme_reg[35]/D 0.00
0:01:02 65463.6 0.01 1.1 41.5 iot_out_reg[65]/D 0.00
0:01:02 65424.6 0.01 1.1 41.5 extreme_reg[35]/D 0.00
0:01:03 65409.3 0.01 1.0 41.5 peak_extreme_reg[126]/D 0.00
0:01:03 65402.5 0.01 0.9 41.5 extreme_reg[35]/D 0.00
0:01:03 65363.5 0.01 0.8 38.9 peak_extreme_reg[97]/D 0.00
0:01:03 65372.0 0.01 0.6 38.9 extreme_reg[35]/D 0.00
0:01:03 65553.6 0.01 0.4 98.9 0.00
0:01:04 65546.8 0.00 0.2 98.9 peak_extreme_reg[0]/D 0.00
0:01:04 65540.0 0.00 0.0 98.9 peak_extreme_reg[0]/D 0.00
0:01:04 65543.4 0.00 0.0 98.9 0.00
0:01:05 65305.8 0.00 0.0 118.9 0.00
0:01:06 65295.6 0.00 0.0 118.9 0.00
Beginning Design Rule Fixing (min_path) (max_fanout) (max_capacitance)
----------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN MIN DELAY
TIME AREA SLACK COST RULE COST ENDPOINT COST
--------- --------- --------- --------- --------- ------------------------- -----------
0:01:06 65295.6 0.00 0.0 118.9 -0.00
0:01:06 65351.6 0.00 0.0 0.0 0.00
Beginning Area-Recovery Phase (cleanup)
-----------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN MIN DELAY
TIME AREA SLACK COST RULE COST ENDPOINT COST
--------- --------- --------- --------- --------- ------------------------- -----------
0:01:06 65351.6 0.00 0.0 0.0 0.00
0:01:06 65351.6 0.00 0.0 0.0 0.00
0:01:07 63754.3 0.06 5.6 0.0 0.00
0:01:07 63396.2 0.05 5.8 0.0 0.00
0:01:07 63324.9 0.05 5.9 0.0 0.00
0:01:07 63287.6 0.05 5.9 0.0 0.00
0:01:07 63268.9 0.05 5.9 0.0 0.00
0:01:07 63268.9 0.05 5.9 0.0 0.00
0:01:08 63223.1 0.00 0.0 0.0 0.00
0:01:08 61186.2 0.22 37.8 0.0 0.00
0:01:08 60220.4 0.20 34.0 0.0 0.00
0:01:09 59919.9 0.19 34.1 0.0 0.00
0:01:09 59901.2 0.19 34.1 0.0 0.00
0:01:09 59901.2 0.19 34.1 0.0 0.00
0:01:09 59901.2 0.19 34.1 0.0 0.00
0:01:09 59901.2 0.19 34.1 0.0 0.00
0:01:09 59901.2 0.19 34.1 0.0 0.00
0:01:09 60108.3 0.07 12.4 0.0 peak_extreme_reg[58]/D 0.00
0:01:09 60242.4 0.03 4.2 0.0 sum_reg[93]/D 0.00
0:01:10 60273.0 0.01 0.9 0.0 sum_reg[60]/D 0.00
0:01:10 60283.2 0.01 0.6 0.0 sum_reg[60]/D 0.00
0:01:11 60186.4 0.00 0.1 0.0 0.00
0:01:11 60244.1 0.00 0.0 0.0 0.00
0:01:11 60262.8 0.00 0.0 0.0 0.00
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db'
Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios
Optimization Complete
---------------------
1
compile -map_effort high -area_effort high -inc
====================================================================================================
| Flow Information |
----------------------------------------------------------------------------------------------------
| Flow | Design Compiler NXT |
====================================================================================================
| Design Information | Value |
====================================================================================================
| Number of Scenarios | 0 |
| Leaf Cell Count | 5458 |
| Number of User Hierarchies | 5 |
| Sequential Cell Count | 677 |
| Macro Count | 0 |
| Number of Power Domains | 0 |
| Number of Path Groups | 2 |
| Number of VT Class | 0 |
| Number of Clocks | 1 |
| Number of Dont Touch Cells | 0 |
| Number of Dont Touch Nets | 1 |
| Number of Size Only Cells | 0 |
| Design with UPF Data | false |
====================================================================================================
Information: There are 24 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Beginning Pass 1 Mapping (Incremental)
------------------------
Updating timing information
Information: Updating design information... (UID-85)
Beginning Mapping Optimizations (High effort) (Incremental)
-------------------------------
Beginning Incremental Implementation Selection
----------------------------------------------
Mapping 'IOTDF_DW01_add_0'
Mapping 'IOTDF_DW01_cmp6_0'
Mapping 'IOTDF_DW01_cmp6_1'
Mapping 'IOTDF_DW_mult_uns_1_0'
Selecting implementations
Building model 'DW01_NAND2'
Building model 'DW01_inc_width11' (rpl)
Beginning Delay Optimization Phase
----------------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN MIN DELAY
TIME AREA SLACK COST RULE COST ENDPOINT COST
--------- --------- --------- --------- --------- ------------------------- -----------
0:00:02 60262.8 0.00 0.0 0.0 0.00
0:00:03 60656.6 0.00 0.0 0.0 0.00
0:00:04 60483.5 0.00 0.0 0.0 0.00
0:00:04 60483.5 0.00 0.0 0.0 0.00
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db'
Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios
Optimization Complete
---------------------
1
write -format ddc -hierarchy -output "IOTDF.ddc"
Writing ddc file 'IOTDF.ddc'.
1
write_sdf IOTDF.sdf
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
Information: Writing timing information to file '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.sdf'. (WT-3)
Information: Updating design information... (UID-85)
1
write_file -format verilog -hierarchy -output IOTDF_syn.v
Writing verilog file '/home/M12/chenneil90121/ic_contest_mock3/IOTDF_syn.v'.
Warning: Verilog writer has added 1 nets to module IOTDF using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the verilog writer. (VO-11)
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
1
report_area > area.log
report_timing > timing.log
report_qor > IOTDF.qor
report_area -designware -hierarchy
****************************************
Report : area
Design : IOTDF
Version: U-2022.12
Date : Sat Mar 23 19:02:14 2024
****************************************
Library(s) Used:
slow (File: /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db)
Number of ports: 1351
Number of nets: 7056
Number of cells: 5565
Number of combinational cells: 4783
Number of sequential cells: 677
Number of macros/black boxes: 0
Number of buf/inv: 1319
Number of references: 107
Combinational area: 35791.376065
Buf/Inv area: 5519.944740
Noncombinational area: 24692.077913
Macro/Black Box area: 0.000000
Net Interconnect area: undefined (No wire load specified)
Total cell area: 60483.453978
Total area: undefined
Hierarchical area distribution
------------------------------
Global cell area Local cell area
------------------- ------------------------------
Hierarchical cell Absolute Percent Combi- Noncombi- Black-
Total Total national national boxes Design
-------------------------------- ---------- ------- ---------- ---------- ------ --------------------
IOTDF 60483.4540 100.0 13794.7697 24692.0779 0.0000 IOTDF
add_109 195.2010 0.3 195.2010 0.0000 0.0000 IOTDF_DW01_inc_0
add_171_aco 10252.2959 17.0 10252.2959 0.0000 0.0000 IOTDF_DW01_add_1
mult_add_171_aco 1240.7994 2.1 1240.7994 0.0000 0.0000 IOTDF_DW_mult_uns_1
r403 5115.9635 8.5 5115.9635 0.0000 0.0000 IOTDF_DW01_cmp6_J2_0
r409 5192.3465 8.6 5192.3465 0.0000 0.0000 IOTDF_DW01_cmp6_2
-------------------------------- ---------- ------- ---------- ---------- ------ --------------------
Total 35791.3761 24692.0779 0.0000
Area of detected synthetic parts
--------------------------------
Perc. of
Module Implem. Count Area cell area
----------- ------- ----- ----------- ---------
DW01_add pparch 1 10252.3223 17.0%
DW01_cmp6 pparch 2 10308.3389 17.0%
DW01_inc rpl 1 195.2010 0.3%
DW_mult_uns pparch 1 1240.7996 2.1%
----------- ------- ----- ----------- ---------
Total: 5 21996.6617 36.4%
Estimated area of ungrouped synthetic parts
-------------------------------------------
Estimated Perc. of
Module Implem. Count Area cell area
------ ------- ----- ---------- ---------
DW_cmp apparch 4 686.2597 1.1%
------ ------- ----- ---------- ---------
Total: 4 686.2597 1.1%
Total synthetic cell area: 22682.9214 37.5% (estimated)
1
report_timing
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : IOTDF
Version: U-2022.12
Date : Sat Mar 23 19:02:14 2024
****************************************
Operating Conditions: slow Library: slow
Wire Load Model Mode: top
Startpoint: peak_extreme_reg[61]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: peak_extreme_reg[41]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 1.00 1.00
peak_extreme_reg[61]/CK (DFFRHQX1) 0.00 1.00 r
peak_extreme_reg[61]/Q (DFFRHQX1) 0.24 1.24 f
r409/B[61] (IOTDF_DW01_cmp6_2) 0.00 1.24 f
r409/U1261/Y (INVX1) 0.08 1.32 r
r409/U1020/Y (XNOR2X1) 0.16 1.48 r
r409/U744/Y (OAI21XL) 0.11 1.60 f
r409/U974/Y (AOI21X1) 0.12 1.72 r
r409/U903/Y (OAI21X1) 0.08 1.80 f
r409/U965/Y (AOI21X1) 0.19 1.99 r
r409/U907/Y (OAI21X4) 0.10 2.09 f
r409/U263/Y (AOI21X4) 0.11 2.20 r
r409/U7/Y (OAI21X4) 0.07 2.27 f
r409/U1054/Y (NOR2BX4) 0.12 2.39 f
r409/GT (IOTDF_DW01_cmp6_2) 0.00 2.39 f
U2022/Y (OR3X4) 0.18 2.57 f
U1855/Y (CLKINVX1) 0.06 2.63 r
U1629/Y (OR2X4) 0.12 2.74 r
U1258/Y (INVX1) 0.06 2.80 f
U1304/Y (INVX3) 0.08 2.88 r
U1205/Y (INVX4) 0.12 3.00 f
U2062/Y (OAI221XL) 0.18 3.18 r
peak_extreme_reg[41]/D (DFFRHQX1) 0.00 3.18 r
data arrival time 3.18
clock clk (rise edge) 2.50 2.50
clock network delay (ideal) 1.00 3.50
clock uncertainty -0.10 3.40
peak_extreme_reg[41]/CK (DFFRHQX1) 0.00 3.40 r
library setup time -0.22 3.18
data required time 3.18
-----------------------------------------------------------
data required time 3.18
data arrival time -3.18
-----------------------------------------------------------
slack (MET) 0.00
1
exit
Memory usage for this session 218 Mbytes.
Memory usage for this session including child processes 348 Mbytes.
CPU usage for this session 121 seconds ( 0.03 hours ).
Elapsed time for this session 84 seconds ( 0.02 hours ).
Thank you...
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