555 Timer Block Diagram using CircuiTikZ

555-timer.tex

% !TEX program = pdflatex
% !TEX options = --shell-escape -synctex=1 -interaction=nonstopmode -file-line-error "%DOC%"


\documentclass[preview]{standalone}


% Block diagrams & Flowcharts
% ========================================
\usepackage{tikz}
\usetikzlibrary{shapes,arrows}
\usetikzlibrary{calc,positioning}
\usetikzlibrary{backgrounds}
\tikzstyle{arrow} = [thick,->,>=latex']

\tikzset{
    block/.style = {draw, fill=white, rectangle, minimum height=2em, minimum width=2em},
    background rectangle/.style={fill=white},
}

% Circuits
% ========================================
\usepackage[americanvoltages, americancurrents, fulldiodes,siunitx]{circuitikz}
\tikzset{
    dot on notQ/.style={flipflop def={t4=\ctikztextnot{Q}, n4=1}},
    % Custom parameters for flipflops
    invert async SR/.style={flipflop def={%
                    tu={\ctikztextnot{RST}}, td={\ctikztextnot{SET}}}},
    add clk SR/.style={flipflop def={c2=1, t2={CLK}}},
    dot on RST/.style={flipflop def={nd=1}},
    dot invert RST/.style={flipflop def={nu=1}}
}

% Math
% ========================================
\usepackage{amsmath}
\sisetup{detect-weight=true}

\standaloneenv{circuitikz}


\begin{document}


\begin{circuitikz}[align=center, show background rectangle]

    \tikzstyle{title} = [font=\bfseries\fontsize{14}{15}\selectfont]

    %
    % FILLS
    %
    % Rectangle : Upper left -- Lower right
    % Voltage divider
    \fill[fill=green!70!blue] (-1.5, 0.5) rectangle (0.5, 9.5)
    node [title, text width=2cm,midway, left=1.5cm, green!70!blue]{{Voltage divider}};
    % Comparators
    \fill[fill=magenta!70] (2.5, 8.5) rectangle (5.5, 1.5);
    \path (2.5, 8.5 |- 5.5, 1.5) -- (5.5, 1.5) node [title, midway, below, magenta!70]{Comparators};
    % Flip-flop
    \fill[fill=orange] (6.5, 7) rectangle (9.5, 3);
    \path (6.5, 7 |- 9.5, 3) -- (9.5, 3) node [title, midway, below, orange]{SR flip-flop};
    % Transistor
    \fill[fill=cyan!60!black] (9, 1.25) rectangle (11, 0.25);
    \path (9, 1.25) node [title, left, cyan!70!black]{Discharge\\Transistor};
    % \path (9, 1.25 |- 11, 0.25) -- (11, 0.25) node [title, midway, below, cyan!70!black]{Discharge\\Transistor};

    % GND + Comp
    \draw{} (0, -1) node [label=-90:GND] (GND) {}
    (4, 3) node [op amp, noinv input up] (1_3comp){}
    (4, 7) node [op amp, noinv input up] (2_3comp){}

    % GND -- VCC
    (GND) to [short, o-] ++(0,1)
    to [R, l=\SI{5}{\kilo\ohm}] ++(0,3) -- (GND |- 1_3comp.+) coordinate (1_3VCC) -- (1_3comp.+)
    (1_3VCC) to [R, l=\SI{5}{\kilo\ohm}, *-*] (GND |- 2_3comp.-) coordinate (2_3VCC)
    (2_3VCC) to [R, l=\SI{5}{\kilo\ohm}, -o] ++(0, 4)
    node [label=VCC] (VCC) {}
    (2_3comp.-) -- ++(-1, 0) coordinate (ctl_line)
    to [short, *-o] (ctl_line |- VCC) node [label=90:CTL\\VOLT](CTL_VLT){}
    (ctl_line) -- (2_3VCC)

    % TRIG + THRESH
    (1_3comp.-) to [short, -o] (1_3comp.- -| -2.5, 0) node [label=180:TRIGGER](TRIG) {}
    (2_3comp.+) to [short, -o] (2_3comp.+ -| -2.5, 0) node [label=180:THRESH](THRESH) {}

    % SR flip-flop
    (8, 5) node[flipflop SR, dot on notQ, invert async SR, dot invert RST, add clk SR] (SR) {}
    (SR.up) to [short, -o] (SR.up |- VCC) node [label=90:RESET](RESET){}

    % Plug comparators to SR flip-flop
    (2_3comp.out) -- (2_3comp.out |- SR.pin 1) -- (SR.pin 1)
    (1_3comp.out) -- (1_3comp.out |- SR.pin 3) -- (SR.pin 3)

    % Discharge transistor
    (10, 0.5) node [npn, rotate=-90] (npn) {}
    (SR.pin 4) -- (SR.pin 4 -| npn.B) coordinate (disch_line) to [short, *-] (npn.B)
    (npn.E) -- (npn.E -| GND)
    (npn.C) to [short, -o] (npn.C -| 14.5,0) node [label=0:DISCH](DISCH){}
    ;

    %
    % FILLS
    %
    % Output inverter
    \coordinate (out_not) at ($(disch_line)+(2,0)$);
    % UP LEft and DOwn RIght
    \coordinate (onot_uple) at ($(out_not)+(-1.5, 1)$);
    \coordinate (onot_dori) at ($(out_not)+(1.5, -1)$);
    \fill[fill=red!70] (onot_uple) rectangle (onot_dori);
    \path (onot_uple |- onot_dori) -- (onot_dori) node [title, midway, below, red!70]{Output\\Inverter};

    % Output
    \draw{}
    (disch_line) ++(2, 0) node[not port](out_not){}
    (disch_line) -- (out_not.in)
    (out_not.out) to [short, -o] (out_not.out -| DISCH) node [label=0:OUT](OUT){}


    %
    % PINS & NODES
    %
    (1_3VCC) node [left] {$\dfrac{1}{3}$VCC}
    (2_3VCC) node [left] {$\dfrac{2}{3}$VCC}

    (VCC) node [below left] {8}
    (GND) node [above left] {1}
    (THRESH) node [above right] {6}
    (TRIG) node [above right] {2}
    (RESET) node [below left] {4}
    (CTL_VLT) node [below left] {5}
    (DISCH) node [above left] {7}
    (OUT) node [above left] {3}
    ;

    % OUTLINE
    \draw[black, thick, dashed] (-2, 10) rectangle (14, -0.5);
    \path (14, 10) node [title, below left]{555\\Timer};
\end{circuitikz}


\end{document}