gray_code.v

/* Generated by Yosys 0.30+1 (git sha1 5813809ad, clang 10.0.0-4ubuntu1 -fPIC -Os) */

(* generator = "nMigen" *)
(* top =  1  *)
(* \nmigen.hierarchy  = "top" *)
module top(clk);
  (* src = "gray_code.py:25" *)
  wire [3:0] async_gray_count;
  (* src = "/home/turro/workspace/venv/lib/python3.8/site-packages/nmigen/hdl/ir.py:526" *)
  input clk;
  wire clk;
  (* src = "gray_code.py:26" *)
  wire [3:0] latched_gray_count;
  TRELLIS_SLICE #(
    .LUT0_INITVAL(14'h3cc3),
    .LUT1_INITVAL(16'he44e),
    .MODE("LOGIC"),
    .REG0_SD("1"),
    .REG1_SD("1")
  ) lutA (
    .A0(async_gray_count[0]),
    .A1(async_gray_count[0]),
    .B0(async_gray_count[1]),
    .B1(async_gray_count[1]),
    .C0(async_gray_count[2]),
    .C1(async_gray_count[2]),
    .CLK(clk),
    .D0(async_gray_count[3]),
    .D1(async_gray_count[3]),
    .DI0(async_gray_count[0]),
    .DI1(async_gray_count[1]),
    .F0(async_gray_count[0]),
    .F1(async_gray_count[1]),
    .Q0(latched_gray_count[0]),
    .Q1(latched_gray_count[1])
  );
  TRELLIS_SLICE #(
    .LUT0_INITVAL(16'hb0f4),
    .LUT1_INITVAL(16'hfe10),
    .MODE("LOGIC"),
    .REG0_SD("1"),
    .REG1_SD("1")
  ) lutB (
    .A0(async_gray_count[0]),
    .A1(async_gray_count[0]),
    .B0(async_gray_count[1]),
    .B1(async_gray_count[1]),
    .C0(async_gray_count[2]),
    .C1(async_gray_count[2]),
    .CLK(clk),
    .D0(async_gray_count[3]),
    .D1(async_gray_count[3]),
    .DI0(async_gray_count[2]),
    .DI1(async_gray_count[3]),
    .F0(async_gray_count[2]),
    .F1(async_gray_count[3]),
    .Q0(latched_gray_count[2]),
    .Q1(latched_gray_count[3])
  );
endmodule