PIC16F18854 CWG Setup Assembly Code

PIC16F18854_CWG_Setup.asm

; ---------[ CWG Setup ]------------------------------------------
; The sequence below follows "20.12 Configuring the CWG" in the PIC16(L)F18854 datasheet:
; http://ww1.microchip.com/downloads/en/DeviceDoc/40001826B.pdf

; Configuring the CWG, Step-1
    banksel TRISB               ; [Bank 0]
    movlw   b'11111111'         ; RB0 & RB1 are CWG Outputs but must be Inputs for now.
    movwf   TRISB               ;  PORTB 
; Configuring the CWG, Steps-2&3
    banksel CWG1CON0            ; [Bank 12]
    movlw   b'00000100'         ; Disable CWG with EN-bit7=0 & set MODE=Half-Bridge
    movwf   CWG1CON0
; Configuring the CWG, Step-4
; Deadband/dead-time = 20 x 62.5E-9 = 1.25us
    movlw   .20                 ; Put 20d into "CWG Rising DEAD-BAND Count Register"
    movwf   CWG1DBR             ;  (20 clock cycles = 1.25us @ HFINTOSC=16MHz)
    movlw   .20                 ; Put 20d into "CWG Falling DEAD-BAND Count Register"
    movwf   CWG1DBF
; Configuring the CWG, Step-5(a/c)
    movlw   b'10000000'         ; Disable Shut-Down on all pins in CWGxAS1 register.
    movwf   CWG1AS1
; Configuring the CWG, Step-5(b/d)
    movlw   b'10101000'         ; Set SHUTDOWN bit, Clear REN bit, CWGxA&B LO on shutdown. 
    movwf   CWG1AS0
; Configuring the CWG, Step-6
    movlw   b'00001000'         ; Select NC01_out as the input source
    movwf   CWG1ISM
; Configuring the CWG, Step-7(a)
    bsf     CWG1CLKCON, CS      ; Select HFINTOSC 16MHz (must be 16MHz!)
; Configuring the CWG, Step-7(b)      
    clrf    CWG1CON1            ; CWG Input Value is ReadOnly?, Normal Polarity on CWGxA, etc.
; Configuring the CWG, Step-7(c) 
    banksel PPSLOCK             ; [Bank 29] (Ensure Interrupts are disabled first)
    movlw   0x55
    movwf   PPSLOCK
    movlw   0xAA
    movwf   PPSLOCK
    bcf     PPSLOCK, PPSLOCKED  ; Unlocks PPS
;
    banksel RB0PPS              ; [Bank 30]
    movlw   0x05                ; Set CWG1A as an Output on RB0
    movwf   RB0PPS
    movlw   0x06                ; Set CWG1B as an Output on RB1
    movwf   RB1PPS
;
    banksel PPSLOCK             ; [Bank 29] 
    movlw   0x55
    movwf   PPSLOCK
    movlw   0xAA
    movwf   PPSLOCK
    bcf     PPSLOCK, PPSLOCKED  ; Locks PPS (remains locked until reset, per config bits)
; Configuring the CWG, Step-8
    banksel CWG1CON0            ; [Bank 12]
    bsf     CWG1CON0, EN        ; Set the EN bit.
; Configuring the CWG, Step-9
    banksel TRISB               ; [Bank 0]
    movlw   b'11111100'         ; Set RB0 & RB1 (CWG outputs) to Outputs
    movwf   TRISB               ;  PORTB 
; Configuring the CWG, Step-10
    banksel CWG1AS0             ; [Bank 12]
    bcf     CWG1AS0, SHUTDOWN   ; Clear SHUTDOWN bit to start CWG.