0001-arm64-dts-rockchip-enable-rk356x-proper-msi-support-1.patch

From 3a462a72cd6c1a6e6b78dae647a86ba6060de55b Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 23 Jan 2022 08:01:20 -0500
Subject: [PATCH] arm64: dts: rockchip: enable rk356x proper msi support

The mbi-aliases is nice in theory, but it is completely broken in
practice.
The following cards have exhibited crashing while using MSIs on the
mbi-alias:
Intel NICs (1G and 10G)
SATA controllers
NVMe controllers.

Fix this by correctly implementing MSIs in the ITS *dependent on the ITS
workaround patch*

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 6a450b20f1b2..def4aebd0961 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -312,9 +312,16 @@ gic: interrupt-controller@fd400000 {
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		mbi-alias = <0x0 0xfd410000>;
-		mbi-ranges = <296 24>;
-		msi-controller;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		its: interrupt-controller@fd440000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0xfd440000 0x0 0x20000>;
+		};
 	};
 
 	usb_host0_ehci: usb@fd800000 {
@@ -899,7 +906,7 @@ pcie2x1: pcie@fe260000 {
 		num-ib-windows = <6>;
 		num-ob-windows = <2>;
 		max-link-speed = <2>;
-		msi-map = <0x0 &gic 0x0 0x1000>;
+		msi-map = <0x0 &its 0x0 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy2 PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
-- 
2.25.1

0001-arm64-dts-rockchip-fix-rk356x-pcie-large-address-spa.patch

From 7219cc9c9836608863fd3108177f19d290050c02 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 23 Jan 2022 22:22:28 -0500
Subject: [PATCH] arm64: dts: rockchip: fix rk356x pcie large address space

It was recommended to not put the PCIe IO address space at 0x0, instead
place it at 0x40000000, by the LKML.
Unfortunately, it seems the driver places the config address space at
0x0 when the IO address space isn't already there.
For some reason the gap causes issues with the driver.
This leads to inbound data corruption on large file transfers.

Correct this by placing the IO address space back at 0x0.
This should probably be fixed by moving the config address space to the
ranges property, but the driver currently doesn't support this.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index b869bfd60bc7..68b30f2ca583 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -911,18 +911,12 @@ pcie2x1: pcie@fe260000 {
 		phys = <&combphy2 PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
 		power-domains = <&power RK3568_PD_PIPE>;
-/*
-		reg = <0x3 0xc0000000 0x0 0x400000>,
-		      <0x0 0xfe260000 0x0 0x10000>,
-		      <0x3 0x3f800000 0x0 0x800000>;
-		ranges = <0x01000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000
-			  0x02000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>;
-*/
-		reg = <0x0 0xf6800000 0x0 0x00400000>,
+
+		reg = <0x3 0xc0000000 0x0 0x00400000>,
 		      <0x0 0xfe260000 0x0 0x00010000>,
-		      <0x0 0xf5d00000 0x0 0x00100000>;
-		ranges = <0x02000000 0x0 0xf5000000 0x0 0xf4000000 0x0 0x01d00000>,
-			 <0x01000000 0x0 0xf5e00000 0x0 0xf5e00000 0x0 0x00100000>;
+		      <0x3 0x3f000000 0x0 0x01000000>;
+		ranges = <0x01000000 0x0 0x3f700000 0x3 0x3e000000 0x0 0x01000000
+			  0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3e000000>;
 
 		reg-names = "dbi", "apb", "config";
 		resets = <&cru SRST_PCIE20_POWERUP>;
-- 
2.25.1

0001-arm64-dts-rockchip-rk356x-move-to-lower-pcie-address-2.patch

From 3c432b65cc1e4bd10d25a94ead20134056a020d8 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 23 Jan 2022 11:27:54 -0500
Subject: [PATCH] arm64: dts: rockchip: rk356x move to lower pcie address space

It seems inbound address translation is broken to the address space
above 12G. Fix it by moving to the smaller address space below 4G for
now.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index def4aebd0961..b869bfd60bc7 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -911,11 +911,19 @@ pcie2x1: pcie@fe260000 {
 		phys = <&combphy2 PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
 		power-domains = <&power RK3568_PD_PIPE>;
+/*
 		reg = <0x3 0xc0000000 0x0 0x400000>,
 		      <0x0 0xfe260000 0x0 0x10000>,
 		      <0x3 0x3f800000 0x0 0x800000>;
-		ranges = <0x1000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000
-			  0x2000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>;
+		ranges = <0x01000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000
+			  0x02000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>;
+*/
+		reg = <0x0 0xf6800000 0x0 0x00400000>,
+		      <0x0 0xfe260000 0x0 0x00010000>,
+		      <0x0 0xf5d00000 0x0 0x00100000>;
+		ranges = <0x02000000 0x0 0xf5000000 0x0 0xf4000000 0x0 0x01d00000>,
+			 <0x01000000 0x0 0xf5e00000 0x0 0xf5e00000 0x0 0x00100000>;
+
 		reg-names = "dbi", "apb", "config";
 		resets = <&cru SRST_PCIE20_POWERUP>;
 		reset-names = "pipe";
-- 
2.25.1