TableGen assert

SM83.td

//===-- SM83.td - Target definition file for the Sharp SM83 --*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===------------------------------------------------------------------------===//
//
// This is a target description file for the Sharp SM83 architecture, referred
// to here as the "SM83" architecture.
//
//===------------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===------------------------------------------------------------------------===//
// Register file, instruction descriptions, and calling conventions
//===------------------------------------------------------------------------===//
include "SM83RegisterInfo.td"
include "SM83InstrInfo.td"
// include "SM83CallingConv.td"

def SM83InstrInfo : InstrInfo;

//===------------------------------------------------------------------------===//
// Define the target
//===------------------------------------------------------------------------===//
def SM83 final : public Target {
  let InstructionSet = SM83InstrInfo;
}

SM83InstrFormats.td

//===-- SM83InstrInfo.td - Target Description for SM83 -----*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

// generic SM83 instruction
class SM83Instruction<dag outs, dag ins, string asmstr, list<dag> pattern = []>
  : Instruction
{
  let Namespace = "SM83";

  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString = asmstr;
  let Pattern = pattern;
}

class SM83Inst8<dag outs, dag ins, string asmstr, list<dag> pattern = []>
  : SM83Instruction<outs, ins, asmstr, pattern>
{
  field bits<8> Inst;

  let Size = 1;
}

class SM83Inst16<dag outs, dag ins, string asmstr, list<dag> pattern>
  : SM83Instruction<outs, ins, asmstr, pattern>
{
  field bits<16> Inst;

  let Size = 2;
}

class SM83Inst24<dag outs, dag ins, string asmstr, list<dag> pattern>
  : SM83Instruction<outs, ins, asmstr, pattern>
{
  field bits<24> Inst;
 
  let Size = 3;
}

// arithmetic operations
class SM83ALU<bits<3> op> {
  bits<3> Value = op;
}
def ALU_ADD : SM83ALU<0b000>;
def ALU_ADC : SM83ALU<0b001>;
def ALU_SUB : SM83ALU<0b010>;
def ALU_SBC : SM83ALU<0b011>;
def ALU_AND : SM83ALU<0b100>;
def ALU_XOR : SM83ALU<0b101>;
def ALU_OR  : SM83ALU<0b110>;
def ALU_CP  : SM83ALU<0b111>;

let Uses = [A], Defs = [A, FLAGS] in {
  class ALU_r<SM83ALU op, dag outs, dag ins, string asmstr, list<dag> pattern>
    : SM83Inst8<outs, ins, asmstr, pattern>
  {
      bits<3> src;

      let Inst{7-6} = 0b10;
      let Inst{5-3} = op.Value;
      let Inst{2-0} = src;
  }

  class ALU_i<SM83ALU op, dag outs, dag ins, string asmstr, list<dag> pattern>  
    : SM83Inst16<outs, ins, asmstr, pattern>
  {
      bits<8> imm;

      let Inst{7-6}  = 0b11;
      let Inst{5-3}  = op.Value;
      let Inst{2-0}  = 0b110;
      let Inst{15-8} = imm;
  }
}

class PrefixCB<dag outs, dag ins, string asmstr, list<dag> pattern>
  : SM83Inst16<outs, ins, asmstr, pattern>
{
    let Inst{7-0} = 0xCB;
}

// shifts and rotates
class SM83SHRO<bits<3> type> {
    bits<3> Value = type;
}
def RO_RLC  : SM83SHRO<0b000>;
def RO_RRC  : SM83SHRO<0b001>;
def RO_RL   : SM83SHRO<0b010>;
def RO_RR   : SM83SHRO<0b011>;
def SH_SLA  : SM83SHRO<0b100>;
def SH_SRA  : SM83SHRO<0b101>;
def SH_SWAP : SM83SHRO<0b110>;
def SH_SRL  : SM83SHRO<0b111>;

class SHRO_r<SM83SHRO type, dag outs, dag ins, string asmstr, list<dag> pattern>
  : PrefixCB<outs, ins, asmstr, pattern>
{
    bits<3> dst;

    let Inst{15-14} = 0b00;
    let Inst{13-11} = type.Value;
    let Inst{10-8}  = dst;
}

// bit tests and sets
class SM83BTS<bits<2> op> {
  bits<2> Value = op;
}
// 00 is shifts and rotates
def BTS_BIT : SM83BTS<0b01>;
def BTS_RES : SM83BTS<0b10>;
def BTS_SET : SM83BTS<0b11>;

class BTS_ri<SM83BTS op, dag outs, dag ins, string asmstr, list<dag> pattern>
  : PrefixCB<outs, ins, asmstr, pattern>
{
    bits<3> dst;
    bits<3> idx;

    let Inst{15-14} = op.Value;
    let Inst{13-11} = idx;
    let Inst{10-8}  = dst;
}

SM83InstrInfo.td

//===-- SM83InstrInfo.td - SM83 Instruction Descriptions ---*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes SM83 instructions in TableGen format.
//
//===----------------------------------------------------------------------===//

include "SM83InstrFormats.td"

multiclass ALU_ri<string opstr, SM83ALU opc, SDPatternOperator op> {
  def r : ALU_r<opc,
                (outs), (ins GR8:$src),
		opstr # " a, $src",
                [(set A, (op A, GR8:$src))]>;
  def r : ALU_i<opc,
                (outs), (ins i8:$imm),
                opstr # " a, $imm",
                [(set A, (op A, i8imm:$imm))]>;
}

defm ADD : ALU_ri<"add", 0b000, add>;
defm SUB : ALU_ri<"sub", 0b010, sub>;
defm AND : ALU_ri<"and", 0b100, and>;
defm XOR : ALU_ri<"xor", 0b101, xor>;
defm OR  : ALU_ri<"or" , 0b110, or >;

def LDddnn : SM83Inst24<(outs AR16:$dst),
                        (ins i16:$src),
                        "ld $dst, $src",
                        [(set $dst, i16imm:$src)]>
{
  bits<2> dst;
  bits<16> src;

  let Inst{7-6} = 0b00;
  let Inst{5-4} = dst; // Destination
  let Inst{3-0} = 0b0001;

  let Inst{8-23} = imm; // Operand
}

SM83RegisterInfo.td

//===- SM83RegisterInfo.td - Describe the SM83 Register File --*- tablegen -*-==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===------------------------------------------------------------------------===//
//
// This file describes the SM83 Register file, defining the registers themselves,
// aliases between the registers, and the register classes built out of the
// registers.
//
//===------------------------------------------------------------------------===//

class SM83Reg<string name,
              bits<16> enc = -1,
              list<Register> subregs = []>
  : RegisterWithSubRegs<name, subregs>
{
  let Namespace = "SM83";
  let HWEncoding = enc;
  let SubRegs = subregs;
}

// Subregister indices.
let Namespace = "SM83" in {
  def sub_low : SubRegIndex<8>;
  def sub_high : SubRegIndex<8, 8>;
}

//===----------------------------------------------------------------------===//
// Register definitions...
//

// 8-bit registers
def B : SM83Reg<"b", 0>;
def C : SM83Reg<"c", 1>;
def D : SM83Reg<"d", 2>;
def E : SM83Reg<"e", 3>;
def H : SM83Reg<"h", 4>;
def L : SM83Reg<"l", 5>;
// we don't want [hl] to be allocated
def A : SM83Reg<"a", 7>;
def FLAGS : SM83Reg<"f">;

let SubRegIndices = [sub_high, sub_low],
    CoveredBySubRegs = 1 in
{
  // 16-bit registers
  def AF : SM83Reg<"af", 3, [A, FLAGS]>;
  def BC : SM83Reg<"bc", 0, [B, C]>;
  def DE : SM83Reg<"de", 1, [D, E]>;
  def HL : SM83Reg<"hl", 2, [H, L]>;
}
// stack pointer
def SP : SM83Reg<"sp", 3>;
// instruction pointer/program counter
def PC : SM83Reg<"pc">;

// miscellaneous
def IME : SM83Reg<"ime">;

//===----------------------------------------------------------------------===//
// Register class definitions...
//

// General-purpose 8-bit registers
def GR8 : RegisterClass<"SM83", [i8], 8, (add A, B, C, D, E, H, L)>;

// All 8-bit registers
def R8 : RegisterClass<"SM83", [i8], 8, (add GR8, FLAGS)>;

// General-purpose 16-bit registers
def GR16 : RegisterClass<"SM83", [i16], 8, (add BC, DE, HL)>;

// 16-bit registers that can be used with the stack
def SR16 : RegisterClass<"SM83", [i16], 8, (add GR16, AF)>;

// with arithmetic and load operations
def AR16 : RegisterClass<"SM83", [i16], 8, (add GR16, SP)>;

// All 16-bit registers
def R16 : RegisterClass<"SM83", [i16], 8, (add GR16, AF, SP, PC)>;