console.out

$ iverilog -s ParityTestbench -o sim MinimalExample.v 
$ ./sim 
		time,	iv,	clk,	ov	out
                   0,	0,	1,	0,	xxxxxxxxxxxxxxx0
                   1,	0,	1,	0,	xxxxxxxxxxxxxx00
                   2,	1,	1,	1,	xxxxxxxxxxxxx000
                   3,	0,	1,	1,	xxxxxxxxxxxx0001
                   4,	0,	1,	1,	xxxxxxxxxxx00011
                   5,	0,	1,	1,	xxxxxxxxxx000111
                   6,	1,	1,	0,	xxxxxxxxx0001111
                   7,	1,	1,	1,	xxxxxxxx00011110
                   8,	1,	1,	0,	xxxxxxx000111101
                   9,	0,	1,	0,	xxxxxx0001111010
                  10,	1,	1,	1,	xxxxx00011110100
                  11,	0,	1,	1,	xxxx000111101001
                  12,	1,	1,	0,	xxx0001111010011
                  13,	0,	1,	0,	xx00011110100110
                  14,	0,	1,	0,	x000111101001100
                  15,	1,	1,	1,	0001111010011000
                  16,	0,	1,	1,	0011110100110001

MinimalExample.v

module Parity(
  input        clock,
  input        i,
  output       o
);

reg state = 1'd0;
reg res = 1'd0;
always @(posedge clock)
begin
  case ({i, state})
    4'b00: {state, res} = {1'b0,1'b0}; //in 0, state 0
    4'b10: {state, res} = {1'b1,1'b1}; //in 1, state 0
    4'b01: {state, res} = {1'b1,1'b1}; //in 0, state 1
    4'b11: {state, res} = {1'b0,1'b0}; //in 1, state 1
  endcase
end
assign o = res;

endmodule

module ParityTestbench();

  reg [15:0] in=16'b1001010111000100, out;
  reg clock=0;
  reg iv=0;
  wire ov;

  always
    begin
    clock=0;
    iv=in[0];
    in=in >> 1;
    clock=1;
    out = out << 1 | ov;
    #1;
    end

  initial
    #16 $finish;

    Parity parity(.clock(clock),  .i(iv),  .o(ov));

    initial
        begin
            $display("\t\ttime,\tiv,\tclk,\tov\tout");
            $monitor("%d,\t%b,\t%b,\t%b,\t%b",$time, iv, clock, ov,out);
        end

endmodule