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JohnDMcMaster/gist:32673423993f5e81988c52ef56fe0177

Created May 26, 2018 00:49
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gistfile1.txt
`timescale 1ns / 1ps
module top(
input wire in_0,
input wire in_1,
input wire in_2,
input wire in_3,
input wire in_4,
input wire in_5,
input wire in_6,
input wire in_7,
input wire in_8,
input wire in_9,
input wire in_10,
input wire in_11,
input wire in_12,
input wire in_13,
input wire in_14,
input wire in_15,
input wire in_16,
input wire in_17,
input wire in_18,
input wire in_19,
input wire in_20,
input wire in_21,
input wire in_22,
input wire in_23,
input wire in_24,
input wire in_25,
input wire in_26,
input wire in_27,
input wire in_28,
input wire in_29,
input wire in_30,
input wire in_31,
input wire in_32,
input wire in_33,
input wire in_34,
input wire in_35,
input wire in_36,
input wire in_37,
input wire in_38,
input wire in_39,
output wire out_0,
output wire out_1,
output wire out_2,
output wire out_3,
output wire out_4,
output wire out_5,
output wire out_6,
output wire out_7,
output wire out_8,
output wire out_9,
output wire out_10,
output wire out_11,
output wire out_12,
output wire out_13,
output wire out_14,
output wire out_15,
output wire out_16,
output wire out_17,
output wire out_18,
output wire out_19,
output wire out_20,
output wire out_21,
output wire out_22,
output wire out_23,
output wire out_24,
output wire out_25,
output wire out_26,
output wire out_27,
output wire out_28,
output wire out_29,
output wire out_30,
output wire out_31,
output wire out_32,
output wire out_33,
output wire out_34,
output wire out_35,
output wire out_36,
output wire out_37,
output wire out_38,
output wire out_39,
output wire out_40,
output wire out_41,
output wire out_42,
output wire out_43,
output wire out_44,
output wire out_45,
output wire out_46,
output wire out_47,
output wire out_48,
output wire out_49,
output wire out_50,
output wire out_51);
my_FB1 fb1(
.in_0(in_0),
.in_1(in_1),
.in_2(in_2),
.in_3(in_3),
.in_4(in_4),
.in_5(in_5),
.in_6(in_6),
.in_7(in_7),
.in_8(in_8),
.in_9(in_9),
.in_10(in_10),
.in_11(in_11),
.in_12(in_12),
.in_13(in_13),
.in_14(in_14),
.in_15(in_15),
.in_16(in_16),
.in_17(in_17),
.in_18(in_18),
.in_19(in_19),
.in_20(in_20),
.in_21(in_21),
.in_22(in_22),
.in_23(in_23),
.in_24(in_24),
.in_25(in_25),
.in_26(in_26),
.in_27(in_27),
.in_28(in_28),
.in_29(in_29),
.in_30(in_30),
.in_31(in_31),
.in_32(in_32),
.in_33(in_33),
.in_34(in_34),
.in_35(in_35),
.in_36(in_36),
.in_37(in_37),
.in_38(in_38),
.in_39(in_39),
.out_0(out_0),
.out_1(out_1),
.out_2(out_2),
.out_3(out_3),
.out_4(out_4),
.out_5(out_5),
.out_6(out_6),
.out_7(out_7),
.out_8(out_8),
.out_9(out_9),
.out_10(out_10),
.out_11(out_11),
.out_12(out_12));
my_FB2 fb2(
.in_0(in_0),
.in_1(in_1),
.in_2(in_2),
.in_3(in_3),
.in_4(in_4),
.in_5(in_5),
.in_6(in_6),
.in_7(in_7),
.in_8(in_8),
.in_9(in_9),
.in_10(in_10),
.in_11(in_11),
.in_12(in_12),
.in_13(in_13),
.in_14(in_14),
.in_15(in_15),
.in_16(in_16),
.in_17(in_17),
.in_18(in_18),
.in_19(in_19),
.in_20(in_20),
.in_21(in_21),
.in_22(in_22),
.in_23(in_23),
.in_24(in_24),
.in_25(in_25),
.in_26(in_26),
.in_27(in_27),
.in_28(in_28),
.in_29(in_29),
.in_30(in_30),
.in_31(in_31),
.in_32(in_32),
.in_33(in_33),
.in_34(in_34),
.in_35(in_35),
.in_36(in_36),
.in_37(in_37),
.in_38(in_38),
.in_39(in_39),
.out_0(out_13),
.out_1(out_14),
.out_2(out_15),
.out_3(out_16),
.out_4(out_17),
.out_5(out_18),
.out_6(out_19),
.out_7(out_20),
.out_8(out_21),
.out_9(out_22),
.out_10(out_23),
.out_11(out_24),
.out_12(out_25));
endmodule
module my_FB1(
input wire in_0,
input wire in_1,
input wire in_2,
input wire in_3,
input wire in_4,
input wire in_5,
input wire in_6,
input wire in_7,
input wire in_8,
input wire in_9,
input wire in_10,
input wire in_11,
input wire in_12,
input wire in_13,
input wire in_14,
input wire in_15,
input wire in_16,
input wire in_17,
input wire in_18,
input wire in_19,
input wire in_20,
input wire in_21,
input wire in_22,
input wire in_23,
input wire in_24,
input wire in_25,
input wire in_26,
input wire in_27,
input wire in_28,
input wire in_29,
input wire in_30,
input wire in_31,
input wire in_32,
input wire in_33,
input wire in_34,
input wire in_35,
input wire in_36,
input wire in_37,
input wire in_38,
input wire in_39,
output wire out_0,
output wire out_1,
output wire out_2,
output wire out_3,
output wire out_4,
output wire out_5,
output wire out_6,
output wire out_7,
output wire out_8,
output wire out_9,
output wire out_10,
output wire out_11,
output wire out_12);
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_0;
assign out_0 = loc_out_0;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_1;
assign out_1 = loc_out_1;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_2;
assign out_2 = loc_out_2;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_3;
assign out_3 = loc_out_3;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_4;
assign out_4 = loc_out_4;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_5;
assign out_5 = loc_out_5;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_6;
assign out_6 = loc_out_6;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_7;
assign out_7 = loc_out_7;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_8;
assign out_8 = loc_out_8;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_9;
assign out_9 = loc_out_9;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_10;
assign out_10 = loc_out_10;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_11;
assign out_11 = loc_out_11;
(* LOC="FB1", keep="true", DONT_TOUCH="true" *) wire loc_out_12;
assign out_12 = loc_out_12;
assign loc_out_0 = !in_0 & !in_1 & in_2 & in_3 & !in_4 & in_5 & !in_6 & in_7 & in_8 & !in_9 & !in_10 & !in_11 & in_12 & !in_13 & !in_14 & in_15 & !in_16 & !in_17 & !in_18 & !in_19 & in_20 & !in_21 & !in_22 & !in_23 & in_24 & in_25 & in_26 & !in_27 & !in_28 & !in_29 & in_30 & !in_31 & in_32 & !in_33 & !in_34 & in_35 & !in_36 & in_37 & !in_38 & !in_39;
assign loc_out_1 = in_0 & in_1 & !in_2 & in_3 & in_4 & !in_5 & in_6 & !in_7 & in_8 & !in_9 & !in_10 & in_11 & in_12 & in_13 & !in_14 & !in_15 & in_16 & !in_17 & !in_18 & !in_19 & !in_20 & !in_21 & !in_22 & !in_23 & !in_24 & in_25 & !in_26 & in_27 & !in_28 & in_29 & in_30 & in_31 & !in_32 & !in_33 & in_34 & in_35 & !in_36 & !in_37 & !in_38 & !in_39;
assign loc_out_2 = !in_0 & !in_1 & !in_2 & in_3 & !in_4 & in_5 & !in_6 & !in_7 & !in_8 & !in_9 & !in_10 & !in_11 & in_12 & !in_13 & !in_14 & !in_15 & !in_16 & in_17 & !in_18 & in_19 & !in_20 & !in_21 & in_22 & !in_23 & in_24 & in_25 & !in_26 & in_27 & !in_28 & in_29 & in_30 & !in_31 & in_32 & !in_33 & !in_34 & !in_35 & !in_36 & in_37 & !in_38 & !in_39;
assign loc_out_3 = !in_0 & in_1 & in_2 & !in_3 & in_4 & in_5 & !in_6 & in_7 & in_8 & in_9 & !in_10 & !in_11 & in_12 & in_13 & in_14 & in_15 & in_16 & !in_17 & in_18 & in_19 & !in_20 & in_21 & in_22 & !in_23 & in_24 & in_25 & !in_26 & !in_27 & !in_28 & in_29 & !in_30 & !in_31 & in_32 & !in_33 & !in_34 & in_35 & in_36 & !in_37 & in_38 & in_39;
assign loc_out_4 = in_0 & in_1 & !in_2 & !in_3 & in_4 & in_5 & !in_6 & in_7 & !in_8 & in_9 & !in_10 & in_11 & in_12 & in_13 & in_14 & !in_15 & in_16 & in_17 & in_18 & !in_19 & !in_20 & !in_21 & !in_22 & in_23 & in_24 & !in_25 & in_26 & in_27 & in_28 & in_29 & !in_30 & in_31 & !in_32 & !in_33 & in_34 & in_35 & !in_36 & in_37 & !in_38 & in_39;
assign loc_out_5 = in_0 & in_1 & in_2 & !in_3 & in_4 & !in_5 & !in_6 & !in_7 & in_8 & in_9 & in_10 & !in_11 & !in_12 & !in_13 & in_14 & !in_15 & !in_16 & in_17 & !in_18 & !in_19 & in_20 & !in_21 & in_22 & in_23 & !in_24 & in_25 & !in_26 & !in_27 & in_28 & in_29 & !in_30 & !in_31 & in_32 & !in_33 & in_34 & !in_35 & in_36 & in_37 & in_38 & in_39;
assign loc_out_6 = !in_0 & !in_1 & in_2 & !in_3 & !in_4 & in_5 & !in_6 & in_7 & in_8 & in_9 & !in_10 & !in_11 & !in_12 & !in_13 & !in_14 & in_15 & !in_16 & !in_17 & !in_18 & !in_19 & !in_20 & !in_21 & in_22 & !in_23 & in_24 & !in_25 & in_26 & in_27 & in_28 & !in_29 & !in_30 & in_31 & !in_32 & in_33 & in_34 & !in_35 & in_36 & in_37 & !in_38 & in_39;
assign loc_out_7 = in_0 & in_1 & in_2 & in_3 & !in_4 & in_5 & in_6 & in_7 & in_8 & in_9 & !in_10 & in_11 & !in_12 & !in_13 & in_14 & in_15 & !in_16 & in_17 & in_18 & !in_19 & !in_20 & !in_21 & !in_22 & in_23 & !in_24 & !in_25 & in_26 & in_27 & !in_28 & in_29 & in_30 & in_31 & !in_32 & in_33 & in_34 & !in_35 & !in_36 & in_37 & in_38 & !in_39;
assign loc_out_8 = in_0 & !in_1 & in_2 & in_3 & in_4 & !in_5 & !in_6 & !in_7 & in_8 & !in_9 & in_10 & in_11 & in_12 & in_13 & !in_14 & in_15 & in_16 & in_17 & in_18 & !in_19 & in_20 & !in_21 & !in_22 & in_23 & in_24 & !in_25 & !in_26 & in_27 & !in_28 & in_29 & in_30 & in_31 & !in_32 & in_33 & !in_34 & in_35 & in_36 & !in_37 & !in_38 & !in_39;
assign loc_out_9 = in_0 & in_1 & in_2 & !in_3 & !in_4 & !in_5 & !in_6 & !in_7 & in_8 & in_9 & !in_10 & in_11 & in_12 & in_13 & in_14 & !in_15 & in_16 & in_17 & in_18 & !in_19 & !in_20 & !in_21 & !in_22 & !in_23 & !in_24 & !in_25 & !in_26 & !in_27 & !in_28 & !in_29 & !in_30 & in_31 & !in_32 & !in_33 & !in_34 & in_35 & !in_36 & in_37 & !in_38 & !in_39;
assign loc_out_10 = !in_0 & !in_1 & in_2 & in_3 & !in_4 & in_5 & in_6 & !in_7 & !in_8 & in_9 & in_10 & !in_11 & in_12 & !in_13 & in_14 & in_15 & !in_16 & in_17 & in_18 & in_19 & in_20 & !in_21 & !in_22 & !in_23 & in_24 & !in_25 & in_26 & !in_27 & in_28 & in_29 & in_30 & in_31 & in_32 & !in_33 & !in_34 & in_35 & !in_36 & in_37 & in_38 & !in_39;
assign loc_out_11 = in_0 & !in_1 & !in_2 & in_3 & !in_4 & in_5 & in_6 & !in_7 & !in_8 & !in_9 & in_10 & !in_11 & !in_12 & !in_13 & !in_14 & !in_15 & !in_16 & !in_17 & !in_18 & in_19 & !in_20 & in_21 & !in_22 & in_23 & !in_24 & in_25 & in_26 & !in_27 & in_28 & !in_29 & !in_30 & !in_31 & !in_32 & in_33 & in_34 & !in_35 & !in_36 & !in_37 & !in_38 & in_39;
assign loc_out_12 = in_0 & in_1 & in_2 & !in_3 & !in_4 & !in_5 & in_6 & in_7 & !in_8 & !in_9 & in_10 & in_11 & !in_12 & in_13 & !in_14 & !in_15 & !in_16 & in_17 & in_18 & in_19 & in_20 & in_21 & in_22 & !in_23 & !in_24 & in_25 & !in_26 & in_27 & in_28 & !in_29 & !in_30 & in_31 & in_32 & in_33 & in_34 & !in_35 & !in_36 & in_37 & in_38 & in_39;
endmodule
module my_FB2(
input wire in_0,
input wire in_1,
input wire in_2,
input wire in_3,
input wire in_4,
input wire in_5,
input wire in_6,
input wire in_7,
input wire in_8,
input wire in_9,
input wire in_10,
input wire in_11,
input wire in_12,
input wire in_13,
input wire in_14,
input wire in_15,
input wire in_16,
input wire in_17,
input wire in_18,
input wire in_19,
input wire in_20,
input wire in_21,
input wire in_22,
input wire in_23,
input wire in_24,
input wire in_25,
input wire in_26,
input wire in_27,
input wire in_28,
input wire in_29,
input wire in_30,
input wire in_31,
input wire in_32,
input wire in_33,
input wire in_34,
input wire in_35,
input wire in_36,
input wire in_37,
input wire in_38,
input wire in_39,
output wire out_0,
output wire out_1,
output wire out_2,
output wire out_3,
output wire out_4,
output wire out_5,
output wire out_6,
output wire out_7,
output wire out_8,
output wire out_9,
output wire out_10,
output wire out_11,
output wire out_12);
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_0;
assign out_0 = loc_out_0;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_1;
assign out_1 = loc_out_1;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_2;
assign out_2 = loc_out_2;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_3;
assign out_3 = loc_out_3;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_4;
assign out_4 = loc_out_4;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_5;
assign out_5 = loc_out_5;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_6;
assign out_6 = loc_out_6;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_7;
assign out_7 = loc_out_7;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_8;
assign out_8 = loc_out_8;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_9;
assign out_9 = loc_out_9;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_10;
assign out_10 = loc_out_10;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_11;
assign out_11 = loc_out_11;
(* LOC="FB2", keep="true", DONT_TOUCH="true" *) wire loc_out_12;
assign out_12 = loc_out_12;
assign loc_out_0 = !in_0 & in_1 & !in_2 & in_3 & in_4 & in_5 & !in_6 & !in_7 & !in_8 & in_9 & !in_10 & in_11 & !in_12 & in_13 & !in_14 & !in_15 & !in_16 & in_17 & in_18 & !in_19 & in_20 & in_21 & in_22 & in_23 & in_24 & in_25 & in_26 & in_27 & !in_28 & !in_29 & in_30 & in_31 & !in_32 & in_33 & in_34 & in_35 & !in_36 & in_37 & in_38 & in_39;
assign loc_out_1 = !in_0 & in_1 & in_2 & in_3 & in_4 & !in_5 & !in_6 & in_7 & !in_8 & !in_9 & !in_10 & in_11 & in_12 & !in_13 & in_14 & in_15 & in_16 & !in_17 & in_18 & in_19 & !in_20 & in_21 & in_22 & in_23 & !in_24 & !in_25 & in_26 & in_27 & !in_28 & !in_29 & !in_30 & in_31 & !in_32 & in_33 & !in_34 & !in_35 & in_36 & !in_37 & in_38 & !in_39;
assign loc_out_2 = in_0 & !in_1 & in_2 & in_3 & !in_4 & !in_5 & in_6 & in_7 & in_8 & in_9 & !in_10 & !in_11 & !in_12 & in_13 & !in_14 & in_15 & in_16 & !in_17 & in_18 & !in_19 & in_20 & in_21 & in_22 & !in_23 & !in_24 & !in_25 & !in_26 & in_27 & !in_28 & in_29 & !in_30 & !in_31 & in_32 & in_33 & !in_34 & in_35 & !in_36 & in_37 & !in_38 & in_39;
assign loc_out_3 = !in_0 & in_1 & in_2 & in_3 & in_4 & !in_5 & in_6 & !in_7 & in_8 & in_9 & !in_10 & in_11 & !in_12 & in_13 & in_14 & !in_15 & in_16 & !in_17 & in_18 & !in_19 & !in_20 & !in_21 & !in_22 & in_23 & in_24 & !in_25 & !in_26 & !in_27 & !in_28 & !in_29 & in_30 & !in_31 & in_32 & in_33 & in_34 & in_35 & in_36 & in_37 & !in_38 & in_39;
assign loc_out_4 = in_0 & !in_1 & !in_2 & in_3 & !in_4 & in_5 & !in_6 & in_7 & !in_8 & in_9 & in_10 & in_11 & !in_12 & !in_13 & in_14 & in_15 & in_16 & in_17 & in_18 & in_19 & !in_20 & in_21 & !in_22 & !in_23 & !in_24 & !in_25 & in_26 & !in_27 & in_28 & in_29 & !in_30 & !in_31 & !in_32 & !in_33 & !in_34 & !in_35 & !in_36 & in_37 & !in_38 & in_39;
assign loc_out_5 = in_0 & in_1 & in_2 & in_3 & !in_4 & in_5 & !in_6 & !in_7 & !in_8 & in_9 & !in_10 & in_11 & in_12 & in_13 & !in_14 & !in_15 & in_16 & in_17 & in_18 & in_19 & in_20 & in_21 & in_22 & !in_23 & in_24 & in_25 & !in_26 & !in_27 & in_28 & !in_29 & in_30 & in_31 & !in_32 & in_33 & !in_34 & in_35 & in_36 & !in_37 & in_38 & !in_39;
assign loc_out_6 = !in_0 & in_1 & in_2 & in_3 & in_4 & !in_5 & in_6 & !in_7 & in_8 & in_9 & in_10 & !in_11 & !in_12 & in_13 & in_14 & in_15 & in_16 & !in_17 & !in_18 & in_19 & in_20 & !in_21 & in_22 & !in_23 & in_24 & in_25 & in_26 & !in_27 & !in_28 & in_29 & in_30 & in_31 & !in_32 & in_33 & !in_34 & in_35 & in_36 & !in_37 & !in_38 & !in_39;
assign loc_out_7 = !in_0 & !in_1 & in_2 & !in_3 & in_4 & !in_5 & in_6 & !in_7 & !in_8 & !in_9 & in_10 & !in_11 & in_12 & !in_13 & !in_14 & in_15 & !in_16 & in_17 & in_18 & !in_19 & !in_20 & in_21 & !in_22 & in_23 & in_24 & in_25 & !in_26 & !in_27 & in_28 & !in_29 & !in_30 & !in_31 & !in_32 & !in_33 & in_34 & !in_35 & !in_36 & !in_37 & in_38 & !in_39;
assign loc_out_8 = !in_0 & !in_1 & in_2 & !in_3 & !in_4 & in_5 & in_6 & in_7 & in_8 & !in_9 & !in_10 & in_11 & !in_12 & in_13 & in_14 & !in_15 & in_16 & !in_17 & !in_18 & !in_19 & !in_20 & in_21 & in_22 & in_23 & !in_24 & !in_25 & in_26 & in_27 & !in_28 & !in_29 & in_30 & !in_31 & in_32 & in_33 & !in_34 & !in_35 & in_36 & in_37 & !in_38 & in_39;
assign loc_out_9 = in_0 & in_1 & !in_2 & in_3 & in_4 & !in_5 & in_6 & !in_7 & in_8 & in_9 & in_10 & in_11 & in_12 & !in_13 & !in_14 & in_15 & in_16 & in_17 & !in_18 & !in_19 & !in_20 & in_21 & in_22 & !in_23 & in_24 & in_25 & in_26 & in_27 & !in_28 & !in_29 & !in_30 & in_31 & in_32 & !in_33 & !in_34 & in_35 & in_36 & !in_37 & in_38 & !in_39;
assign loc_out_10 = !in_0 & in_1 & in_2 & !in_3 & !in_4 & !in_5 & in_6 & in_7 & !in_8 & in_9 & !in_10 & !in_11 & in_12 & !in_13 & in_14 & in_15 & in_16 & in_17 & in_18 & in_19 & !in_20 & in_21 & in_22 & in_23 & in_24 & in_25 & !in_26 & !in_27 & !in_28 & !in_29 & !in_30 & in_31 & !in_32 & in_33 & !in_34 & in_35 & in_36 & in_37 & !in_38 & in_39;
assign loc_out_11 = !in_0 & !in_1 & !in_2 & in_3 & !in_4 & in_5 & !in_6 & in_7 & !in_8 & !in_9 & in_10 & !in_11 & in_12 & !in_13 & !in_14 & !in_15 & !in_16 & !in_17 & in_18 & !in_19 & !in_20 & in_21 & !in_22 & in_23 & !in_24 & !in_25 & !in_26 & in_27 & !in_28 & in_29 & !in_30 & !in_31 & !in_32 & in_33 & in_34 & in_35 & in_36 & !in_37 & !in_38 & in_39;
assign loc_out_12 = !in_0 & !in_1 & !in_2 & !in_3 & in_4 & !in_5 & in_6 & !in_7 & in_8 & in_9 & !in_10 & in_11 & in_12 & !in_13 & !in_14 & !in_15 & !in_16 & in_17 & in_18 & in_19 & !in_20 & !in_21 & !in_22 & !in_23 & !in_24 & !in_25 & in_26 & !in_27 & !in_28 & !in_29 & !in_30 & in_31 & !in_32 & !in_33 & !in_34 & in_35 & !in_36 & !in_37 & in_38 & !in_39;
endmodule
Raw
gistfile2.txt
Considering device XC2C64A-5-VQ100.
ERROR:Cpld:847 - Insufficient number of input pins. This design needs at least
40 but only 38 left after allocating other resources.
ERROR:Cpld:29 - Device XC2C64A-5-VQ100 was disqualified.
ERROR:Cpld - The design requires too many resources to fit in any of the
specified devices or design rule checks prevent this design from fitting.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
Makefile:2: recipe for target 'all' failed
make: *** [all] Error 1
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