Introduce ARTIK05x and TizenRT

Introduce_ARTIK05x_and_TizenRT.md

Introduce ARTIK05x and TizenRT

Introduuce TizenRT OS

• lightweight RTOS-based platform to support low-end IoT devices.
• Forked from NuttX.
• You can Download at https://github.com/SamsungARTIK/TizenRT

Support Dev Board

The Samsung ARTIK™ 05X Module is a highly integrated module for secure Internet of Things (IoT) devices that require Wi-Fi®. It is based on an ARM® Cortex® R4 core with on-chip memories, a complete 2.4GHz Wi-Fi® Phy, MAC layer processing, a large complement of standard digital buses, a PUF-based security system and power management. The module is packaged with additional external Flash memory, a hardware Secure Element and a single integrated 2.4GHz structural antenna. Aimed especially at power-sensitive devices needing Wi-Fi®, the ARTIK05X Module provides excellent performance in a variety of environments, with a feature set tailored specifically for IoT end nodes.

• ARTIK053 : The ARTIK053 is a SOC for Wi-Fi™ IoT solutions. The ARTIK053 has a Wi-Fi subsystem, security subsystem, and application subsystem.

• ARTIK053S : The ARTIK053S is a Secure Model of ARTIK053.

• ARTIK055S : The ARTIK055S is the same Secure Model as ARTIK053S and supports I2S. PCB size is reduced compared to ARTIK053, and the power specification has been changed to 3.3V.

Board Spec

CPU

The ARTIK 05X Module CPU has an ARM® Cortex® R4. It has the following features:

• 32KB of Instruction Cache (I-Cache)
• 32KB of Data Cache (D-Cache)
• 320 MHz execution clock
• R4 core tuned for embedded and real-time applications

Memory

The ARTIK 05X Module on-module memory has the following features:

• CPU and general purpose RAM
  • 1280KB CPU RAM
  • 128KB global Inter-Process Communication (IPC) RAM
• 8MB flash

Real Time Clock

The ARTIK 05X Module has a Real Time Clock (RTC) for tracking date/time. The RTC has the following features:

• Binary-Coded Decimal (BCD) coded seconds, minutes, hour, day of the week, day, month, and year
• Leap year detection and compensation
• Millisecond tick time interrupt for Real-Time Operating System (RTOS) kernel time tick

PUF Unit

The ARTIK 05X Module has a Physically Unclonable Function (PUF) unit. The PUF unit has the following features:

• Generates unique key values, locked to an individual ARTIK 05X Module
• The algorithm construction is unique to each module
• Allows individual ARTIK 05X Modules to be “fingerprint-identified”

Security Subsystem

The ARTIK 05X Module has an independent security subsystem to ensure secure end-to-end operation in any IoT environment. The security subsystem includes the following features:

• Protected Execution Environment
• Secure IPC Mailbox for inter-subsystem communication
  • Encapsulated key support
• Backup encryption key - 256 bits
• Security subsystem root private key - 521 bits
• Storage key - 256 bits
• Symmetric key engines
  • Secure AES
  • Secure DES/Triple-DES
• Stream cipher engine
  • ARC4 engine
• Various Hash engines
  • SHA-1, SHA2-256, SHA2-384, SHA2-512, MD5 HMAC
• Asymmetric key engines
  • PKA (Public Key Accelerator) engine
• PRNG (Pseudo Random Number Generator)
• DTRNG (Digital True Random Number Generator)
• Secure key storage

Wi-Fi Subsystem

The ARTIK 05X Module has an 802.11b/g/n Wi-Fi subsystem. The Wi-Fi subsystem has the following features:

• 802.11™ b/g/n support at 2.4GHz
• 20MHz single stream (802.11n)
• WPA/WPA2/WAPI
• Dedicated Wi-Fi Processor subsystem

UART Interface

The ARTIK 05X Module has four 2-pin UART interfaces, each with the following features:

• Can be operated in DMA or interrupt-based mode
• Support for 5, 6, 7 or 8-bit serial data transmit and receive
• Programmable baud rate
• One or two stop bit insertion

GPIO Interface

The ARTIK 05X Module has flexible General Purpose Input Output (GPIO) interfaces:

• 27 configurable GPIO ports
• Independently configurable for either input or output
• Configurable internal pull-up or pull-down resistors

I2C Interface

The ARTIK 05X Module has two high speed multi-master I2C interfaces available, with speeds up to 3.4Mbps.

PWM Interface

The ARTIK 05X Module has five PWM timers available, each with the following features:

• 32 bits of resolution for each PWM signal
• Two 8-bit pre-scalers (first level of division) and 5 clock-dividers/multiplexers for second level division
• Continuous run or one-shot pulse mode
• Dead zone generator to avoid simultaneous change of multiple PWM signals
• Interrupt generation

SPI Interface

The ARTIK 05X Module has two SPI interfaces, each with the following features:

• Full duplex communication
• 8, 16 or 32-bit shift registers and bus interface
• Motorola SPI protocol and National Semiconductor Microwire protocol
• Master and slave mode operation
• Two independent 32-bit wide transmit/receive FIFOs
• Transmit and receive speeds up to 50MHz

ADC Interface

The ARTIK 05X Module has four channels of analog-to-digital converter. The A/D interface has the following features:

• 12-bit resolution
• ADC conversion clock at 1.08 MSPS (Sampling per Second) using a main 6.5 MHz clock
• Support sample averaging over 1, 2, 4, 8, 16, 32, 64 samples
• Differential non-linearity error ±2 LSB
• Integral non-linearity error ±6 LSB
• Top offset error ±10 LSB
• Bottom offset error ±10 LSB
• Voltage range up to 1.8V The figure below depicts the dynamic behavior between input voltage on the ADC and resulting LSB value in the ADC register.

I2S Interface

The ARTIK 05X Module has one I2S interface, Following are the features of I2S bus interface:

• 1-channel I2S for audio codec interface with DMA-based operation
• Serial, 8-/16-/20-/24-bit per channel data transfers
• Supports I2S, MSB-justified, and LSB-justified data formats
• Supports various bit clock frequency and codec clock frequency:
  • 16, 24, 32, 48, 64 fs of bit clock frequency
  • 256, 384, 512, 768 fs of codec clock frequency

Directory Structure about Source Code

    TizenRT
    ├── apps      : Application Directory
    ├── build     : Build Environment & Output
    ├── external  : External Application
    ├── framework : External APIs
    ├── lib       : Library (libc, libxx)
    ├── os        : Main Kernel & BSP(Build Support Package)
    └── tools     : Useful Tools

Memory Map (Flash Partition)

8MB is allocated to the SPI Flash area. 1280 KB is prepared for operation in SRAM. If you want to know the physical memory address, see here.

BL1, BL2, OS Booting Sequence

When a system resets or wakes up from low-power modes, the program executes at the address 0x0000_0000. By default, the internal ROM (IROM) area is mapped to this address. IROM is a small and simple code to initiate the SoC. IROM is implemented on an internal ROM of the SoC. IROM loads the first bootloader. Following are the features of the first and second bootloaders:

• First Bootloader (BL1): It is chip-specific and is stored in an external memory device.
• Second Bootloader (BL2): It is platform-specific and is stored in an external memory device. BL2 is not provided with this package. You must generate the BL2 source code, compile the code, and then store the code in the external memory device.

1. The IROM is placed in an internal 64 KB ROM. It initializes the basic system functions such as clock and stack.
2. The IROM loads the BL1 image from a specific booting device to the internal SRAM. Operating Mode (OM) pins select the booting device. IROM verifies BL1 image based on the secure boot key values.
3. The BL1 and BL2 have service functions for OS or F/W image and prepare to run them. IROM function verifies these images, based on the secure boot key values.
4. After OS or F/W loaded, the program counter on the BL2 progresses to OS or F/W.

Source Build

cd os/tools
sh configure.sh artik053/nettest
cd ..
make

How to program a binary

This makes complete set of binaries programmed.

cd os
make download ALL

menuconfig

cd os
make menuconfig