Last active
August 23, 2022 02:23
-
-
Save KaoRz/bb882b149be63b227fe4eb7a749303da to your computer and use it in GitHub Desktop.
IDA - AVR configuration for ATtiny85
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| .ATtiny85 | |
| ; IDA avr configuration for ATtiny85 (Author: @KaoRz) | |
| ; Documentation: https://www.microchip.com/en-us/product/ATTINY85 | |
| SUBARCH=25 | |
| RAM=512 ; SRAM: 512 bytes | |
| ROM=8192 ; Flash: 8 KB | |
| EEPROM=512 ; EEPROM: 512 bytes | |
| ; MEMORY MAP | |
| area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers | |
| area DATA FSR_ 0x0020:0x0060 I/O registers | |
| area DATA I_SRAM 0x0060:0x0260 Internal SRAM | |
| ; INTERRUPT AND RESET VECTOR ASSIGNMENTS | |
| entry __RESET 0x0000 External Pin, Power-on Reset,Brown-out Reset, Watchdog Reset | |
| entry INT0_ 0x0001 External Interrupt Request 0 | |
| entry PCINT0_ 0x0002 Pin Change Interrupt Request 0 | |
| entry TIMER1_COMPA 0x0003 Timer/Counter1 Compare Match A | |
| entry TIMER1_OVF 0x0004 Timer/Counter1 Overflow | |
| entry TIMER0_OVF 0x0005 Timer/Counter0 Overflow | |
| entry EE_READY 0x0006 EEPROM Ready | |
| entry ANALOG_COMP 0x0007 Analog Comparator | |
| entry ADC 0x0008 ADC Conversion Complete | |
| entry TIMER1_COMPB 0x0009 Timer/Counter1 Compare Match B | |
| entry TIMER0_COMPA 0x000a Timer/Counter0 Compare Match A | |
| entry TIMER0_COMPB 0x000b Timer/Counter0 Compare Match B | |
| entry WDT 0x000c Watchdog Time-out | |
| entry USI_START 0x000d USI START | |
| entry USI_OVF 0x000e USI Overflow | |
| ; INPUT/OUTPUT PORTS | |
| RESERVED0000 0x0000 RESERVED | |
| RESERVED0001 0x0001 RESERVED | |
| RESERVED0002 0x0002 RESERVED | |
| ADCSRB 0x0003 ADC Control and Status Register B | |
| ADCSRB.BIN 7 Bipolar Input Mode | |
| ADCSRB.ACME 6 Analog Comparator Multiplexer Enable | |
| ADCSRB.IPR 5 Input Polarity Reversal | |
| ADCSRB.ADTS2 2 ADC Auto Trigger Source Bit 2 | |
| ADCSRB.ADTS1 1 ADC Auto Trigger Source Bit 1 | |
| ADCSRB.ADTS0 0 ADC Auto Trigger Source Bit 0 | |
| ADCL 0x0004 ADC Data Register Low Byte | |
| ADCH 0x0005 ADC Data Register High Byte | |
| ADCSRA 0x0006 ADC Control and Status Register A | |
| ADCSRA.ADEN 7 ADC Enable | |
| ADCSRA.ADSC 6 ADC Start Conversion | |
| ADCSRA.ADATE 5 ADC Auto Trigger Enable | |
| ADCSRA.ADIF 4 ADC Interrupt Flag | |
| ADCSRA.ADIE 3 ADC Interrupt Enable | |
| ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2 | |
| ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1 | |
| ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0 | |
| ADMUX 0x0007 ADC Multiplexer Selection Register | |
| ADMUX.REFS1 7 Voltage Reference Selection Bit 1 | |
| ADMUX.REFS0 6 Voltage Reference Selection Bit 0 | |
| ADMUX.ADLAR 5 ADC Left Adjust Result | |
| ADMUX.REFS2 4 Voltage Reference Selection Bit 2 | |
| ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3 | |
| ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2 | |
| ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1 | |
| ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0 | |
| ACSR 0x0008 Analog Comparator Control and Status Register | |
| ACSR.ACD 7 Analog Comparator Disable | |
| ACSR.ACBG 6 Analog Comparator Bandgap Select | |
| ACSR.ACO 5 Analog Comparator Output | |
| ACSR.ACI 4 Analog Comparator Interrupt Flag | |
| ACSR.ACIE 3 Analog Comparator Interrupt Enable | |
| ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select Bit 1 | |
| ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select Bit 0 | |
| RESERVED0009 0x0009 RESERVED | |
| RESERVED000A 0x000a RESERVED | |
| RESERVED000B 0x000b RESERVED | |
| RESERVED000C 0x000c RESERVED | |
| USICR 0x000d USI Control Register | |
| USICR.USISIE 7 Start Condition Interrupt Enable | |
| USICR.USIOIE 6 Counter Overflow Interrupt Enable | |
| USICR.USIWM1 5 Wire Mode Bit 1 | |
| USICR.USIWM0 4 Wire Mode Bit 0 | |
| USICR.USICS1 3 Clock Source Select Bit 1 | |
| USICR.USICS0 2 Clock Source Select Bit 0 | |
| USICR.USICLK 1 Clock Strobe | |
| USICR.USITC 0 Toggle Clock Port Pin | |
| USISR 0x000e USI Status Register | |
| USISR.USISIF 7 Start Condition Interrupt Flag | |
| USISR.USIOIF 6 Counter Overflow Interrupt Flag | |
| USISR.USIPF 5 Stop Condition Flag | |
| USISR.USIDC 4 Data Output Collision | |
| USISR.USICNT3 3 Counter Value Bit 3 | |
| USISR.USICNT2 2 Counter Value Bit 2 | |
| USISR.USICNT1 1 Counter Value Bit 1 | |
| USISR.USICNT0 0 Counter Value Bit 0 | |
| USIDR 0x000f USI Data Register | |
| USIBR 0x0010 USI Buffer Register | |
| GPIOR0 0x0011 General Purpose I/O Register 0 | |
| GPIOR1 0x0012 General Purpose I/O Register 1 | |
| GPIOR2 0x0013 General Purpose I/O Register 2 | |
| DIDR0 0x0014 Digital Input Disable Register 0 | |
| DIDR0.ADC0D 5 ADC Digital Input Disable Bit 0 | |
| DIDR0.ADC2D 4 ADC Digital Input Disable Bit 2 | |
| DIDR0.ADC3D 3 ADC Digital Input Disable Bit 3 | |
| DIDR0.ADC1D 2 ADC Digital Input Disable Bit 1 | |
| DIDR0.AIN1D 1 AIN Digital Input Disable Bit 1 | |
| DIDR0.AIN0D 0 AIN Digital Input Disable Bit 0 | |
| PCMSK 0x0015 Pin Change Mask Register | |
| PCMSK.PCINT5 5 Pin Change Enable Mask Bit 5 | |
| PCMSK.PCINT4 4 Pin Change Enable Mask Bit 4 | |
| PCMSK.PCINT3 3 Pin Change Enable Mask Bit 3 | |
| PCMSK.PCINT2 2 Pin Change Enable Mask Bit 2 | |
| PCMSK.PCINT1 1 Pin Change Enable Mask Bit 1 | |
| PCMSK.PCINT0 0 Pin Change Enable Mask Bit 0 | |
| PINB 0x0016 Port B Input Pins Address | |
| PINB.PINB5 5 | |
| PINB.PINB4 4 | |
| PINB.PINB3 3 | |
| PINB.PINB2 2 | |
| PINB.PINB1 1 | |
| PINB.PINB0 0 | |
| DDRB 0x0017 Port B Data Direction Register | |
| DDRB.DDB5 5 | |
| DDRB.DDB4 4 | |
| DDRB.DDB3 3 | |
| DDRB.DDB2 2 | |
| DDRB.DDB1 1 | |
| DDRB.DDB0 0 | |
| PORTB 0x0018 Port B Data Register | |
| PORTB.PORTB5 5 | |
| PORTB.PORTB4 4 | |
| PORTB.PORTB3 3 | |
| PORTB.PORTB2 2 | |
| PORTB.PORTB1 1 | |
| PORTB.PORTB0 0 | |
| RESERVED0019 0x0019 RESERVED | |
| RESERVED001A 0x001a RESERVED | |
| RESERVED001B 0x001b RESERVED | |
| EECR 0x001c EEPROM Control Register | |
| EECR.EEPM1 5 EEPROM Programming Mode Bit 1 | |
| EECR.EEPM0 4 EEPROM Programming Mode Bit 0 | |
| EECR.EERIE 3 EEPROM Ready Interrupt Enable | |
| EECR.EEMPE 2 EEPROM Master Program Enable | |
| EECR.EEPE 1 EEPROM Program Enable | |
| EECR.EERE 0 EEPROM Read Enable | |
| EEDR 0x001d EEPROM Data Register | |
| EEARL 0x001e EEPROM Address Register | |
| EEARH 0x001f EEPROM Address Register MSB | |
| EEARH.EEAR8 0 EEPROM Address Bit 8 | |
| PRR 0x0020 Power Reduction Register | |
| PRR.PRTIM1 3 Power Reduction Timer/Counter1 | |
| PRR.PRTIM0 2 Power Reduction Timer/Counter0 | |
| PRR.PRUSI 1 Power Reduction USI | |
| PRR.PRADC 0 Power Reduction ADC | |
| WDTCR 0x0021 Watchdog Timer Control Register | |
| WDTCR.WDIF 7 Watchdog Timeout Interrupt Flag | |
| WDTCR.WDIE 6 Watchdog Timeout Interrupt Enable | |
| WDTCR.WDP3 5 Watchdog Timer Prescaler Bit 3 | |
| WDTCR.WDCE 4 Watchdog Change Enable | |
| WDTCR.WDE 3 Watchdog Enable | |
| WDTCR.WDP2 2 Watchdog Timer Prescaler Bit 2 | |
| WDTCR.WDP1 1 Watchdog Timer Prescaler Bit 1 | |
| WDTCR.WDP0 0 Watchdog Timer Prescaler Bit 0 | |
| DWDR 0x0022 debugWire Data Register | |
| DTPS1 0x0023 Dead Time Prescaler Register 1 | |
| DTPS1.DTPS11 1 Dead Time Prescaler Bit 1 | |
| DTPS1.DTPS10 0 Dead Time Prescaler Bit 0 | |
| DT1B 0x0024 Timer/Counter1 Dead Time B | |
| DT1B.DT1BH3 7 Dead Time Value for OC1B Output Bit 3 | |
| DT1B.DT1BH2 6 Dead Time Value for OC1B Output Bit 2 | |
| DT1B.DT1BH1 5 Dead Time Value for OC1B Output Bit 1 | |
| DT1B.DT1BH0 4 Dead Time Value for OC1B Output Bit 0 | |
| DT1B.DT1BL3 3 Dead Time Value for ~OC1B Output Bit 3 | |
| DT1B.DT1BL2 2 Dead Time Value for ~OC1B Output Bit 2 | |
| DT1B.DT1BL1 1 Dead Time Value for ~OC1B Output Bit 1 | |
| DT1B.DT1BL0 0 Dead Time Value for ~OC1B Output Bit 0 | |
| DT1A 0x0025 Timer/Counter1 Dead Time A | |
| DT1A.DT1AH3 7 Dead Time Value for OC1A Output Bit 3 | |
| DT1A.DT1AH2 6 Dead Time Value for OC1A Output Bit 2 | |
| DT1A.DT1AH1 5 Dead Time Value for OC1A Output Bit 1 | |
| DT1A.DT1AH0 4 Dead Time Value for OC1A Output Bit 0 | |
| DT1A.DT1AL3 3 Dead Time Value for ~OC1A Output Bit 3 | |
| DT1A.DT1AL2 2 Dead Time Value for ~OC1A Output Bit 2 | |
| DT1A.DT1AL1 1 Dead Time Value for ~OC1A Output Bit 1 | |
| DT1A.DT1AL0 0 Dead Time Value for ~OC1A Output Bit 0 | |
| CLKPR 0x0026 Clock Prescale Register | |
| CLKPR.CLKPCE 7 Clock Prescaler Change Enable | |
| CLKPR.CLKPS3 3 Clock Prescaler Select Bit 3 | |
| CLKPR.CLKPS2 2 Clock Prescaler Select Bit 2 | |
| CLKPR.CLKPS1 1 Clock Prescaler Select Bit 1 | |
| CLKPR.CLKPS0 0 Clock Prescaler Select Bit 0 | |
| PLLCSR 0x0027 PLL Control and Status Register | |
| PLLCSR.LSM 7 Low Speed Mode | |
| PLLCSR.PCKE 2 PCK Enable | |
| PLLCSR.PLLE 1 PLL Enable | |
| PLLCSR.PLOCK 0 PLL Lock Detector | |
| OCR0B 0x0028 Timer/Counter0 – Output Compare Register B | |
| OCR0A 0x0029 Timer/Counter0 – Output Compare Register A | |
| TCCR0A 0x002a Timer/Counter Control Register A | |
| TCCR0A.COM0A1 7 Compare Match Output A Mode Bit 1 | |
| TCCR0A.COM0A0 6 Compare Match Output A Mode Bit 0 | |
| TCCR0A.COM0B1 5 Compare Match Output B Mode Bit 1 | |
| TCCR0A.COM0B0 4 Compare Match Output B Mode Bit 0 | |
| TCCR0A.WGM01 1 Waveform Generation Mode Bit 1 | |
| TCCR0A.WGM00 0 Waveform Generation Mode Bit 0 | |
| OCR1B 0x002b Timer/Counter1 Output Compare Register B | |
| GTCCR 0x002c General Timer/Counter Control Register | |
| GTCCR.TSM 7 Timer/Counter Synchronization Mode | |
| GTCCR.PWM1B 6 Pulse Width Modulator B Enable | |
| GTCCR.COM1B1 5 Comparator B Output Mode Bit 1 | |
| GTCCR.COM1B0 4 Comparator B Output Mode Bit 0 | |
| GTCCR.FOC1B 3 Force Output Compare Match 1B | |
| GTCCR.FOC1A 2 Force Output Compare Match 1A | |
| GTCCR.PSR1 1 Prescaler Reset Timer/Counter1 | |
| GTCCR.PSR0 0 Prescaler Reset Timer/Counter0 | |
| OCR1C 0x002d Timer/Counter1 Output Compare Register C | |
| OCR1A 0x002e Timer/Counter1 Output Compare Register A | |
| TCNT1 0x002f Timer/Counter1 | |
| TCCR1 0x0030 Timer/Counter1 Control Register | |
| TCCR1.CTC1 7 Clear Timer/Counter on Compare Match | |
| TCCR1.PWM1A 6 Pulse Width Modulator A Enable | |
| TCCR1.COM1A1 5 Comparator A Output Mode Bit 1 | |
| TCCR1.COM1A0 4 Comparator A Output Mode Bit 0 | |
| TCCR1.CS13 3 Clock Select Bit 3 | |
| TCCR1.CS12 2 Clock Select Bit 2 | |
| TCCR1.CS11 1 Clock Select Bit 1 | |
| TCCR1.CS10 0 Clock Select Bit 0 | |
| OSCCAL 0x0031 Oscillator Calibration Register | |
| TCNT0 0x0032 Timer/Counter0 | |
| TCCR0B 0x0033 Timer/Counter Control Register B | |
| TCCR0B.FOC0A 7 Force Output Compare A | |
| TCCR0B.FOC0B 6 Force Output Compare B | |
| TCCR0B.WGM02 3 Waveform Generation Mode | |
| TCCR0B.CS02 2 Clock Select Bit 2 | |
| TCCR0B.CS01 1 Clock Select Bit 1 | |
| TCCR0B.CS00 0 Clock Select Bit 0 | |
| MCUSR 0x0034 MCU Status Register | |
| MCUSR.WDRF 3 Watchdog Reset Flag | |
| MCUSR.BORF 2 Brown-out Reset Flag | |
| MCUSR.EXTRF 1 External Reset Flag | |
| MCUSR.PORF 0 Power-on Reset Flag | |
| MCUCR 0x0035 MCU Control Register | |
| MCUCR.BODS 7 BOD Sleep | |
| MCUCR.PUD 6 Pull-up Disable | |
| MCUCR.SE 5 Sleep Enable | |
| MCUCR.SM1 4 Sleep Mode Select Bit 1 | |
| MCUCR.SM0 3 Sleep Mode Select Bit 0 | |
| MCUCR.BODSE 2 BOD Sleep Enable | |
| MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1 | |
| MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0 | |
| RESERVED0036 0x0036 RESERVED | |
| SPMCSR 0x0037 Store Program Memory Control and Status Register | |
| SPMCSR.RSIG 5 Read Device Signature Imprint Table | |
| SPMCSR.CTPB 4 Clear Temporary Page Buffer | |
| SPMCSR.RFLB 3 Read Fuse and Lock Bits | |
| SPMCSR.PGWRT 2 Page Write | |
| SPMCSR.PGERS 1 Page Erase | |
| SPMCSR.SPMEN 0 Store Program Memory Enable | |
| TIFR 0x0038 Timer/Counter Interrupt Flag Register | |
| TIFR.OCF1A 6 Output Compare Flag 1A | |
| TIFR.OCF1B 5 Output Compare Flag 1B | |
| TIFR.OCF0A 4 Output Compare Flag 0A | |
| TIFR.OCF0B 3 Output Compare Flag 0B | |
| TIFR.TOV1 2 Timer/Counter1 Overflow Flag | |
| TIFR.TOV0 1 Timer/Counter0 Overflow Flag | |
| TIMSK 0x0039 Timer/Counter Interrupt Mask Register | |
| TIMSK.OCIE1A 6 Timer/Counter1 Output Compare Match A Interrupt Enable | |
| TIMSK.OCIE1B 5 Timer/Counter1 Output Compare Match B Interrupt Enable | |
| TIMSK.OCIE0A 4 Timer/Counter0 Output Compare Match A Interrupt Enable | |
| TIMSK.OCIE0B 3 Timer/Counter0 Output Compare Match B Interrupt Enable | |
| TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable | |
| TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable | |
| GIFR 0x003a General Interrupt Flag Register | |
| GIFR.INTF0 6 External Interrupt Flag 0 | |
| GIFR.PCIF 5 Pin Change Interrupt Flag | |
| GIMSK 0x003b General Interrupt Mask Register | |
| GIMSK.INT0 6 External Interrupt Request 0 Enable | |
| GIMSK.PCIE 5 Pin Change Interrupt Enable | |
| RESERVED003C 0x003c RESERVED | |
| SPL 0x003d Stack Pointer LSB | |
| SPL.SP7 7 | |
| SPL.SP6 6 | |
| SPL.SP5 5 | |
| SPL.SP4 4 | |
| SPL.SP3 3 | |
| SPL.SP2 2 | |
| SPL.SP1 1 | |
| SPL.SP0 0 | |
| SPH 0x003e Stack Pointer MSB | |
| SPH.SP9 9 | |
| SPH.SP8 8 | |
| SREG 0x003f Status Register | |
| SREG.I 7 Global Interrupt Enable | |
| SREG.T 6 Bit Copy Storage | |
| SREG.H 5 Half Carry Flag | |
| SREG.S 4 Sign Bit | |
| SREG.V 3 Twos Complement Overflow Flag | |
| SREG.N 2 Negative Flag | |
| SREG.Z 1 Zero Flag | |
| SREG.C 0 Carry Flag |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment