Reverse Engineering Plan

re_plan.md

• #1. Hardware

  • 1.1 Von Neumann Architecture
  • 1.2 Harvard Architecture
  • 1.3 Virtual Memory
  • 1.4 CPU
  • 1.5 Power consumption
  • 1.6 HUD
  • 1.7 Data exchange interfaces
    • 1.7.1 USB 2.0
    • 1.7.2 USB 3.0
    • 1.7.3 USB Type-C
    • 1.7.4 SATA
    • 1.7.5 Optic Fiber
    • 1.7.6 Thunderbolt
    • 1.7.7 Thunderbolt 2

• #2 Operation System

  • 2.1 Kernel
  • 2.2 Program execution
  • 2.3 Interrupts
  • 2.4 Modes
  • 2.5 Memory management
  • 2.6 Virtual memory
  • 2.7 Multitasking
  • 2.8 Device drivers
  • 2.9 File System
  • 2.10 Networking

• #3 Networking

  • 3.1 OSI model

• #4. Assembler Microarchitecture

  • 4.1 Instruction cycle
    • 4.1.1 Program counter (PC)
    • 4.1.2 Memory address register (MAR)
    • 4.1.3 Memory data register (MDR)
    • 4.1.4 Instruction register (IR)
    • 4.1.5 Control unit (CU)
    • 4.1.6 Arithmetic logic unit (ALU)
    • 4.1.7 Floating-point unit (FPU)
  • 4.2 Instruction Set
    • 4.2.1 ASIP
    • 4.2.2 CISC
    • 4.2.3 RISC
    • 4.2.4 EDGE (TRIPS)
    • 4.2.5 VLIW (EPIC)
    • 4.2.6 MISC
    • 4.2.7 OISC
    • 4.2.8 NISC
    • 4.2.9 ZISC
  • 4.3 Instruction Set Architecture
    • 4.2.1 AMD
    • 4.2.2 ARM
    • 4.2.3 IBM
    • 4.2.4 Intel
    • 4.2.5 MIPS
  • 4.3 Caching
  • 4.4 Branch prediction
  • 4.5 Instruction pipelining
  • 4.6 Superscalar
  • 4.7 Out-of-order execution
  • 4.8 Register renaming
  • 4.9 Multiprocessing and multithreading