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| enable prepare protect duty | |
| clock count count count rate accuracy phase cycle | |
| --------------------------------------------------------------------------------------------- | |
| xtal 12 12 0 24000000 0 0 50000 | |
| cts_oscin 0 0 0 24000000 0 0 50000 | |
| g12a_ao_cec_pre 0 0 0 24000000 0 0 50000 | |
| g12a_ao_cec_div 0 0 0 32742 0 0 50000 | |
| g12a_ao_cec_sel 0 0 0 32742 0 0 50000 | |
| g12a_ao_cec 0 0 0 32742 0 0 50000 | |
| g12a_ao_32k_by_oscin_pre 0 0 0 24000000 0 0 50000 | |
| g12a_ao_32k_by_oscin_sel 0 0 0 24000000 0 0 50000 | |
| g12a_ao_32k_by_oscin 0 0 0 24000000 0 0 50000 | |
| g12a_ao_cts_rtc_oscin 0 0 0 24000000 0 0 50000 | |
| g12a_ao_32k_by_oscin_div 0 0 0 32742 0 0 50000 | |
| g12a_ao_saradc_mux 0 0 0 24000000 0 0 50000 | |
| g12a_ao_saradc_div 0 0 0 149069 0 0 50000 | |
| g12a_ao_saradc_gate 0 0 0 149069 0 0 50000 | |
| spicc1_sclk_sel 0 0 0 24000000 0 0 50000 | |
| spicc1_sclk_div 0 0 0 24000000 0 0 50000 | |
| spicc1_sclk 0 0 0 24000000 0 0 50000 | |
| spicc0_sclk_sel 0 0 0 24000000 0 0 50000 | |
| spicc0_sclk_div 0 0 0 24000000 0 0 50000 | |
| spicc0_sclk 0 0 0 24000000 0 0 50000 | |
| cpub_clk_dyn0_sel 0 0 0 24000000 0 0 50000 | |
| cpub_clk_dyn0 0 0 0 24000000 0 0 50000 | |
| cpub_clk_dyn0_div 0 0 0 24000000 0 0 50000 | |
| sys1_pll_dco 1 1 0 3792000000 0 0 50000 | |
| sys1_pll 0 0 0 1896000000 0 0 50000 | |
| cpu_clk 0 0 0 1896000000 0 0 50000 | |
| cpu_clk_trace_div 0 0 0 59250000 0 0 50000 | |
| cpu_clk_trace 0 0 0 59250000 0 0 50000 | |
| sys1_pll_div16_en 0 0 0 1896000000 0 0 50000 | |
| sys1_pll_div16 0 0 0 118500000 0 0 50000 | |
| ts_div 1 1 0 960000 0 0 50000 | |
| ts 2 2 0 960000 0 0 50000 | |
| pcie_pll_dco 1 1 0 2400000000 0 0 50000 | |
| pcie_pll_dco_div2 1 1 0 1200000000 0 0 50000 | |
| pcie_pll_od 1 1 0 200000000 0 0 50000 | |
| pcie_pll_pll 1 1 0 100000000 0 0 50000 | |
| cpu_clk_dyn0_sel 0 0 0 24000000 0 0 50000 | |
| cpu_clk_dyn0 0 0 0 24000000 0 0 50000 | |
| cpu_clk_dyn 0 0 0 24000000 0 0 50000 | |
| cpu_clk_dyn0_div 0 0 0 24000000 0 0 50000 | |
| mali_1_sel 0 0 0 24000000 0 0 50000 | |
| mali_1_div 0 0 0 24000000 0 0 50000 | |
| mali_1 0 0 0 24000000 0 0 50000 | |
| hdmi_sel 1 1 0 24000000 0 0 50000 | |
| hdmi_div 1 1 0 24000000 0 0 50000 | |
| hdmi 2 2 0 24000000 0 0 50000 | |
| hdmi_pll_dco 0 0 0 5928000000 0 0 50000 | |
| hdmi_pll_od 0 0 0 2964000000 0 0 50000 | |
| hdmi_pll_od2 0 0 0 2964000000 0 0 50000 | |
| hdmi_pll 0 0 0 2964000000 0 0 50000 | |
| vid_pll_div 0 0 0 592800000 0 0 50000 | |
| vid_pll_sel 0 0 0 592800000 0 0 50000 | |
| vid_pll 0 0 0 592800000 0 0 50000 | |
| vclk2_sel 0 0 0 592800000 0 0 50000 | |
| vclk2_input 0 0 0 592800000 0 0 50000 | |
| vclk2_div 0 0 0 10778182 0 0 50000 | |
| vclk2 0 0 0 10778182 0 0 50000 | |
| vclk2_div1 0 0 0 10778182 0 0 50000 | |
| cts_vdac_sel 0 0 0 10778182 0 0 50000 | |
| cts_vdac 0 0 0 10778182 0 0 50000 | |
| cts_enci_sel 0 0 0 10778182 0 0 50000 | |
| cts_enci 0 0 0 10778182 0 0 50000 | |
| vclk2_div12_en 0 0 0 10778182 0 0 50000 | |
| vclk2_div12 0 0 0 898181 0 0 50000 | |
| vclk2_div6_en 0 0 0 10778182 0 0 50000 | |
| vclk2_div6 0 0 0 1796363 0 0 50000 | |
| vclk2_div4_en 0 0 0 10778182 0 0 50000 | |
| vclk2_div4 0 0 0 2694545 0 0 50000 | |
| vclk2_div2_en 0 0 0 10778182 0 0 50000 | |
| vclk2_div2 0 0 0 5389091 0 0 50000 | |
| vclk_sel 0 0 0 592800000 0 0 50000 | |
| vclk_input 0 0 0 592800000 0 0 50000 | |
| vclk_div 0 0 0 592800000 0 0 50000 | |
| vclk 0 0 0 592800000 0 0 50000 | |
| vclk_div1 0 0 0 592800000 0 0 50000 | |
| hdmi_tx_sel 0 0 0 592800000 0 0 50000 | |
| hdmi_tx 0 0 0 592800000 0 0 50000 | |
| cts_encp_sel 0 0 0 592800000 0 0 50000 | |
| cts_encp 0 0 0 592800000 0 0 50000 | |
| vclk_div12_en 0 0 0 592800000 0 0 50000 | |
| vclk_div12 0 0 0 49400000 0 0 50000 | |
| vclk_div6_en 0 0 0 592800000 0 0 50000 | |
| vclk_div6 0 0 0 98800000 0 0 50000 | |
| vclk_div4_en 0 0 0 592800000 0 0 50000 | |
| vclk_div4 0 0 0 148200000 0 0 50000 | |
| vclk_div2_en 0 0 0 592800000 0 0 50000 | |
| vclk_div2 0 0 0 296400000 0 0 50000 | |
| hifi_pll_dco 0 0 0 0 0 0 50000 | |
| hifi_pll 0 0 0 0 0 0 50000 | |
| gp0_pll_dco 0 0 0 0 0 0 50000 | |
| gp0_pll 0 0 0 0 0 0 50000 | |
| sys_pll_dco 1 1 0 3408000000 0 0 50000 | |
| sys_pll 0 0 0 1704000000 0 0 50000 | |
| cpub_clk 0 0 0 1704000000 0 0 50000 | |
| cpub_clk_div8 0 0 0 213000000 0 0 50000 | |
| cpub_clk_div7 0 0 0 243428571 0 0 50000 | |
| cpub_clk_div6 0 0 0 284000000 0 0 50000 | |
| cpub_clk_trace_sel 0 0 0 284000000 0 0 50000 | |
| cpub_clk_trace 0 0 0 284000000 0 0 50000 | |
| cpub_clk_div5 0 0 0 340800000 0 0 50000 | |
| cpub_clk_apb_sel 0 0 0 340800000 0 0 50000 | |
| cpub_clk_apb 0 0 0 340800000 0 0 50000 | |
| cpub_clk_div4 0 0 0 426000000 0 0 50000 | |
| cpub_clk_div3 0 0 0 568000000 0 0 50000 | |
| cpub_clk_atb_sel 0 0 0 568000000 0 0 50000 | |
| cpub_clk_atb 0 0 0 568000000 0 0 50000 | |
| cpub_clk_div2 0 0 0 852000000 0 0 50000 | |
| cpub_clk_axi_sel 0 0 0 852000000 0 0 50000 | |
| cpub_clk_axi 0 0 0 852000000 0 0 50000 | |
| cpub_clk_div16_en 0 0 0 1704000000 0 0 50000 | |
| cpub_clk_div16 0 0 0 106500000 0 0 50000 | |
| sys_pll_div16_en 0 0 0 1704000000 0 0 50000 | |
| sys_pll_div16 0 0 0 106500000 0 0 50000 | |
| fixed_pll_dco 2 2 0 3999999939 0 0 50000 | |
| mpll_50m_div 0 0 0 49999999 0 0 50000 | |
| mpll_50m 0 0 0 49999999 0 0 50000 | |
| ff64c000.mdio-multiplexer#mux 0 0 0 49999999 0 0 50000 | |
| ff64c000.mdio-multiplexer#pll 0 0 0 499999990 0 0 50000 | |
| fixed_pll 3 3 0 1999999970 0 0 50000 | |
| fclk_div7_div 0 0 0 285714281 0 0 50000 | |
| fclk_div7 0 0 0 285714281 0 0 50000 | |
| fclk_div5_div 0 0 0 399999994 0 0 50000 | |
| fclk_div5 0 0 0 399999994 0 0 50000 | |
| fclk_div4_div 1 1 0 499999992 0 0 50000 | |
| fclk_div4 1 1 0 499999992 0 0 50000 | |
| vapb_1_sel 0 0 0 499999992 0 0 50000 | |
| vapb_1_div 0 0 0 499999992 0 0 50000 | |
| vapb_1 0 0 0 499999992 0 0 50000 | |
| vapb_0_sel 1 1 0 499999992 0 0 50000 | |
| vapb_0_div 1 1 0 249999996 0 0 50000 | |
| vapb_0 1 1 0 249999996 0 0 50000 | |
| vapb_sel 1 1 0 249999996 0 0 50000 | |
| vapb 1 1 0 249999996 0 0 50000 | |
| fclk_div3_div 1 1 0 666666656 0 0 50000 | |
| fclk_div3 3 3 0 666666656 0 0 50000 | |
| cpu_clk_dyn1_sel 0 0 0 666666656 0 0 50000 | |
| cpu_clk_dyn1 0 0 0 666666656 0 0 50000 | |
| cpu_clk_dyn1_div 0 0 0 666666656 0 0 50000 | |
| vpu_1_sel 0 0 0 666666656 0 0 50000 | |
| vpu_1_div 0 0 0 666666656 0 0 50000 | |
| vpu_1 0 0 0 666666656 0 0 50000 | |
| vpu_0_sel 1 1 0 666666656 0 0 50000 | |
| vpu_0_div 1 1 0 666666656 0 0 50000 | |
| vpu_0 1 1 0 666666656 0 0 50000 | |
| vpu 1 1 0 666666656 0 0 50000 | |
| mpeg_clk_sel 1 1 0 666666656 0 0 50000 | |
| mpeg_clk_div 1 1 0 222222219 0 0 50000 | |
| clk81 11 11 0 222222219 0 0 50000 | |
| g12a_ao_clk81 0 0 0 222222219 0 0 50000 | |
| g12a_ao_m4_hclk 0 0 0 222222219 0 0 50000 | |
| g12a_ao_m4_fclk 0 0 0 222222219 0 0 50000 | |
| g12a_ao_rti 0 0 0 222222219 0 0 50000 | |
| g12a_ao_ahb_sram 0 0 0 222222219 0 0 50000 | |
| g12a_ao_m3 0 0 0 222222219 0 0 50000 | |
| g12a_ao_mailbox 0 0 0 222222219 0 0 50000 | |
| g12a_ao_saradc 0 0 0 222222219 0 0 50000 | |
| g12a_ao_ir_out 0 0 0 222222219 0 0 50000 | |
| g12a_ao_uart2 0 0 0 222222219 0 0 50000 | |
| g12a_ao_prod_i2c 0 0 0 222222219 0 0 50000 | |
| g12a_ao_uart 1 1 0 222222219 0 0 50000 | |
| g12a_ao_i2c_s0 0 0 0 222222219 0 0 50000 | |
| g12a_ao_i2c_m0 0 0 0 222222219 0 0 50000 | |
| g12a_ao_ir_in 0 0 0 222222219 0 0 50000 | |
| g12a_ao_ahb 0 0 0 222222219 0 0 50000 | |
| g12a_sec_ahb_apb3 0 0 0 222222219 0 0 50000 | |
| g12a_reset_sec 0 0 0 222222219 0 0 50000 | |
| g12a_rom_boot 0 0 0 222222219 0 0 50000 | |
| g12a_efuse 1 1 0 222222219 0 0 50000 | |
| g12a_dma 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_other1 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_vencl 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_venclmmc 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_encl 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_enct 0 0 0 222222219 0 0 50000 | |
| g12a_rng1 0 0 0 222222219 0 0 50000 | |
| g12a_enc480p 0 0 0 222222219 0 0 50000 | |
| g12a_iec958_gate 0 0 0 222222219 0 0 50000 | |
| g12a_aoclk_gate 0 0 0 222222219 0 0 50000 | |
| g12a_dac_clk 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_encp 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_enci 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_other 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_venct1 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_venct0 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_vencp1 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_vencp0 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_venci1 0 0 0 222222219 0 0 50000 | |
| g12a_vclk2_venci0 0 0 0 222222219 0 0 50000 | |
| g12a_gic 0 0 0 222222219 0 0 50000 | |
| g12a_vpu_intr 1 1 0 222222219 0 0 50000 | |
| g12a_uart2 0 0 0 222222219 0 0 50000 | |
| g12a_mmc_pclk 0 0 0 222222219 0 0 50000 | |
| g12a_usb1_to_ddr 0 0 0 222222219 0 0 50000 | |
| g12a_bt656 0 0 0 222222219 0 0 50000 | |
| g12a_htx_pclk 1 1 0 222222219 0 0 50000 | |
| g12a_htx_hdcp22 0 0 0 222222219 0 0 50000 | |
| g12a_ahb_ctrl_bus 0 0 0 222222219 0 0 50000 | |
| g12a_ahb_data_bus 0 0 0 222222219 0 0 50000 | |
| g12a_ahb_arb0 0 0 0 222222219 0 0 50000 | |
| g12a_pcie_phy 0 0 0 222222219 0 0 50000 | |
| g12a_usb_general 1 1 0 222222219 0 0 50000 | |
| g12a_parser 0 0 0 222222219 0 0 50000 | |
| g12a_pcie_comb 0 0 0 222222219 0 0 50000 | |
| g12a_reset 0 0 0 222222219 0 0 50000 | |
| g12a_g2d 0 0 0 222222219 0 0 50000 | |
| g12a_uart1 0 0 0 222222219 0 0 50000 | |
| g12a_adc 0 0 0 222222219 0 0 50000 | |
| g12a_audio_ififo 0 0 0 222222219 0 0 50000 | |
| g12a_demux 0 0 0 222222219 0 0 50000 | |
| g12a_eth_core 1 1 0 222222219 0 0 50000 | |
| g12a_audio 2 2 0 222222219 0 0 50000 | |
| aud_top 1 1 0 222222219 0 0 50000 | |
| aud_ddr_arb 1 1 0 222222219 0 0 50000 | |
| aud_pdm 0 0 0 222222219 0 0 50000 | |
| aud_tdmin_a 0 0 0 222222219 0 0 50000 | |
| aud_tdmin_b 0 0 0 222222219 0 0 50000 | |
| aud_tdmin_c 0 0 0 222222219 0 0 50000 | |
| aud_tdmin_lb 0 0 0 222222219 0 0 50000 | |
| aud_tdmout_a 0 0 0 222222219 0 0 50000 | |
| aud_tdmout_b 0 0 0 222222219 0 0 50000 | |
| aud_tdmout_c 0 0 0 222222219 0 0 50000 | |
| aud_frddr_a 0 0 0 222222219 0 0 50000 | |
| aud_frddr_b 0 0 0 222222219 0 0 50000 | |
| aud_frddr_c 0 0 0 222222219 0 0 50000 | |
| aud_toddr_a 0 0 0 222222219 0 0 50000 | |
| aud_toddr_b 0 0 0 222222219 0 0 50000 | |
| aud_toddr_c 0 0 0 222222219 0 0 50000 | |
| aud_loopback 0 0 0 222222219 0 0 50000 | |
| aud_spdifin 0 0 0 222222219 0 0 50000 | |
| aud_spdifout 0 0 0 222222219 0 0 50000 | |
| aud_resample 0 0 0 222222219 0 0 50000 | |
| aud_power_detect 0 0 0 222222219 0 0 50000 | |
| aud_spdifout_b 0 0 0 222222219 0 0 50000 | |
| g12a_audio_codec 0 0 0 222222219 0 0 50000 | |
| g12a_emmc_c 1 1 0 222222219 0 0 50000 | |
| g12a_emmc_b 1 1 0 222222219 0 0 50000 | |
| g12a_emmc_a 0 0 0 222222219 0 0 50000 | |
| g12a_assist_misc 0 0 0 222222219 0 0 50000 | |
| g12a_mipi_dsi_phy 0 0 0 222222219 0 0 50000 | |
| g12a_hiu_reg 0 0 0 222222219 0 0 50000 | |
| g12a_spicc_1 0 0 0 222222219 0 0 50000 | |
| g12a_uart0 0 0 0 222222219 0 0 50000 | |
| g12a_rng0 0 0 0 222222219 0 0 50000 | |
| g12a_sd 0 0 0 222222219 0 0 50000 | |
| g12a_sana 0 0 0 222222219 0 0 50000 | |
| g12a_i2c 0 0 0 222222219 0 0 50000 | |
| g12a_spicc_0 0 0 0 222222219 0 0 50000 | |
| g12a_periphs 0 0 0 222222219 0 0 50000 | |
| g12a_pl301 0 0 0 222222219 0 0 50000 | |
| g12a_isa 0 0 0 222222219 0 0 50000 | |
| g12a_eth_phy 1 1 0 222222219 0 0 50000 | |
| g12a_mipi_dsi_host 0 0 0 222222219 0 0 50000 | |
| g12a_audio_locker 0 0 0 222222219 0 0 50000 | |
| g12a_dos 0 0 0 222222219 0 0 50000 | |
| g12a_ddr 0 0 0 222222219 0 0 50000 | |
| fclk_div2_div 1 1 0 999999985 0 0 50000 | |
| fclk_div2 1 1 0 999999985 0 0 50000 | |
| ff3f0000.ethernet#m250_sel 1 1 0 999999985 0 0 50000 | |
| ff3f0000.ethernet#m250_div 1 1 0 249999997 0 0 50000 | |
| ff3f0000.ethernet#fixed_div2 1 1 0 124999998 0 0 50000 | |
| ff3f0000.ethernet#rgmii_tx_en 1 1 0 124999998 0 0 50000 | |
| cpub_clk_dyn1_sel 0 0 0 999999985 0 0 50000 | |
| cpub_clk_dyn1 0 0 0 999999985 0 0 50000 | |
| cpub_clk_dyn 0 0 0 999999985 0 0 50000 | |
| cpub_clk_dyn1_div 0 0 0 999999985 0 0 50000 | |
| mpll_prediv 0 0 0 1999999969 0 0 50000 | |
| mpll0_div 0 0 0 270948747 0 0 50000 | |
| mpll0 0 0 0 270948747 0 0 50000 | |
| aud_spdifout_b_clk_sel 0 0 0 270948747 0 0 50000 | |
| aud_spdifout_b_clk_div 0 0 0 270948747 0 0 50000 | |
| aud_spdifout_b_clk 0 0 0 270948747 0 0 50000 | |
| aud_pdm_sysclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_pdm_sysclk_div 0 0 0 270948747 0 0 50000 | |
| aud_pdm_sysclk 0 0 0 270948747 0 0 50000 | |
| aud_pdm_dclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_pdm_dclk_div 0 0 0 270948747 0 0 50000 | |
| aud_pdm_dclk 0 0 0 270948747 0 0 50000 | |
| aud_spdifin_clk_sel 0 0 0 270948747 0 0 50000 | |
| aud_spdifin_clk_div 0 0 0 270948747 0 0 50000 | |
| aud_spdifin_clk 0 0 0 270948747 0 0 50000 | |
| aud_spdifout_clk_sel 0 0 0 270948747 0 0 50000 | |
| aud_spdifout_clk_div 0 0 0 270948747 0 0 50000 | |
| aud_spdifout_clk 0 0 0 270948747 0 0 50000 | |
| aud_mst_f_mclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_mst_f_mclk_div 0 0 0 270948747 0 0 50000 | |
| aud_mst_f_mclk 0 0 0 270948747 0 0 50000 | |
| aud_mst_f_sclk_pre_en 0 0 0 270948747 0 0 50000 | |
| aud_mst_f_sclk_div 0 0 0 264599 0 0 50000 | |
| aud_mst_f_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_mst_f_lrclk_div 0 0 0 259 0 0 97 | |
| aud_mst_f_lrclk 0 0 0 259 0 0 97 | |
| aud_mst_f_sclk 0 0 0 264599 0 0 50000 | |
| aud_mst_e_mclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_mst_e_mclk_div 0 0 0 270948747 0 0 50000 | |
| aud_mst_e_mclk 0 0 0 270948747 0 0 50000 | |
| aud_mst_e_sclk_pre_en 0 0 0 270948747 0 0 50000 | |
| aud_mst_e_sclk_div 0 0 0 264599 0 0 50000 | |
| aud_mst_e_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_mst_e_lrclk_div 0 0 0 259 0 0 97 | |
| aud_mst_e_lrclk 0 0 0 259 0 0 97 | |
| aud_mst_e_sclk 0 0 0 264599 0 0 50000 | |
| aud_mst_d_mclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_mst_d_mclk_div 0 0 0 270948747 0 0 50000 | |
| aud_mst_d_mclk 0 0 0 270948747 0 0 50000 | |
| aud_mst_d_sclk_pre_en 0 0 0 270948747 0 0 50000 | |
| aud_mst_d_sclk_div 0 0 0 264599 0 0 50000 | |
| aud_mst_d_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_mst_d_lrclk_div 0 0 0 259 0 0 97 | |
| aud_mst_d_lrclk 0 0 0 259 0 0 97 | |
| aud_mst_d_sclk 0 0 0 264599 0 0 50000 | |
| aud_mst_c_mclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_mst_c_mclk_div 0 0 0 270948747 0 0 50000 | |
| aud_mst_c_mclk 0 0 0 270948747 0 0 50000 | |
| aud_mst_c_sclk_pre_en 0 0 0 270948747 0 0 50000 | |
| aud_mst_c_sclk_div 0 0 0 264599 0 0 50000 | |
| aud_mst_c_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_mst_c_lrclk_div 0 0 0 259 0 0 97 | |
| aud_mst_c_lrclk 0 0 0 259 0 0 97 | |
| aud_mst_c_sclk 0 0 0 264599 0 0 50000 | |
| aud_mst_b_mclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_mst_b_mclk_div 0 0 0 270948747 0 0 50000 | |
| aud_mst_b_mclk 0 0 0 270948747 0 0 50000 | |
| aud_mst_b_sclk_pre_en 0 0 0 270948747 0 0 50000 | |
| aud_mst_b_sclk_div 0 0 0 264599 0 0 50000 | |
| aud_mst_b_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_mst_b_lrclk_div 0 0 0 259 0 0 97 | |
| aud_mst_b_lrclk 0 0 0 259 0 0 97 | |
| aud_mst_b_sclk 0 0 0 264599 0 0 50000 | |
| aud_mst_a_mclk_sel 0 0 0 270948747 0 0 50000 | |
| aud_mst_a_mclk_div 0 0 0 270948747 0 0 50000 | |
| aud_mst_a_mclk 0 0 0 270948747 0 0 50000 | |
| aud_mclk_pad_1 0 0 0 270948747 0 0 50000 | |
| aud_mclk_pad_0 0 0 0 270948747 0 0 50000 | |
| aud_mst_a_sclk_pre_en 0 0 0 270948747 0 0 50000 | |
| aud_mst_a_sclk_div 0 0 0 264599 0 0 50000 | |
| aud_mst_a_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_mst_a_lrclk_div 0 0 0 259 0 0 97 | |
| aud_mst_a_lrclk 0 0 0 259 0 0 97 | |
| aud_lrclk_pad_2 0 0 0 259 0 0 97 | |
| aud_lrclk_pad_1 0 0 0 259 0 0 97 | |
| aud_lrclk_pad_0 0 0 0 259 0 0 97 | |
| aud_tdmout_c_lrclk 0 0 0 259 0 0 97 | |
| aud_tdmout_b_lrclk 0 0 0 259 0 0 97 | |
| aud_tdmout_a_lrclk 0 0 0 259 0 0 97 | |
| aud_tdmin_lb_lrclk 0 0 0 259 0 0 97 | |
| aud_tdmin_c_lrclk 0 0 0 259 0 0 97 | |
| aud_tdmin_b_lrclk 0 0 0 259 0 0 97 | |
| aud_tdmin_a_lrclk 0 0 0 259 0 0 97 | |
| aud_mst_a_sclk 0 0 0 264599 0 0 50000 | |
| aud_sclk_pad_2 0 0 0 264599 0 0 50000 | |
| aud_sclk_pad_1 0 0 0 264599 0 0 50000 | |
| aud_sclk_pad_0 0 0 0 264599 0 0 50000 | |
| aud_tdmout_c_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmout_c_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmout_c_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmout_c_sclk 0 0 0 264599 0 0 50000 | |
| aud_tdmout_b_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmout_b_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmout_b_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmout_b_sclk 0 0 0 264599 0 0 50000 | |
| aud_tdmout_a_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmout_a_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmout_a_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmout_a_sclk 0 0 0 264599 0 0 50000 | |
| aud_tdmin_lb_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmin_lb_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_lb_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_lb_sclk 0 0 0 264599 0 0 50000 | |
| aud_tdmin_c_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmin_c_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_c_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_c_sclk 0 0 0 264599 0 0 50000 | |
| aud_tdmin_b_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmin_b_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_b_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_b_sclk 0 0 0 264599 0 0 50000 | |
| aud_tdmin_a_sclk_sel 0 0 0 264599 0 0 50000 | |
| aud_tdmin_a_sclk_pre_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_a_sclk_post_en 0 0 0 264599 0 0 50000 | |
| aud_tdmin_a_sclk 0 0 0 264599 0 0 50000 | |
| mpll1_div 0 0 0 393212849 0 0 50000 | |
| mpll1 0 0 0 393212849 0 0 50000 | |
| mpll2_div 0 0 0 294909637 0 0 50000 | |
| mpll2 0 0 0 294909637 0 0 50000 | |
| mpll3_div 0 0 0 0 0 0 50000 | |
| mpll3 0 0 0 0 0 0 50000 | |
| fclk_div2p5_div 1 1 0 799999987 0 0 50000 | |
| fclk_div2p5 1 1 0 799999987 0 0 50000 | |
| mali_0_sel 1 1 0 799999987 0 0 50000 | |
| mali_0_div 1 1 0 799999987 0 0 50000 | |
| mali_0 1 1 0 799999987 0 0 50000 | |
| mali 1 1 0 799999987 0 0 50000 | |
| vdec_hevcf_sel 0 0 0 799999987 0 0 50000 | |
| vdec_hevcf_div 0 0 0 799999987 0 0 50000 | |
| vdec_hevcf 0 0 0 799999987 0 0 50000 | |
| vdec_hevc_sel 0 0 0 799999987 0 0 50000 | |
| vdec_hevc_div 0 0 0 799999987 0 0 50000 | |
| vdec_hevc 0 0 0 799999987 0 0 50000 | |
| vdec_1_sel 0 0 0 799999987 0 0 50000 | |
| vdec_1_div 0 0 0 799999987 0 0 50000 | |
| vdec_1 0 0 0 799999987 0 0 50000 | |
| sd_emmc_c_clk0_sel 1 1 0 24000000 0 0 50000 | |
| sd_emmc_c_clk0_div 1 1 0 24000000 0 0 50000 | |
| sd_emmc_c_clk0 1 1 0 24000000 0 0 50000 | |
| ffe07000.mmc#mux 1 1 0 24000000 0 0 50000 | |
| ffe07000.mmc#div 1 1 0 400000 0 0 50000 | |
| sd_emmc_b_clk0_sel 1 1 0 24000000 0 0 50000 | |
| sd_emmc_b_clk0_div 1 1 0 24000000 0 0 50000 | |
| sd_emmc_b_clk0 1 1 0 24000000 0 0 50000 | |
| ffe05000.sd#mux 1 1 0 24000000 0 0 50000 | |
| ffe05000.sd#div 1 1 0 400000 0 0 50000 | |
| sd_emmc_a_clk0_sel 0 0 0 24000000 0 0 50000 | |
| sd_emmc_a_clk0_div 0 0 0 24000000 0 0 50000 | |
| sd_emmc_a_clk0 0 0 0 24000000 0 0 50000 | |
| ffd1b000.pwm#mux1 0 0 0 24000000 0 0 50000 | |
| ffd1b000.pwm#mux0 1 1 0 24000000 0 0 50000 | |
| ff802000.pwm#mux1 1 1 0 24000000 0 0 50000 | |
| ff802000.pwm#mux0 0 0 0 24000000 0 0 50000 | |
| cpu_clk_axi_div 0 0 0 0 0 0 50000 | |
| cpu_clk_axi 0 0 0 0 0 0 50000 | |
| cpu_clk_atb_div 0 0 0 0 0 0 50000 | |
| cpu_clk_atb 0 0 0 0 0 0 50000 | |
| cpu_clk_apb_div 0 0 0 0 0 0 50000 | |
| cpu_clk_apb 0 0 0 0 0 0 50000 | |
| cpu_clk_div16_en 0 0 0 0 0 0 50000 | |
| cpu_clk_div16 0 0 0 0 0 0 50000 |
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