bafybeiejkkzkwldmva7lq6kufmmd25npxnvto6za2maugmpp6pixu2ocqi

INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-09-26 18:01:54)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : LFE5UM-45F-8BG381C.
INFO:SoC:System clock: 55.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 32.0KiB Address Space, 2048B Paging, big Ordering (Up to 64 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 32.0KiB Address Space, 2048B Paging, big Ordering (Up to 64 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0xc0000000, Size: 0x10000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:cpu_bus2 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:ECP5PLL:Creating ClkOut0 sys2x_i of 110.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 init of 25.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 6.
INFO:SoCCSRHandler:sdram CSR allocated at Location 7.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x08000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoCCSRHandler:leds CSR allocated at Location 8.
Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Warn : Transport "jtag" was already selected
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 25000 kHz
Info : JTAG tap: ecp5.tap tap/device found: 0x00191043 (mfg: 0x021 (Lattice Semi.), part: 0x0191, ver: 0x0)
Warn : JTAG tap: ecp5.tap       UNEXPECTED: 0x00191043 (mfg: 0x021 (Lattice Semi.), part: 0x0191, ver: 0x0)
Error: JTAG tap: ecp5.tap  expected 1 of 1: 0x81112043 (mfg: 0x021 (Lattice Semi.), part: 0x1112, ver: 0x8)
Info : JTAG tap: auto0.tap tap/device found: 0x01112043 (mfg: 0x021 (Lattice Semi.), part: 0x1112, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x01112043"
Error: IR capture error at bit 10, saw 0x3fffffffffffff051d not 0x...3
Warn : Bypassing JTAG setup events due to errors
Warn : gdb services need one or more targets defined
svf processing file: "/nix/store/mz8jiibaaj17fivkpgnwhx4y9jg8p7rx-libresoc-versa-ecp5-20210925"
40%    Error: tdo check error at line 11
Error:     READ = 0x2224086
Error:     WANT = 0x1112043
Error:     MASK = 0xffffffff
Error: fail to run command at line 12510
Error: tdo check error at line 11
Error:     READ = 0x2224086
Error:     WANT = 0x1112043
Error:     MASK = 0xffffffff
Time used: 0m0s555ms 
svf file programmed failed