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Answers at the bottom

  1. By having the cache act as a bridge between main memory and the CPU, the time it takes to retrieve a block of data from main memory is longer than it would be if the cache did not exist.
  • True
  • False
  1. Typically, a split cache divides both the L1 and L2 caches into an instruction-only cache and a data-only cache.
  • True
  • False
  1. Which is the fastest cache mapping function? Select all that apply.
  • One-way set associative cache
  • Direct-mapped cache
  • Fully associative cache
  • All of these
  1. Which cache mapping function(s) do not require a replacement algorithm? Select all that apply.
  • One-way set associative cache
  • Direct-mapped cache
  • Fully associative cache
  • All of these
  1. Consider this cache design:
  • 1KB of cache
  • 16-bit address
  • Byte aligned
  • 8 byte block
  • Fully associative cache

How many bits would its tag and offset have?

  1. Consider this cache design:
  • 1KB of cache
  • 16-bit address
  • Byte aligned
  • 8 byte block
  • Direct-mapped

How many bits would its tag, index, and offset have?

  1. Consider this cache design:
  • 1KB of cache
  • 16-bit address
  • Byte aligned
  • 8 byte block
  • 4-way set associative

How many bits would its tag, index, and offset have?

  1. Consider this cache design:
  • 1KB of cache
  • 16-bit address
  • Word aligned
  • 64 byte block
  • 2-way set associative

How many bits would its tag, index, and offset have?

  1. Suppose we have a cache with:
  • 256 bytes of cache
  • Byte aligned
  • 16 bytes per cache line
  • One-way set associative

Assume that the cache is initially empty. For each reference, write down the tag (in hex), index, whether that reference is a hit or miss, and the type of miss (compulsory or conflict).

Memory address Tag Index Hit/miss Compulsory/conflict
0x23ab
0xc31b
0xc31a
0xac7a

 

 

 

 

 

 

 

 

 

 

 

 

Answers

  1. False
  2. True
  3. One-way set associative cache and direct-mapped cache
  4. One-way set associative cache and direct-mapped cache
  5. Tag: 13, offset: 3
  6. Tag: 6, index: 7, offset: 3
  7. Tag: 8, index: 5, offset: 3
  8. Tag: 9, index: 3, offset: 4
Memory address Tag Index Hit/miss Compulsory/conflict
0x23ab 23 a Miss Compulsory
0xc31b c3 1 Miss Conflict
0xc31a c3 1 Hit
0xac7a ac 7 Miss Compulsory
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