Marc-AntoineGuay
Marc-AntoineGuay
/ rules.txt
Created
December 28, 2022 17:42
— forked from denniskupec/rules.txt
KiCad DRC rules for JLCPCB, 4-layer PCB
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| (version 1) | |
| # 4-layer, 1oz copper | |
| (rule "Minimum Trace Width and Spacing (inner layer)" | |
| (constraint track_width (min 5mil)) | |
| (constraint clearance (min 5mil)) | |
| (layer inner) | |
| (condition "A.Type == 'track'")) | |
| (rule "Minimum Trace Width and Spacing (outer layer)" |