4to1mux - 4bits wide

41mux.vhd

-- file = "mux45.vhd" , VHDL Representation of 4:1 Mux 
-- note: these two dashes are used to creat a comment line in VHDL
-- VHDL is very syntax specific; Pay close attention to the details below.
library ieee;	-- Specific VHDL library we will use that has definitions
				-- of the variable types shown in the PORT statement below.
				-- This library also supports the functions (and, OR & not) 
				-- we will use in the ARCHITECTURE section.
use ieee.std_logic_1164.all;	-- The package that containing several libraries (including ieee).
								-- This is like an include statement in 'C'.

entity MUX41 is		-- Similar to the project name... it must match the file name 
					-- for MaxPlusII to compile this file properly.	

    port					-- Inputs & Outputs of the design
        (
		S  	 :  in  std_logic_vector(1 downto 0);	
		in0  :  in	std_logic_vector(3 downto 0);	
		in1  :  in	std_logic_vector(3 downto 0);	
		in2  :  in	std_logic_vector(3 downto 0);	
		in3  :  in	std_logic_vector(3 downto 0);	
		Y    :  out	std_logic_vector(3 downto 0)		-- output Y is signal type "bit", note: this line does NOT have a ;
        );
end MUX41;

architecture behavior of MUX41 is	-- This is where we define the circuit function.
begin

        process (S, in0, in1, in2, in3) -- rerun process if any changes, sensitivity list, all inputs 
        begin 
         if (S = "00") then 
			Y <= in0; 
         elsif (S = "01") then 
			Y <= in1; 
	     elsif (S = "10") then 
			Y <= in2;
         elsif (S = "11") then 
			Y <= in3;  
         end if; -- note that *end if* is two words 
        end process;
end behavior;