The 1-Wire protocol is a proprietary protocol (Maxim/Dallas) single-wire interface, half-duplex, bidirectional, low-speed and power, long-distance serial-data communication protocol. It operates over a single data line, without clock signal. But, at least two wires are required for 1-wire bus: Data, GND. An additional wire might be necessary (Vcc), depending on powering mode. The powering modes are: parasitic (no vcc), and conventional (with vcc), as seen on figures below.
A 1-Wire standard has a master and slave configuration, where can only be one master device, and several slave devices.
Every slave has an identification address.
The master device is solely responsible for the read and write operations of the slave devices, so slaves cannot initiate a data transfer on their own.
The typical data speed is 16 kbps, but the 1-wire bus can be overdriven up to 125 kbps.
Both master and slaves have an open-drain (open collector) connection with the data line. Tipically, a 4.7k resistor pulls the data line up.
Communication is initiated by the master using a reset. It pulls down the data line for 480 us and then releases it, allowing the typical pull-up resistor to pull the data line HIGH. If slave devices are connected to the bus, they respond to the reset signal by pulling the data line LOW for 60~240 us. If the line is pulled down by the slave, the master confirms their presence over the bus. After 60~240 us, the slave releases the data line, so the master can start writing.
The LSB is always sent first in the 1-Wire protocol.
After a reset, the master can write and read data with the slave devices. Initially, it sends ROM commands, like the search ROM command (0xF0), to access the ROM address of the slave devices. After reading the ROM addresses of all the connected 1-Wire slave devices, the master device can access one by sending the Match ROM command (0x55). The ROM commands are followed by the function ones.
Since the 1-wire standard does not use any clock signal, communication of the '0' and '1' bits occur by setting the logical level of the data line for a specific time slot. Usually, the time slot is 60 us long. There's also an interval of 1 us between each time slot, so that the data line is pulled HIGH again by the pullup resistor. During each 60 us time slot, 1 bit is communicated between the master and slave. The time slot can be up to 10 times shorter if the bus is overdriven.
- To write '0', the master pulls down the data line for the full 60 us time slot, then releases it for a 1 us interval between the time slots.
- To write '1', the master pulls the data line down for a shorter period of 15 us, during the entire time slot, then releases it for a 1 us interval between the time slots.
The slave devices sample at about the mid-time slot (i.e. 30 us in the 60 us time slot). The ROM and function commands are 8-bit long. The data communicated is also in group of 8 bits. The error detection is performed by an 8-bit cyclic redundancy check.
The master reads from the slave device after sending a ROM search or function command. The read operation is controlled by the master device. The master reads from the slave bit-by-bit in groups of 8 bits. Each bit is read in a 60 us time slot.
The master pulls the data line down for 1 us and releases it. Then, it samples the data from the bus after 15 us. If the slave writes '0' over the bus, it keeps the line pulled down for the full 60 us of time slot, and then releases the data line for a 1 us interval between the time slots. If the slave writes '1' over the bus, it keeps the line pulled down for 15 us, and then releases the data line for the pull-up resistor to pull the data line HIGH.
The master samples each bit after 15 us. If the bit sent by the slave is '0', the line is pulled LOW at the time of sampling. If the bit sent by the slave is '1', the line is pulled HIGH at the time of sampling.
The master initiates every communication on the bus down to the bit-level. This means that for every bit that is to be transmitted, regardless of direction, the master has to initiate the bit transmission. This is always done by pulling the bus low, which will synchronize the timing logic of all units. There are five basic commands for communication on the 1-Wire bus: “Write 1”, “Write 0”, “Read”, “Reset” and “Presence”.
- Write '1' signal: The master pulls the bus low for 1 to 15 μs. It then releases the bus for the rest of the time slot.
- Write '0' signal: The master pulls the bus low for a period of at least 60 μs, with a maximum length of 120 μs.
- Read signal: The master pulls the bus low for 1 to 15 μs. The slave then holds the bus low if it wants to send a ‘0’. If it wants to send a ‘1’, it simply releases the line. The bus should be sampled 15 μs after the bus was pulled low. As seen from the master’s side, the “Read” signal is, in essence, a “Write 1” signal. It is the internal state of the slave, rather than the signal itself that dictates whether it is a “Write 1” or “Read” signal.
- Reset / Presence signal: Note that the time scale is different from the first waveforms. The master pulls the bus low for at least eight time slots, or 480 μs, and then releases it. This long low period is called the “Reset” signal. If there is a slave present, it should then pull the bus low within 60 μs after it was released by the master and hold it low for at least 60 μs. This response is called a “Presence” signal. If no presence signal is issued on the bus, the master must assume that no device is present on the bus, and further communication is not possible.
The basic 1-Wire signals can also be generated by a UART. This requires both the TXD and RXD pins to be connected to the bus. An external open-collector or open-drain buffer is required to allow slave devices to pull the bus low when the UART output is high.
The UART data format used when generating 1-Wire signals is eight data bits, no parity, and one stop byte. One UART data frame is used to generate the waveform for one bit or one RESET/PRESENCE sequence. The table below shows how to set up the UART module to generate the waveforms and how to interpret the received data.
Every 1-Wire device contains a globally unique 64-bit identifier number stored in ROM. This number can be used to facilitate addressing or identification of individual devices on the bus. The identifier consists of three parts; an 8-bit family code, a 48-bit serial number, and an 8-bit CRC computed from the first 56 bits. A small set of commands that operate on the 64-bit identifier is defined. These are called ROM function commands. The table below lists the six defined ROM commands.
The “READ ROM” command can be used on a bus with a single slave to read the 64-bit unique identifier. If there are several slave devices connected to the bus, the result of this command will be the AND result of all slave device identifiers. Assumed that communication is flawless, the presence of several slaves is indicated by a failed CRC.
The “SKIP ROM” command can be used when no specific slave is targeted. On a one-slave bus, the “SKIP ROM” command is sufficient for addressing. On a multiple-slave bus, the “SKIP ROM” command can be used to address all devices at once. This is only useful when sending commands to slave devices, e.g., to start temperature conversions on several temperature sensors at once. It is not possible to use the “SKIP ROM” command when reading from slave devices on a multiple-slave bus.
The “MATCH ROM” command is used to address individual slave devices on the bus. After the “MATCH ROM” command, the complete 64-bit identifier is transmitted on the bus. When this is done, only the device with exactly this identifier is allowed to answer until the next reset pulse is received.
The “SEARCH ROM” command can be used when the identifiers of all slave devices are not known in advance. It makes it possible to discover the identifiers of all the slaves present on the bus. First, the “SEARCH ROM” command is transmitted on the bus. The master then reads one bit from the bus. Each slave places the first bit of its identifier on the bus. The master will read this as the logical AND result of the first bit of all slave identifiers. The master then reads one more bit from the bus. Each slave then places the complement of the first bit of its identifier on the bus. The master will read this as the logical AND of the complement of the first bit of the identifier of all slaves. If all devices have ‘1’ as the first bit, the master will have read 10b. Similarly, if all devices have ‘0’ as the first bit, the master will have read 01b. In these cases, the bit can be stored as the first bit of all addresses. The master will then write back this bit, which in effect, will tell all slaves to keep sending identifier bits. If there are devices with both ‘0’ and ‘1’ as the first bit in the identifier on the bus, the master will have read 00. In this case, the master must choose, whether to continue with the addresses that have ‘0’ in this position or ‘1’. The choice is transmitted on the bus, in effect making all slaves that do not have this bit in this position of the identifier, enter an idle state.
The master then goes on to read the next bit, and the process is repeated until all 64 bits are read. The master should then have discovered one complete 64-bit identifier. To discover more identifiers, the “SEARCH ROM” command should be run again, but this time a different choice for the bit value should be made the first time there is a discrepancy. Repeating this once for each slave device should discover all slaves. Note that when one search has been performed, all slaves except one should have entered an idle state. It is now possible to communicate with the active slave without specifically addressing it with the MATCH ROM command.
There are 8 bytes that identifies a device. You should see the device datasheet to be sure about the structure of the bytes, but most of them are structured as follows:
- 1-byte Family code (LSB)
- 6-byte Unique ID
- 1-byte CRC (MSB)
The 8th byte of the ROM ID is the cyclic redundancy check (CRC), based on the previous 7 bytes.
- 8-bit CRC computing
The hardware equivalent of the 8-bit CRC is shown below:
The equivalent CRC polynomial is
| X8 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 |
|---|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
To get the hex representation of the polynom, there are 4 variations:
-
not reflected, drop high order bit: 00110001 -> 0x31
-
not reflected, drop low order bit: 10011000 -> 0x98
-
reflected, drop high order bit: 00011001 -> 0x19
-
reflected, drop low order bit: 10001100 -> 0x8C
OneWire protocol starts transmission with LS-Bit. So we choose the reflected variation, and shift the byte to right (drop low order bit). So we get 0x8C. See Section 7 of Ray & Koopman.
byte dsCRC8(const uint8_t *addr, uint8_t len)//begins from LS-bit of LS-byte (OneWire.h)
{
uint8_t crc = 0;
while (len--)
{
uint8_t inbyte = *addr++;
for (uint8_t i = 8; i; i--)
{
uint8_t mix = (crc ^ inbyte) & 0x01;
crc >>= 1;
if (mix) crc ^= 0x8C;
inbyte >>= 1;
}
}
return crc;
}
What is the 1-Wire protocol? - engineersgarage.com
1-Wire implementation for AVR - kampi.gitbook.io
Theory of Operation - The Dallas 1-Wire® Protocol - microchip.com
AN937 Maxim Book of iButton Standards
Efficient High Hamming Distance CRCs for Embedded Networks
Help coding CRC - Arduino Forum
Video - 1-Wire – Through the Looking Glass (Scope) and Down the Rabbit Hole (Bit Level)