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| diff --git src/jit/graph.c src/jit/graph.c | |
| index a610001ee..7fb822d52 100644 | |
| --- src/jit/graph.c | |
| +++ src/jit/graph.c | |
| @@ -413,6 +413,8 @@ static void * op_to_func(MVMThreadContext *tc, MVMint16 opcode) { | |
| case MVM_OP_getuniprop_bool: return MVM_unicode_codepoint_get_property_bool; | |
| case MVM_OP_getuniprop_str: return MVM_unicode_codepoint_get_property_str; | |
| + case MVM_OP_ctxouter: return MVM_context_apply_traversal; | |
| + | |
| default: | |
| MVM_oops(tc, "JIT: No function for op %d in op_to_func (%s)", opcode, MVM_op_get_op(opcode)->name); | |
| } | |
| @@ -2955,6 +2957,15 @@ start: | |
| MVM_JIT_RV_PTR, dst); | |
| break; | |
| } | |
| + case MVM_OP_ctxouter: { | |
| + MVMint16 dst = ins->operands[0].reg.orig; | |
| + MVMint16 ctx = ins->operands[1].reg.orig; | |
| + MVMJitCallArg args[] = { { MVM_JIT_INTERP_VAR, { MVM_JIT_INTERP_TC } }, | |
| + { MVM_JIT_REG_VAL, { ctx } }, | |
| + { MVM_JIT_LITERAL, { MVM_CTX_TRAV_OUTER } } }; | |
| + jg_append_call_c(tc, jg, op_to_func(tc, op), 3, args, MVM_JIT_RV_PTR, dst); | |
| + break; | |
| + } | |
| case MVM_OP_escape: | |
| case MVM_OP_uc: | |
| case MVM_OP_lc: |
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| diff --git src/jit/graph.c src/jit/graph.c | |
| index a610001ee..f25d4f983 100644 | |
| --- src/jit/graph.c | |
| +++ src/jit/graph.c | |
| @@ -1819,6 +1819,7 @@ start: | |
| case MVM_OP_ctx: | |
| case MVM_OP_ctxlexpad: | |
| case MVM_OP_ctxcallerskipthunks: | |
| + case MVM_OP_ctxouter: | |
| case MVM_OP_curcode: | |
| case MVM_OP_getcode: | |
| case MVM_OP_sp_fastcreate: | |
| diff --git src/jit/x64/emit.dasc src/jit/x64/emit.dasc | |
| index c8ebdbae1..61a78fe70 100644 | |
| --- src/jit/x64/emit.dasc | |
| +++ src/jit/x64/emit.dasc | |
| @@ -1047,6 +1047,29 @@ void MVM_jit_emit_primitive(MVMThreadContext *tc, MVMJitCompiler *compiler, MVMJ | |
| |2: | |
| break; | |
| } | |
| + case MVM_OP_ctxouter: { | |
| + MVMint16 dst = ins->operands[0].reg.orig; | |
| + MVMint16 ctx = ins->operands[1].reg.orig; | |
| + /* ctx = NULL */ | |
| + | xor RV, RV; | |
| + | mov TMP5, aword WORK[ctx]; | |
| + /* check concrete instance of type or throw */ | |
| + | test_type_object TMP5; | |
| + | jnz >1; | |
| + | cmp_repr_id TMP5, TMP6, MVM_REPR_ID_MVMContext; | |
| + | jne >1; | |
| + /* Call function to create context. */ | |
| + | mov ARG1, TC | |
| + | mov ARG2, TMP5 | |
| + | mov ARG3, MVM_CTX_TRAV_OUTER | |
| + | callp &MVM_context_apply_traversal; | |
| + | mov WORK[dst], RV; | |
| + | jmp >2; | |
| + |1: | |
| + | throw_adhoc "ctxouter needs an MVMContext"; | |
| + |2: | |
| + break; | |
| + } | |
| case MVM_OP_curcode: { | |
| MVMint16 dst = ins->operands[0].reg.orig; | |
| | mov TMP1, TC->cur_frame; |
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| Specialization of 'SET_BLOCK_OUTER_CTX' (cuid: 103) | |
| Before: | |
| Spesh of 'SET_BLOCK_OUTER_CTX' (cuid: 103, file: gen/moar/stage2/NQPHLL.nqp:1499) | |
| BB 0 (0x7f84440399a8): | |
| line: 1499 (pc 0) | |
| Instructions: | |
| no_op | |
| Successors: 1, 20, 24 | |
| Predecessors: | |
| Dominance children: 1, 19, 20, 22, 24, 111, 113 | |
| BB 1 (0x7f8444039a30): | |
| line: 1499 (pc 0) | |
| Instructions: | |
| null r0(1) | |
| null r1(1) | |
| null r2(1) | |
| null r4(1) | |
| null r5(1) | |
| null r6(1) | |
| null r7(1) | |
| null r8(1) | |
| null r9(1) | |
| null r10(1) | |
| null r13(1) | |
| null r15(1) | |
| null r16(1) | |
| null r18(1) | |
| null r24(1) | |
| null r27(1) | |
| null r29(1) | |
| null r31(1) | |
| null r33(1) | |
| null r36(1) | |
| null r38(1) | |
| null r40(1) | |
| null r42(1) | |
| checkarity liti16(2), liti16(2) | |
| param_rp_o r0(2), liti16(0) | |
| param_rp_o r1(2), liti16(1) | |
| paramnamesused | |
| [Annotation: Line Number: gen/moar/stage2/NQPHLL.nqp:1499] | |
| const_s r3(1), lits(%*COMPILING) | |
| getdynlex r4(2), r3(1) | |
| ifnonnull r4(2), BB(9) | |
| Successors: 9, 2 | |
| Predecessors: 0 | |
| Dominance children: 2, 9, 10 | |
| BB 2 (0x7f8444039a90): | |
| line: 1499 (pc 42) | |
| Instructions: | |
| wval r8(2), liti16(0), liti16(0) (not deserialized) | |
| getwho r8(3), r8(2) | |
| set r7(2), r8(3) | |
| const_s r3(2), lits(%COMPILING) | |
| atkey_o r8(4), r7(2), r3(2) | |
| ifnonnull r8(4), BB(4) | |
| Successors: 4, 3 | |
| Predecessors: 1 | |
| Dominance children: 3, 4, 5 | |
| BB 3 (0x7f8444039af0): | |
| line: 1499 (pc 86) | |
| Instructions: | |
| const_s r3(3), lits(%COMPILING) | |
| hllhash r10(2) | |
| create r10(3), r10(2) | |
| bindkey_o r7(2), r3(3), r10(3) | |
| set r9(2), r10(3) | |
| goto BB(5) | |
| Successors: 5 | |
| Predecessors: 2 | |
| Dominance children: | |
| BB 4 (0x7f8444039b50): | |
| line: 1499 (pc 124) | |
| Instructions: | |
| set r9(3), r8(4) | |
| Successors: 5 | |
| Predecessors: 2 | |
| Dominance children: | |
| BB 5 (0x7f8444039bb0): | |
| line: 1499 (pc 130) | |
| Instructions: | |
| PHI r10(4), r10(3), r10(1) | |
| PHI r9(4), r9(2), r9(3) | |
| PHI r3(4), r3(3), r3(2) | |
| set r6(2), r9(4) | |
| ifnonnull r9(4), BB(8) | |
| Successors: 8, 6 | |
| Predecessors: 3, 4 | |
| Dominance children: 6, 8 | |
| BB 6 (0x7f8444039c10): | |
| line: 1499 (pc 144) | |
| Instructions: | |
| const_s r3(5), lits(Contextual %*COMPILING not found) | |
| die r10(5), r3(5) | |
| Successors: 7 | |
| Predecessors: 5 | |
| Dominance children: 7 | |
| BB 7 (0x7f8444039c70): | |
| line: 1499 (pc 158) | |
| Instructions: | |
| set r6(3), r10(5) | |
| Successors: 8 | |
| Predecessors: 6 | |
| Dominance children: | |
| BB 8 (0x7f8444039cd0): | |
| line: 1499 (pc 164) | |
| Instructions: | |
| PHI r10(6), r10(4), r10(5) | |
| PHI r6(4), r6(2), r6(3) | |
| PHI r3(6), r3(4), r3(5) | |
| set r5(2), r6(4) | |
| goto BB(10) | |
| Successors: 10 | |
| Predecessors: 5, 7 | |
| Dominance children: | |
| BB 9 (0x7f8444039d30): | |
| line: 1499 (pc 176) | |
| Instructions: | |
| set r5(3), r4(2) | |
| Successors: 10 | |
| Predecessors: 1 | |
| Dominance children: | |
| BB 10 (0x7f8444039d90): | |
| line: 1499 (pc 182) | |
| Instructions: | |
| PHI r10(7), r10(6), r10(1) | |
| PHI r9(5), r9(4), r9(1) | |
| PHI r8(5), r8(4), r8(1) | |
| PHI r7(3), r7(2), r7(1) | |
| PHI r6(5), r6(4), r6(1) | |
| PHI r5(4), r5(2), r5(3) | |
| PHI r3(7), r3(6), r3(1) | |
| const_s r3(8), lits(%?OPTIONS) | |
| atkey_o r5(5), r5(4), r3(8) | |
| ifnonnull r5(5), BB(12) | |
| Successors: 12, 11 | |
| Predecessors: 8, 9 | |
| Dominance children: 11, 12, 13 | |
| BB 11 (0x7f8444039df0): | |
| line: 1499 (pc 206) | |
| Instructions: | |
| wval r4(3), liti16(1), liti16(44) (P6opaque: NQPMu) | |
| set r6(6), r4(3) | |
| goto BB(13) | |
| Successors: 13 | |
| Predecessors: 10 | |
| Dominance children: | |
| BB 12 (0x7f8444039e50): | |
| line: 1499 (pc 226) | |
| Instructions: | |
| set r6(7), r5(5) | |
| Successors: 13 | |
| Predecessors: 10 | |
| Dominance children: | |
| BB 13 (0x7f8444039eb0): | |
| line: 1499 (pc 232) | |
| Instructions: | |
| PHI r6(8), r6(6), r6(7) | |
| PHI r4(4), r4(3), r4(2) | |
| const_s r3(9), lits(outer_ctx) | |
| atkey_o r6(9), r6(8), r3(9) | |
| ifnonnull r6(9), BB(15) | |
| Successors: 15, 14 | |
| Predecessors: 11, 12 | |
| Dominance children: 14, 15, 16 | |
| BB 14 (0x7f8444039f10): | |
| line: 1499 (pc 256) | |
| Instructions: | |
| wval r5(6), liti16(1), liti16(44) (P6opaque: NQPMu) | |
| set r4(5), r5(6) | |
| goto BB(16) | |
| Successors: 16 | |
| Predecessors: 13 | |
| Dominance children: | |
| BB 15 (0x7f8444039f70): | |
| line: 1499 (pc 276) | |
| Instructions: | |
| set r4(6), r6(9) | |
| Successors: 16 | |
| Predecessors: 13 | |
| Dominance children: | |
| BB 16 (0x7f8444039fd0): | |
| line: 1499 (pc 282) | |
| Instructions: | |
| PHI r5(7), r5(6), r5(5) | |
| PHI r4(7), r4(5), r4(6) | |
| set r2(2), r4(7) | |
| [Annotation: INS Deopt One (idx 0 -> pc 294; line 1499)] | |
| [Annotation: Logged (bytecode offset 288)] | |
| decont r4(8), r2(2) | |
| Successors: 17 | |
| Predecessors: 14, 15 | |
| Dominance children: 17 | |
| BB 17 (0x7f844403a030): | |
| line: 1499 (pc 294) | |
| Instructions: | |
| isconcrete r11(1), r4(8) | |
| hllboxtype_i r42(2) | |
| box_i r42(3), r11(1), r42(2) | |
| set r10(8), r42(3) | |
| unless_i r11(1), BB(113) | |
| Successors: 113, 18 | |
| Predecessors: 16 | |
| Dominance children: 18 | |
| BB 18 (0x7f844403a090): | |
| line: 1501 (pc 326) | |
| Instructions: | |
| [Annotation: Line Number: gen/moar/stage2/NQPHLL.nqp:1501] | |
| null r4(9) | |
| Successors: 19 | |
| Predecessors: 17 | |
| Dominance children: | |
| BB 19 (0x7f844403a0f0): | |
| line: 1501 (pc 330) | |
| Instructions: | |
| PHI r42(4), r42(3), r42(10) | |
| PHI r41(1), r41(0), r41(8) | |
| PHI r40(2), r40(1), r40(10) | |
| PHI r39(1), r39(0), r39(8) | |
| PHI r38(2), r38(1), r38(10) | |
| PHI r37(1), r37(0), r37(8) | |
| PHI r36(2), r36(1), r36(10) | |
| PHI r35(1), r35(0), r35(10) | |
| PHI r34(1), r34(0), r34(8) | |
| PHI r33(2), r33(1), r33(10) | |
| PHI r32(1), r32(0), r32(8) | |
| PHI r31(2), r31(1), r31(10) | |
| PHI r30(1), r30(0), r30(8) | |
| PHI r29(2), r29(1), r29(10) | |
| PHI r28(1), r28(0), r28(8) | |
| PHI r27(2), r27(1), r27(10) | |
| PHI r26(1), r26(0), r26(15) | |
| PHI r25(1), r25(0), r25(8) | |
| PHI r24(2), r24(1), r24(10) | |
| PHI r23(1), r23(0), r23(7) | |
| PHI r22(1), r22(0), r22(8) | |
| PHI r21(1), r21(0), r21(8) | |
| PHI r20(1), r20(0), r20(8) | |
| PHI r19(1), r19(0), r19(26) | |
| PHI r18(2), r18(1), r18(8) | |
| PHI r17(1), r17(0), r17(6) | |
| PHI r16(2), r16(1), r16(7) | |
| PHI r15(2), r15(1), r15(7) | |
| PHI r14(1), r14(0), r14(6) | |
| PHI r13(2), r13(1), r13(7) | |
| PHI r12(1), r12(0), r12(6) | |
| PHI r11(2), r11(1), r11(6) | |
| PHI r10(9), r10(8), r10(39) | |
| PHI r9(6), r9(5), r9(13) | |
| PHI r8(6), r8(5), r8(14) | |
| PHI r7(4), r7(3), r7(8) | |
| PHI r6(10), r6(9), r6(21) | |
| PHI r5(8), r5(7), r5(21) | |
| PHI r4(10), r4(9), r4(14) | |
| PHI r3(10), r3(9), r3(20) | |
| PHI r2(3), r2(2), r2(8) | |
| PHI r1(3), r1(2), r1(7) | |
| PHI r0(3), r0(2), r0(7) | |
| isnull r12(2), r2(3) | |
| if_i r12(2), BB(112) | |
| Successors: 112, 20 | |
| Predecessors: 18, 111 | |
| Dominance children: 112 | |
| BB 20 (0x7f844403a150): | |
| line: 1501 (pc 344) | |
| Instructions: | |
| PHI r42(5), r42(0), r42(4) | |
| PHI r41(2), r41(0), r41(1) | |
| PHI r40(3), r40(0), r40(2) | |
| PHI r39(2), r39(0), r39(1) | |
| PHI r38(3), r38(0), r38(2) | |
| PHI r37(2), r37(0), r37(1) | |
| PHI r36(3), r36(0), r36(2) | |
| PHI r35(2), r35(0), r35(1) | |
| PHI r34(2), r34(0), r34(1) | |
| PHI r33(3), r33(0), r33(2) | |
| PHI r32(2), r32(0), r32(1) | |
| PHI r31(3), r31(0), r31(2) | |
| PHI r30(2), r30(0), r30(1) | |
| PHI r29(3), r29(0), r29(2) | |
| PHI r28(2), r28(0), r28(1) | |
| PHI r27(3), r27(0), r27(2) | |
| PHI r26(2), r26(0), r26(1) | |
| PHI r25(2), r25(0), r25(1) | |
| PHI r24(3), r24(0), r24(2) | |
| PHI r23(2), r23(0), r23(1) | |
| PHI r22(2), r22(0), r22(1) | |
| PHI r21(2), r21(0), r21(1) | |
| PHI r20(2), r20(0), r20(1) | |
| PHI r19(2), r19(0), r19(1) | |
| PHI r18(3), r18(0), r18(2) | |
| PHI r17(2), r17(0), r17(1) | |
| PHI r16(3), r16(0), r16(2) | |
| PHI r15(3), r15(0), r15(2) | |
| PHI r14(2), r14(0), r14(1) | |
| PHI r13(3), r13(0), r13(2) | |
| PHI r12(3), r12(0), r12(2) | |
| PHI r11(3), r11(0), r11(2) | |
| PHI r10(11), r10(0), r10(9) | |
| PHI r9(7), r9(0), r9(6) | |
| PHI r8(7), r8(0), r8(6) | |
| PHI r7(5), r7(0), r7(4) | |
| PHI r6(11), r6(0), r6(10) | |
| PHI r5(9), r5(0), r5(8) | |
| PHI r4(11), r4(0), r4(10) | |
| PHI r3(11), r3(0), r3(10) | |
| PHI r2(4), r2(0), r2(3) | |
| PHI r1(4), r1(0), r1(3) | |
| PHI r0(4), r0(0), r0(3) | |
| [Annotation: INS Deopt OSR (idx 1 -> pc 346); line 1502] | |
| osrpoint | |
| ctxlexpad r5(10), r2(4) | |
| set r13(4), r5(10) | |
| isnull r14(3), r13(4) | |
| if_i r14(3), BB(111) | |
| Successors: 111, 21 | |
| Predecessors: 0, 19 | |
| Dominance children: 21 | |
| BB 21 (0x7f844403a1b0): | |
| line: 1504 (pc 372) | |
| Instructions: | |
| iter r5(11), r13(4) | |
| set r15(4), r5(11) | |
| Successors: 22 | |
| Predecessors: 20 | |
| Dominance children: | |
| BB 22 (0x7f844403a210): | |
| line: 1504 (pc 384) | |
| Instructions: | |
| PHI r42(6), r42(5), r42(6), r42(6), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(8), r42(8), r42(7), r42(7), r42(9) | |
| PHI r41(3), r41(2), r41(3), r41(3), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6), r41(6), r41(6), r41(6), r41(7) | |
| PHI r40(4), r40(3), r40(4), r40(4), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(6), r40(6), r40(5), r40(5), r40(5), r40(7), r40(8), r40(5), r40(5), r40(9) | |
| PHI r39(3), r39(2), r39(3), r39(3), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(7) | |
| PHI r38(4), r38(3), r38(4), r38(4), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(6), r38(6), r38(5), r38(5), r38(5), r38(7), r38(8), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(9) | |
| PHI r37(3), r37(2), r37(3), r37(3), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(7) | |
| PHI r36(4), r36(3), r36(4), r36(4), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(6), r36(6), r36(5), r36(5), r36(5), r36(7), r36(8), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(9) | |
| PHI r35(3), r35(2), r35(3), r35(3), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(5), r35(5), r35(4), r35(4), r35(6), r35(6), r35(6), r35(4), r35(4), r35(7), r35(7), r35(7), r35(4), r35(4), r35(8), r35(8), r35(8), r35(4), r35(4), r35(9) | |
| PHI r34(3), r34(2), r34(3), r34(3), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(7) | |
| PHI r33(4), r33(3), r33(4), r33(4), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(6), r33(6), r33(5), r33(5), r33(5), r33(7), r33(8), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(9) | |
| PHI r32(3), r32(2), r32(3), r32(3), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(7) | |
| PHI r31(4), r31(3), r31(4), r31(4), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(6), r31(6), r31(5), r31(5), r31(5), r31(7), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(9) | |
| PHI r30(3), r30(2), r30(3), r30(3), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(7) | |
| PHI r29(4), r29(3), r29(4), r29(4), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(6), r29(6), r29(5), r29(5), r29(5), r29(7), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(9) | |
| PHI r28(3), r28(2), r28(3), r28(3), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(7) | |
| PHI r27(4), r27(3), r27(4), r27(4), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(6), r27(6), r27(6), r27(5), r27(5), r27(5), r27(7), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(9) | |
| PHI r26(3), r26(2), r26(3), r26(3), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(5), r26(5), r26(5), r26(4), r26(4), r26(6), r26(6), r26(6), r26(4), r26(4), r26(7), r26(7), r26(7), r26(4), r26(4), r26(8), r26(8), r26(8), r26(4), r26(4), r26(9), r26(9), r26(9), r26(4), r26(4), r26(10), r26(10), r26(10), r26(4), r26(4), r26(11), r26(11), r26(11), r26(4), r26(4), r26(12), r26(12), r26(12), r26(4), r26(13), r26(14) | |
| PHI r25(3), r25(2), r25(3), r25(3), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(7) | |
| PHI r24(4), r24(3), r24(4), r24(4), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(6), r24(6), r24(6), r24(5), r24(5), r24(5), r24(7), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(9) | |
| PHI r23(3), r23(2), r23(3), r23(3), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(5), r23(5), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(6) | |
| PHI r22(3), r22(2), r22(3), r22(3), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(7) | |
| PHI r21(3), r21(2), r21(3), r21(3), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(7) | |
| PHI r20(3), r20(2), r20(3), r20(3), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(7) | |
| PHI r19(3), r19(2), r19(3), r19(3), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(5), r19(6), r19(6), r19(6), r19(6), r19(6), r19(7), r19(8), r19(8), r19(8), r19(7), r19(9), r19(9), r19(9), r19(9), r19(9), r19(10), r19(10), r19(10), r19(10), r19(10), r19(11), r19(12), r19(12), r19(12), r19(11), r19(13), r19(14), r19(14), r19(14), r19(13), r19(15), r19(16), r19(16), r19(16), r19(15), r19(17), r19(18), r19(18), r19(18), r19(17), r19(19), r19(20), r19(20), r19(20), r19(19), r19(21), r19(22), r19(22), r19(22), r19(21), r19(23), r19(24), r19(24), r19(24), r19(23), r19(23), r19(25) | |
| PHI r18(4), r18(3), r18(4), r18(4), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(7) | |
| PHI r17(3), r17(2), r17(3), r17(3), r17(4), r17(4), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5) | |
| PHI r16(4), r16(3), r16(4), r16(4), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6) | |
| PHI r15(5), r15(4), r15(5), r15(5), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6) | |
| PHI r14(4), r14(3), r14(4), r14(4), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5) | |
| PHI r13(5), r13(4), r13(5), r13(5), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6) | |
| PHI r12(4), r12(3), r12(4), r12(4), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5) | |
| PHI r11(4), r11(3), r11(4), r11(4), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5) | |
| PHI r10(12), r10(11), r10(12), r10(12), r10(13), r10(13), r10(13), r10(13), r10(13), r10(14), r10(14), r10(14), r10(14), r10(15), r10(15), r10(15), r10(16), r10(16), r10(17), r10(17), r10(17), r10(18), r10(18), r10(19), r10(19), r10(19), r10(20), r10(20), r10(21), r10(21), r10(21), r10(22), r10(22), r10(23), r10(23), r10(23), r10(24), r10(24), r10(25), r10(25), r10(25), r10(26), r10(26), r10(27), r10(27), r10(27), r10(28), r10(28), r10(29), r10(29), r10(29), r10(30), r10(30), r10(31), r10(31), r10(31), r10(32), r10(32), r10(33), r10(33), r10(33), r10(34), r10(34), r10(35), r10(35), r10(35), r10(37), r10(37), r10(38) | |
| PHI r9(8), r9(7), r9(8), r9(8), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(10), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(12) | |
| PHI r8(8), r8(7), r8(8), r8(8), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(10), r8(10), r8(10), r8(9), r8(9), r8(9), r8(11), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(13) | |
| PHI r7(6), r7(5), r7(6), r7(6), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7) | |
| PHI r6(12), r6(11), r6(12), r6(12), r6(13), r6(13), r6(14), r6(14), r6(14), r6(14), r6(14), r6(17), r6(17), r6(17), r6(18), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(20) | |
| PHI r5(12), r5(11), r5(13), r5(13), r5(16), r5(16), r5(16), r5(17), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18) | |
| PHI r4(12), r4(11), r4(12), r4(12), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13) | |
| PHI r3(12), r3(11), r3(12), r3(12), r3(13), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(15), r3(15), r3(15), r3(14), r3(14), r3(16), r3(16), r3(16), r3(14), r3(14), r3(17), r3(17), r3(17), r3(14), r3(14), r3(18), r3(18), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(19) | |
| PHI r2(5), r2(4), r2(5), r2(5), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6) | |
| PHI r1(5), r1(4), r1(5), r1(5), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6) | |
| PHI r0(5), r0(4), r0(5), r0(5), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6) | |
| [Annotation: FH Start (2)] | |
| [Annotation: FH Goto (1)] | |
| [Annotation: FH Start (1)] | |
| [Annotation: FH Start (0)] | |
| [Annotation: INS Deopt One (idx 2 -> pc 390; line 1504)] | |
| [Annotation: Logged (bytecode offset 384)] | |
| decont r5(13), r15(5) | |
| Successors: 23, 24, 22, 111 | |
| Predecessors: 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 38, 39, 41, 42, 43, 45, 46, 48, 49, 50, 52, 53, 55, 56, 57, 59, 60, 62, 63, 64, 66, 67, 69, 70, 71, 73, 74, 76, 77, 78, 80, 81, 83, 84, 85, 87, 88, 90, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, 106, 108, 109, 110 | |
| Dominance children: 23 | |
| BB 23 (0x7f844403a270): | |
| line: 1504 (pc 390) | |
| Instructions: | |
| unless_o r5(13), BB(111) | |
| Successors: 111, 24, 22 | |
| Predecessors: 22 | |
| Dominance children: | |
| BB 24 (0x7f844403a2d0): | |
| line: 1504 (pc 398) | |
| Instructions: | |
| PHI r42(7), r42(0), r42(6), r42(6), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(8), r42(8), r42(7), r42(7) | |
| PHI r41(4), r41(0), r41(3), r41(3), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6), r41(6), r41(6), r41(6) | |
| PHI r40(5), r40(0), r40(4), r40(4), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(6), r40(6), r40(5), r40(5), r40(5), r40(7), r40(8), r40(5), r40(5) | |
| PHI r39(4), r39(0), r39(3), r39(3), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6) | |
| PHI r38(5), r38(0), r38(4), r38(4), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(6), r38(6), r38(5), r38(5), r38(5), r38(7), r38(8), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5) | |
| PHI r37(4), r37(0), r37(3), r37(3), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6) | |
| PHI r36(5), r36(0), r36(4), r36(4), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(6), r36(6), r36(5), r36(5), r36(5), r36(7), r36(8), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5) | |
| PHI r35(4), r35(0), r35(3), r35(3), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(5), r35(5), r35(4), r35(4), r35(6), r35(6), r35(6), r35(4), r35(4), r35(7), r35(7), r35(7), r35(4), r35(4), r35(8), r35(8), r35(8), r35(4), r35(4) | |
| PHI r34(4), r34(0), r34(3), r34(3), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6) | |
| PHI r33(5), r33(0), r33(4), r33(4), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(6), r33(6), r33(5), r33(5), r33(5), r33(7), r33(8), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5) | |
| PHI r32(4), r32(0), r32(3), r32(3), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6) | |
| PHI r31(5), r31(0), r31(4), r31(4), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(6), r31(6), r31(5), r31(5), r31(5), r31(7), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5) | |
| PHI r30(4), r30(0), r30(3), r30(3), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6) | |
| PHI r29(5), r29(0), r29(4), r29(4), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(6), r29(6), r29(5), r29(5), r29(5), r29(7), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5) | |
| PHI r28(4), r28(0), r28(3), r28(3), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6) | |
| PHI r27(5), r27(0), r27(4), r27(4), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(6), r27(6), r27(6), r27(5), r27(5), r27(5), r27(7), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5) | |
| PHI r26(4), r26(0), r26(3), r26(3), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(5), r26(5), r26(5), r26(4), r26(4), r26(6), r26(6), r26(6), r26(4), r26(4), r26(7), r26(7), r26(7), r26(4), r26(4), r26(8), r26(8), r26(8), r26(4), r26(4), r26(9), r26(9), r26(9), r26(4), r26(4), r26(10), r26(10), r26(10), r26(4), r26(4), r26(11), r26(11), r26(11), r26(4), r26(4), r26(12), r26(12), r26(12), r26(4), r26(13) | |
| PHI r25(4), r25(0), r25(3), r25(3), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6) | |
| PHI r24(5), r24(0), r24(4), r24(4), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(6), r24(6), r24(6), r24(5), r24(5), r24(5), r24(7), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5) | |
| PHI r23(4), r23(0), r23(3), r23(3), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(5), r23(5), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4) | |
| PHI r22(4), r22(0), r22(3), r22(3), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6) | |
| PHI r21(4), r21(0), r21(3), r21(3), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6) | |
| PHI r20(4), r20(0), r20(3), r20(3), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6) | |
| PHI r19(4), r19(0), r19(3), r19(3), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(5), r19(6), r19(6), r19(6), r19(6), r19(6), r19(7), r19(8), r19(8), r19(8), r19(7), r19(9), r19(9), r19(9), r19(9), r19(9), r19(10), r19(10), r19(10), r19(10), r19(10), r19(11), r19(12), r19(12), r19(12), r19(11), r19(13), r19(14), r19(14), r19(14), r19(13), r19(15), r19(16), r19(16), r19(16), r19(15), r19(17), r19(18), r19(18), r19(18), r19(17), r19(19), r19(20), r19(20), r19(20), r19(19), r19(21), r19(22), r19(22), r19(22), r19(21), r19(23), r19(24), r19(24), r19(24), r19(23), r19(23) | |
| PHI r18(5), r18(0), r18(4), r18(4), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6) | |
| PHI r17(4), r17(0), r17(3), r17(3), r17(4), r17(4), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5) | |
| PHI r16(5), r16(0), r16(4), r16(4), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6) | |
| PHI r15(6), r15(0), r15(5), r15(5), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6) | |
| PHI r14(5), r14(0), r14(4), r14(4), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5) | |
| PHI r13(6), r13(0), r13(5), r13(5), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6) | |
| PHI r12(5), r12(0), r12(4), r12(4), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5) | |
| PHI r11(5), r11(0), r11(4), r11(4), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5) | |
| PHI r10(13), r10(0), r10(12), r10(12), r10(13), r10(13), r10(13), r10(13), r10(13), r10(14), r10(14), r10(14), r10(14), r10(15), r10(15), r10(15), r10(16), r10(16), r10(17), r10(17), r10(17), r10(18), r10(18), r10(19), r10(19), r10(19), r10(20), r10(20), r10(21), r10(21), r10(21), r10(22), r10(22), r10(23), r10(23), r10(23), r10(24), r10(24), r10(25), r10(25), r10(25), r10(26), r10(26), r10(27), r10(27), r10(27), r10(28), r10(28), r10(29), r10(29), r10(29), r10(30), r10(30), r10(31), r10(31), r10(31), r10(32), r10(32), r10(33), r10(33), r10(33), r10(34), r10(34), r10(35), r10(35), r10(35), r10(37), r10(37) | |
| PHI r9(9), r9(0), r9(8), r9(8), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(10), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9) | |
| PHI r8(9), r8(0), r8(8), r8(8), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(10), r8(10), r8(10), r8(9), r8(9), r8(9), r8(11), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9) | |
| PHI r7(7), r7(0), r7(6), r7(6), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7) | |
| PHI r6(13), r6(0), r6(12), r6(12), r6(13), r6(13), r6(14), r6(14), r6(14), r6(14), r6(14), r6(17), r6(17), r6(17), r6(18), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17) | |
| PHI r5(14), r5(0), r5(13), r5(13), r5(16), r5(16), r5(16), r5(17), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18) | |
| PHI r4(13), r4(0), r4(12), r4(12), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13) | |
| PHI r3(13), r3(0), r3(12), r3(12), r3(13), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(15), r3(15), r3(15), r3(14), r3(14), r3(16), r3(16), r3(16), r3(14), r3(14), r3(17), r3(17), r3(17), r3(14), r3(14), r3(18), r3(18), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14) | |
| PHI r2(6), r2(0), r2(5), r2(5), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6) | |
| PHI r1(6), r1(0), r1(5), r1(5), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6) | |
| PHI r0(6), r0(0), r0(5), r0(5), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6) | |
| [Annotation: FH Goto (0)] | |
| [Annotation: INS Deopt OSR (idx 3 -> pc 400); line 1504] | |
| osrpoint | |
| shift_o r5(15), r15(6) | |
| set r16(6), r5(15) | |
| [Annotation: INS Deopt One (idx 4 -> pc 418; line 1505)] | |
| [Annotation: Logged (bytecode offset 412)] | |
| decont r5(16), r16(6) | |
| Successors: 25, 24, 22, 111 | |
| Predecessors: 0, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 38, 39, 41, 42, 43, 45, 46, 48, 49, 50, 52, 53, 55, 56, 57, 59, 60, 62, 63, 64, 66, 67, 69, 70, 71, 73, 74, 76, 77, 78, 80, 81, 83, 84, 85, 87, 88, 90, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, 106, 108, 109 | |
| Dominance children: 25 | |
| BB 25 (0x7f844403a330): | |
| line: 1505 (pc 418) | |
| Instructions: | |
| smrt_strify r3(14), r5(16) | |
| Successors: 26, 24, 22, 111 | |
| Predecessors: 24 | |
| Dominance children: 26 | |
| BB 26 (0x7f844403a390): | |
| line: 1505 (pc 424) | |
| Instructions: | |
| set r17(5), r3(14) | |
| [Annotation: INS Deopt One (idx 5 -> pc 436; line 1505)] | |
| [Annotation: Logged (bytecode offset 430)] | |
| decont r6(14), r1(6) | |
| Successors: 27, 24, 22, 111 | |
| Predecessors: 25 | |
| Dominance children: 27 | |
| BB 27 (0x7f844403a3f0): | |
| line: 1505 (pc 436) | |
| Instructions: | |
| findmeth r5(17), r6(14), lits(symbol) | |
| Successors: 28, 24, 22, 111 | |
| Predecessors: 26 | |
| Dominance children: 28 | |
| BB 28 (0x7f844403a450): | |
| line: 1505 (pc 446) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 6 -> pc 446; line 1505)] | |
| prepargs callsite(0x7f844c1156a0, 2 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| [Annotation: INS Deopt All (idx 8 -> pc 468; line 1505)] | |
| [Annotation: INS Deopt One (idx 7 -> pc 468; line 1505)] | |
| [Annotation: Logged (bytecode offset 462)] | |
| invoke_o r5(18), r5(17) | |
| Successors: 29, 24, 22, 111 | |
| Predecessors: 27 | |
| Dominance children: 29 | |
| BB 29 (0x7f844403a4b0): | |
| line: 1505 (pc 468) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 9 -> pc 474; line 1505)] | |
| [Annotation: Logged (bytecode offset 468)] | |
| decont r10(14), r5(18) | |
| Successors: 30, 24, 22, 111 | |
| Predecessors: 28 | |
| Dominance children: 30 | |
| BB 30 (0x7f844403a510): | |
| line: 1505 (pc 474) | |
| Instructions: | |
| if_o r10(14), BB(110) | |
| Successors: 110, 31, 24, 22, 111 | |
| Predecessors: 29 | |
| Dominance children: 31, 110 | |
| BB 31 (0x7f844403a570): | |
| line: 1507 (pc 482) | |
| Instructions: | |
| lexprimspec r19(5), r13(6), r17(5) | |
| hllboxtype_i r6(15) | |
| box_i r6(16), r19(5), r6(15) | |
| set r18(6), r6(16) | |
| [Annotation: INS Deopt One (idx 10 -> pc 514; line 1507)] | |
| [Annotation: Logged (bytecode offset 508)] | |
| decont r6(17), r18(6) | |
| Successors: 32, 24, 22, 111 | |
| Predecessors: 30 | |
| Dominance children: 32 | |
| BB 32 (0x7f844403a5d0): | |
| line: 1507 (pc 514) | |
| Instructions: | |
| smrt_intify r19(6), r6(17) | |
| Successors: 33, 24, 22, 111 | |
| Predecessors: 31 | |
| Dominance children: 33 | |
| BB 33 (0x7f844403a630): | |
| line: 1507 (pc 520) | |
| Instructions: | |
| const_i64_16 r20(5), liti16(0) | |
| eq_i r20(6), r19(6), r20(5) | |
| unless_i r20(6), BB(38) | |
| Successors: 38, 34 | |
| Predecessors: 32 | |
| Dominance children: 34, 38 | |
| BB 34 (0x7f844403a690): | |
| line: 1510 (pc 542) | |
| Instructions: | |
| const_s r3(15), lits(lexical) | |
| [Annotation: INS Deopt One (idx 11 -> pc 556; line 1510)] | |
| [Annotation: Logged (bytecode offset 550)] | |
| decont r10(15), r1(6) | |
| Successors: 35, 24, 22, 111 | |
| Predecessors: 33 | |
| Dominance children: 35 | |
| BB 35 (0x7f844403a6f0): | |
| line: 1510 (pc 556) | |
| Instructions: | |
| findmeth r6(18), r10(15), lits(symbol) | |
| Successors: 36, 24, 22, 111 | |
| Predecessors: 34 | |
| Dominance children: 36 | |
| BB 36 (0x7f844403a750): | |
| line: 1510 (pc 566) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 12 -> pc 566; line 1510)] | |
| prepargs callsite(0x560f5bb9f6d0, 6 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(15) | |
| argconst_s liti16(4), lits(lazy_value_from) | |
| arg_o liti16(5), r13(6) | |
| [Annotation: INS Deopt All (idx 14 -> pc 616; line 1510)] | |
| [Annotation: INS Deopt One (idx 13 -> pc 616; line 1510)] | |
| [Annotation: Logged (bytecode offset 610)] | |
| invoke_o r6(19), r6(18) | |
| Successors: 37, 24, 22, 111 | |
| Predecessors: 35 | |
| Dominance children: 37 | |
| BB 37 (0x7f844403a7b0): | |
| line: 1510 (pc 616) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 36 | |
| Dominance children: | |
| BB 38 (0x7f844403a810): | |
| line: 1510 (pc 622) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 15 -> pc 628; line 1510)] | |
| [Annotation: Logged (bytecode offset 622)] | |
| decont r10(16), r18(6) | |
| Successors: 39, 24, 22, 111 | |
| Predecessors: 33 | |
| Dominance children: 39 | |
| BB 39 (0x7f844403a870): | |
| line: 1510 (pc 628) | |
| Instructions: | |
| smrt_intify r19(7), r10(16) | |
| Successors: 40, 24, 22, 111 | |
| Predecessors: 38 | |
| Dominance children: 40 | |
| BB 40 (0x7f844403a8d0): | |
| line: 1510 (pc 634) | |
| Instructions: | |
| const_i64_16 r21(5), liti16(1) | |
| eq_i r21(6), r19(7), r21(5) | |
| unless_i r21(6), BB(45) | |
| Successors: 45, 41 | |
| Predecessors: 39 | |
| Dominance children: 41, 45 | |
| BB 41 (0x7f844403a930): | |
| line: 1514 (pc 656) | |
| Instructions: | |
| const_s r3(16), lits(lexical) | |
| atkey_i r19(8), r13(6), r17(5) | |
| wval r10(17), liti16(1), liti16(2) (P6int: int) | |
| [Annotation: INS Deopt One (idx 16 -> pc 686; line 1514)] | |
| [Annotation: Logged (bytecode offset 680)] | |
| decont r8(10), r1(6) | |
| Successors: 42, 24, 22, 111 | |
| Predecessors: 40 | |
| Dominance children: 42 | |
| BB 42 (0x7f844403a990): | |
| line: 1514 (pc 686) | |
| Instructions: | |
| findmeth r9(10), r8(10), lits(symbol) | |
| Successors: 43, 24, 22, 111 | |
| Predecessors: 41 | |
| Dominance children: 43 | |
| BB 43 (0x7f844403a9f0): | |
| line: 1514 (pc 696) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 17 -> pc 696; line 1514)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(16) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(8) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(17) | |
| [Annotation: INS Deopt All (idx 19 -> pc 760; line 1514)] | |
| [Annotation: INS Deopt One (idx 18 -> pc 760; line 1514)] | |
| [Annotation: Logged (bytecode offset 754)] | |
| invoke_o r9(11), r9(10) | |
| Successors: 44, 24, 22, 111 | |
| Predecessors: 42 | |
| Dominance children: 44 | |
| BB 44 (0x7f844403aa50): | |
| line: 1514 (pc 760) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 43 | |
| Dominance children: | |
| BB 45 (0x7f844403aab0): | |
| line: 1514 (pc 766) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 20 -> pc 772; line 1514)] | |
| [Annotation: Logged (bytecode offset 766)] | |
| decont r10(18), r18(6) | |
| Successors: 46, 24, 22, 111 | |
| Predecessors: 40 | |
| Dominance children: 46 | |
| BB 46 (0x7f844403ab10): | |
| line: 1514 (pc 772) | |
| Instructions: | |
| smrt_intify r19(9), r10(18) | |
| Successors: 47, 24, 22, 111 | |
| Predecessors: 45 | |
| Dominance children: 47 | |
| BB 47 (0x7f844403ab70): | |
| line: 1514 (pc 778) | |
| Instructions: | |
| const_i64_16 r22(5), liti16(2) | |
| eq_i r22(6), r19(9), r22(5) | |
| unless_i r22(6), BB(52) | |
| Successors: 52, 48 | |
| Predecessors: 46 | |
| Dominance children: 48, 52 | |
| BB 48 (0x7f844403abd0): | |
| line: 1518 (pc 800) | |
| Instructions: | |
| const_s r3(17), lits(lexical) | |
| atkey_n r23(5), r13(6), r17(5) | |
| wval r10(19), liti16(1), liti16(12) (P6num: num) | |
| [Annotation: INS Deopt One (idx 21 -> pc 830; line 1518)] | |
| [Annotation: Logged (bytecode offset 824)] | |
| decont r24(6), r1(6) | |
| Successors: 49, 24, 22, 111 | |
| Predecessors: 47 | |
| Dominance children: 49 | |
| BB 49 (0x7f844403ac30): | |
| line: 1518 (pc 830) | |
| Instructions: | |
| findmeth r8(11), r24(6), lits(symbol) | |
| Successors: 50, 24, 22, 111 | |
| Predecessors: 48 | |
| Dominance children: 50 | |
| BB 50 (0x7f844403ac90): | |
| line: 1518 (pc 840) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 22 -> pc 840; line 1518)] | |
| prepargs callsite(0x560f5bb9f7f0, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(17) | |
| argconst_s liti16(4), lits(value) | |
| arg_n liti16(5), r23(5) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(19) | |
| [Annotation: INS Deopt All (idx 24 -> pc 904; line 1518)] | |
| [Annotation: INS Deopt One (idx 23 -> pc 904; line 1518)] | |
| [Annotation: Logged (bytecode offset 898)] | |
| invoke_o r8(12), r8(11) | |
| Successors: 51, 24, 22, 111 | |
| Predecessors: 49 | |
| Dominance children: 51 | |
| BB 51 (0x7f844403acf0): | |
| line: 1518 (pc 904) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 50 | |
| Dominance children: | |
| BB 52 (0x7f844403ad50): | |
| line: 1518 (pc 910) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 25 -> pc 916; line 1518)] | |
| [Annotation: Logged (bytecode offset 910)] | |
| decont r10(20), r18(6) | |
| Successors: 53, 24, 22, 111 | |
| Predecessors: 47 | |
| Dominance children: 53 | |
| BB 53 (0x7f844403adb0): | |
| line: 1518 (pc 916) | |
| Instructions: | |
| smrt_intify r19(10), r10(20) | |
| Successors: 54, 24, 22, 111 | |
| Predecessors: 52 | |
| Dominance children: 54 | |
| BB 54 (0x7f844403ae10): | |
| line: 1518 (pc 922) | |
| Instructions: | |
| const_i64_16 r25(5), liti16(3) | |
| eq_i r25(6), r19(10), r25(5) | |
| unless_i r25(6), BB(59) | |
| Successors: 59, 55 | |
| Predecessors: 53 | |
| Dominance children: 55, 59 | |
| BB 55 (0x7f844403ae70): | |
| line: 1522 (pc 944) | |
| Instructions: | |
| const_s r3(18), lits(lexical) | |
| atkey_s r26(5), r13(6), r17(5) | |
| wval r10(21), liti16(1), liti16(15) (P6str: str) | |
| [Annotation: INS Deopt One (idx 26 -> pc 974; line 1522)] | |
| [Annotation: Logged (bytecode offset 968)] | |
| decont r27(6), r1(6) | |
| Successors: 56, 24, 22, 111 | |
| Predecessors: 54 | |
| Dominance children: 56 | |
| BB 56 (0x7f844403aed0): | |
| line: 1522 (pc 974) | |
| Instructions: | |
| findmeth r24(7), r27(6), lits(symbol) | |
| Successors: 57, 24, 22, 111 | |
| Predecessors: 55 | |
| Dominance children: 57 | |
| BB 57 (0x7f844403af30): | |
| line: 1522 (pc 984) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 27 -> pc 984; line 1522)] | |
| prepargs callsite(0x560f5bb9f860, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(18) | |
| argconst_s liti16(4), lits(value) | |
| arg_s liti16(5), r26(5) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(21) | |
| [Annotation: INS Deopt All (idx 29 -> pc 1048; line 1522)] | |
| [Annotation: INS Deopt One (idx 28 -> pc 1048; line 1522)] | |
| [Annotation: Logged (bytecode offset 1042)] | |
| invoke_o r24(8), r24(7) | |
| Successors: 58, 24, 22, 111 | |
| Predecessors: 56 | |
| Dominance children: 58 | |
| BB 58 (0x7f844403af90): | |
| line: 1522 (pc 1048) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 57 | |
| Dominance children: | |
| BB 59 (0x7f844403aff0): | |
| line: 1522 (pc 1054) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 30 -> pc 1060; line 1522)] | |
| [Annotation: Logged (bytecode offset 1054)] | |
| decont r10(22), r18(6) | |
| Successors: 60, 24, 22, 111 | |
| Predecessors: 54 | |
| Dominance children: 60 | |
| BB 60 (0x7f844403b050): | |
| line: 1522 (pc 1060) | |
| Instructions: | |
| smrt_intify r19(11), r10(22) | |
| Successors: 61, 24, 22, 111 | |
| Predecessors: 59 | |
| Dominance children: 61 | |
| BB 61 (0x7f844403b0b0): | |
| line: 1522 (pc 1066) | |
| Instructions: | |
| const_i64_16 r28(5), liti16(4) | |
| eq_i r28(6), r19(11), r28(5) | |
| unless_i r28(6), BB(66) | |
| Successors: 66, 62 | |
| Predecessors: 60 | |
| Dominance children: 62, 66 | |
| BB 62 (0x7f844403b110): | |
| line: 1526 (pc 1088) | |
| Instructions: | |
| const_s r26(6), lits(lexical) | |
| atkey_i r19(12), r13(6), r17(5) | |
| wval r10(23), liti16(1), liti16(6) (P6int: int8) | |
| [Annotation: INS Deopt One (idx 31 -> pc 1118; line 1526)] | |
| [Annotation: Logged (bytecode offset 1112)] | |
| decont r29(6), r1(6) | |
| Successors: 63, 24, 22, 111 | |
| Predecessors: 61 | |
| Dominance children: 63 | |
| BB 63 (0x7f844403b170): | |
| line: 1526 (pc 1118) | |
| Instructions: | |
| findmeth r27(7), r29(6), lits(symbol) | |
| Successors: 64, 24, 22, 111 | |
| Predecessors: 62 | |
| Dominance children: 64 | |
| BB 64 (0x7f844403b1d0): | |
| line: 1526 (pc 1128) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 32 -> pc 1128; line 1526)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(6) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(12) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(23) | |
| [Annotation: INS Deopt All (idx 34 -> pc 1192; line 1526)] | |
| [Annotation: INS Deopt One (idx 33 -> pc 1192; line 1526)] | |
| [Annotation: Logged (bytecode offset 1186)] | |
| invoke_o r27(8), r27(7) | |
| Successors: 65, 24, 22, 111 | |
| Predecessors: 63 | |
| Dominance children: 65 | |
| BB 65 (0x7f844403b230): | |
| line: 1526 (pc 1192) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 64 | |
| Dominance children: | |
| BB 66 (0x7f844403b290): | |
| line: 1526 (pc 1198) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 35 -> pc 1204; line 1526)] | |
| [Annotation: Logged (bytecode offset 1198)] | |
| decont r10(24), r18(6) | |
| Successors: 67, 24, 22, 111 | |
| Predecessors: 61 | |
| Dominance children: 67 | |
| BB 67 (0x7f844403b2f0): | |
| line: 1526 (pc 1204) | |
| Instructions: | |
| smrt_intify r19(13), r10(24) | |
| Successors: 68, 24, 22, 111 | |
| Predecessors: 66 | |
| Dominance children: 68 | |
| BB 68 (0x7f844403b350): | |
| line: 1526 (pc 1210) | |
| Instructions: | |
| const_i64_16 r30(5), liti16(5) | |
| eq_i r30(6), r19(13), r30(5) | |
| unless_i r30(6), BB(73) | |
| Successors: 73, 69 | |
| Predecessors: 67 | |
| Dominance children: 69, 73 | |
| BB 69 (0x7f844403b3b0): | |
| line: 1530 (pc 1232) | |
| Instructions: | |
| const_s r26(7), lits(lexical) | |
| atkey_i r19(14), r13(6), r17(5) | |
| wval r10(25), liti16(1), liti16(5) (P6int: int16) | |
| [Annotation: INS Deopt One (idx 36 -> pc 1262; line 1530)] | |
| [Annotation: Logged (bytecode offset 1256)] | |
| decont r31(6), r1(6) | |
| Successors: 70, 24, 22, 111 | |
| Predecessors: 68 | |
| Dominance children: 70 | |
| BB 70 (0x7f844403b410): | |
| line: 1530 (pc 1262) | |
| Instructions: | |
| findmeth r29(7), r31(6), lits(symbol) | |
| Successors: 71, 24, 22, 111 | |
| Predecessors: 69 | |
| Dominance children: 71 | |
| BB 71 (0x7f844403b470): | |
| line: 1530 (pc 1272) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 37 -> pc 1272; line 1530)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(7) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(14) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(25) | |
| [Annotation: INS Deopt All (idx 39 -> pc 1336; line 1530)] | |
| [Annotation: INS Deopt One (idx 38 -> pc 1336; line 1530)] | |
| [Annotation: Logged (bytecode offset 1330)] | |
| invoke_o r29(8), r29(7) | |
| Successors: 72, 24, 22, 111 | |
| Predecessors: 70 | |
| Dominance children: 72 | |
| BB 72 (0x7f844403b4d0): | |
| line: 1530 (pc 1336) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 71 | |
| Dominance children: | |
| BB 73 (0x7f844403b530): | |
| line: 1530 (pc 1342) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 40 -> pc 1348; line 1530)] | |
| [Annotation: Logged (bytecode offset 1342)] | |
| decont r10(26), r18(6) | |
| Successors: 74, 24, 22, 111 | |
| Predecessors: 68 | |
| Dominance children: 74 | |
| BB 74 (0x7f844403b590): | |
| line: 1530 (pc 1348) | |
| Instructions: | |
| smrt_intify r19(15), r10(26) | |
| Successors: 75, 24, 22, 111 | |
| Predecessors: 73 | |
| Dominance children: 75 | |
| BB 75 (0x7f844403b5f0): | |
| line: 1530 (pc 1354) | |
| Instructions: | |
| const_i64_16 r32(5), liti16(6) | |
| eq_i r32(6), r19(15), r32(5) | |
| unless_i r32(6), BB(80) | |
| Successors: 80, 76 | |
| Predecessors: 74 | |
| Dominance children: 76, 80 | |
| BB 76 (0x7f844403b650): | |
| line: 1534 (pc 1376) | |
| Instructions: | |
| const_s r26(8), lits(lexical) | |
| atkey_i r19(16), r13(6), r17(5) | |
| wval r10(27), liti16(1), liti16(4) (P6int: int32) | |
| [Annotation: INS Deopt One (idx 41 -> pc 1406; line 1534)] | |
| [Annotation: Logged (bytecode offset 1400)] | |
| decont r33(6), r1(6) | |
| Successors: 77, 24, 22, 111 | |
| Predecessors: 75 | |
| Dominance children: 77 | |
| BB 77 (0x7f844403b6b0): | |
| line: 1534 (pc 1406) | |
| Instructions: | |
| findmeth r31(7), r33(6), lits(symbol) | |
| Successors: 78, 24, 22, 111 | |
| Predecessors: 76 | |
| Dominance children: 78 | |
| BB 78 (0x7f844403b710): | |
| line: 1534 (pc 1416) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 42 -> pc 1416; line 1534)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(8) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(16) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(27) | |
| [Annotation: INS Deopt All (idx 44 -> pc 1480; line 1534)] | |
| [Annotation: INS Deopt One (idx 43 -> pc 1480; line 1534)] | |
| [Annotation: Logged (bytecode offset 1474)] | |
| invoke_o r31(8), r31(7) | |
| Successors: 79, 24, 22, 111 | |
| Predecessors: 77 | |
| Dominance children: 79 | |
| BB 79 (0x7f844403b770): | |
| line: 1534 (pc 1480) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 78 | |
| Dominance children: | |
| BB 80 (0x7f844403b7d0): | |
| line: 1534 (pc 1486) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 45 -> pc 1492; line 1534)] | |
| [Annotation: Logged (bytecode offset 1486)] | |
| decont r10(28), r18(6) | |
| Successors: 81, 24, 22, 111 | |
| Predecessors: 75 | |
| Dominance children: 81 | |
| BB 81 (0x7f844403b830): | |
| line: 1534 (pc 1492) | |
| Instructions: | |
| smrt_intify r19(17), r10(28) | |
| Successors: 82, 24, 22, 111 | |
| Predecessors: 80 | |
| Dominance children: 82 | |
| BB 82 (0x7f844403b890): | |
| line: 1534 (pc 1498) | |
| Instructions: | |
| const_i64_16 r34(5), liti16(7) | |
| eq_i r34(6), r19(17), r34(5) | |
| unless_i r34(6), BB(87) | |
| Successors: 87, 83 | |
| Predecessors: 81 | |
| Dominance children: 83, 87 | |
| BB 83 (0x7f844403b8f0): | |
| line: 1538 (pc 1520) | |
| Instructions: | |
| const_s r26(9), lits(lexical) | |
| atkey_u r35(5), r13(6), r17(5) | |
| coerce_ui r19(18), r35(5) | |
| wval r10(29), liti16(1), liti16(11) (P6int: uint8) | |
| [Annotation: INS Deopt One (idx 46 -> pc 1556; line 1538)] | |
| [Annotation: Logged (bytecode offset 1550)] | |
| decont r36(6), r1(6) | |
| Successors: 84, 24, 22, 111 | |
| Predecessors: 82 | |
| Dominance children: 84 | |
| BB 84 (0x7f844403b950): | |
| line: 1538 (pc 1556) | |
| Instructions: | |
| findmeth r33(7), r36(6), lits(symbol) | |
| Successors: 85, 24, 22, 111 | |
| Predecessors: 83 | |
| Dominance children: 85 | |
| BB 85 (0x7f844403b9b0): | |
| line: 1538 (pc 1566) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 47 -> pc 1566; line 1538)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(9) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(18) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(29) | |
| [Annotation: INS Deopt All (idx 49 -> pc 1630; line 1538)] | |
| [Annotation: INS Deopt One (idx 48 -> pc 1630; line 1538)] | |
| [Annotation: Logged (bytecode offset 1624)] | |
| invoke_o r33(8), r33(7) | |
| Successors: 86, 24, 22, 111 | |
| Predecessors: 84 | |
| Dominance children: 86 | |
| BB 86 (0x7f844403ba10): | |
| line: 1538 (pc 1630) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 85 | |
| Dominance children: | |
| BB 87 (0x7f844403ba70): | |
| line: 1538 (pc 1636) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 50 -> pc 1642; line 1538)] | |
| [Annotation: Logged (bytecode offset 1636)] | |
| decont r10(30), r18(6) | |
| Successors: 88, 24, 22, 111 | |
| Predecessors: 82 | |
| Dominance children: 88 | |
| BB 88 (0x7f844403bad0): | |
| line: 1538 (pc 1642) | |
| Instructions: | |
| smrt_intify r19(19), r10(30) | |
| Successors: 89, 24, 22, 111 | |
| Predecessors: 87 | |
| Dominance children: 89 | |
| BB 89 (0x7f844403bb30): | |
| line: 1538 (pc 1648) | |
| Instructions: | |
| const_i64_16 r37(5), liti16(8) | |
| eq_i r37(6), r19(19), r37(5) | |
| unless_i r37(6), BB(94) | |
| Successors: 94, 90 | |
| Predecessors: 88 | |
| Dominance children: 90, 94 | |
| BB 90 (0x7f844403bb90): | |
| line: 1542 (pc 1670) | |
| Instructions: | |
| const_s r26(10), lits(lexical) | |
| atkey_u r35(6), r13(6), r17(5) | |
| coerce_ui r19(20), r35(6) | |
| wval r10(31), liti16(1), liti16(10) (P6int: uint16) | |
| [Annotation: INS Deopt One (idx 51 -> pc 1706; line 1542)] | |
| [Annotation: Logged (bytecode offset 1700)] | |
| decont r38(6), r1(6) | |
| Successors: 91, 24, 22, 111 | |
| Predecessors: 89 | |
| Dominance children: 91 | |
| BB 91 (0x7f844403bbf0): | |
| line: 1542 (pc 1706) | |
| Instructions: | |
| findmeth r36(7), r38(6), lits(symbol) | |
| Successors: 92, 24, 22, 111 | |
| Predecessors: 90 | |
| Dominance children: 92 | |
| BB 92 (0x7f844403bc50): | |
| line: 1542 (pc 1716) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 52 -> pc 1716; line 1542)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(10) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(20) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(31) | |
| [Annotation: INS Deopt All (idx 54 -> pc 1780; line 1542)] | |
| [Annotation: INS Deopt One (idx 53 -> pc 1780; line 1542)] | |
| [Annotation: Logged (bytecode offset 1774)] | |
| invoke_o r36(8), r36(7) | |
| Successors: 93, 24, 22, 111 | |
| Predecessors: 91 | |
| Dominance children: 93 | |
| BB 93 (0x7f844403bcb0): | |
| line: 1542 (pc 1780) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 92 | |
| Dominance children: | |
| BB 94 (0x7f844403bd10): | |
| line: 1542 (pc 1786) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 55 -> pc 1792; line 1542)] | |
| [Annotation: Logged (bytecode offset 1786)] | |
| decont r10(32), r18(6) | |
| Successors: 95, 24, 22, 111 | |
| Predecessors: 89 | |
| Dominance children: 95 | |
| BB 95 (0x7f844403bd70): | |
| line: 1542 (pc 1792) | |
| Instructions: | |
| smrt_intify r19(21), r10(32) | |
| Successors: 96, 24, 22, 111 | |
| Predecessors: 94 | |
| Dominance children: 96 | |
| BB 96 (0x7f844403bdd0): | |
| line: 1542 (pc 1798) | |
| Instructions: | |
| const_i64_16 r39(5), liti16(9) | |
| eq_i r39(6), r19(21), r39(5) | |
| unless_i r39(6), BB(101) | |
| Successors: 101, 97 | |
| Predecessors: 95 | |
| Dominance children: 97, 101 | |
| BB 97 (0x7f844403be30): | |
| line: 1546 (pc 1820) | |
| Instructions: | |
| const_s r26(11), lits(lexical) | |
| atkey_u r35(7), r13(6), r17(5) | |
| coerce_ui r19(22), r35(7) | |
| wval r10(33), liti16(1), liti16(9) (P6int: uint32) | |
| [Annotation: INS Deopt One (idx 56 -> pc 1856; line 1546)] | |
| [Annotation: Logged (bytecode offset 1850)] | |
| decont r40(6), r1(6) | |
| Successors: 98, 24, 22, 111 | |
| Predecessors: 96 | |
| Dominance children: 98 | |
| BB 98 (0x7f844403be90): | |
| line: 1546 (pc 1856) | |
| Instructions: | |
| findmeth r38(7), r40(6), lits(symbol) | |
| Successors: 99, 24, 22, 111 | |
| Predecessors: 97 | |
| Dominance children: 99 | |
| BB 99 (0x7f844403bef0): | |
| line: 1546 (pc 1866) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 57 -> pc 1866; line 1546)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(11) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(22) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(33) | |
| [Annotation: INS Deopt All (idx 59 -> pc 1930; line 1546)] | |
| [Annotation: INS Deopt One (idx 58 -> pc 1930; line 1546)] | |
| [Annotation: Logged (bytecode offset 1924)] | |
| invoke_o r38(8), r38(7) | |
| Successors: 100, 24, 22, 111 | |
| Predecessors: 98 | |
| Dominance children: 100 | |
| BB 100 (0x7f844403bf50): | |
| line: 1546 (pc 1930) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 99 | |
| Dominance children: | |
| BB 101 (0x7f844403bfb0): | |
| line: 1546 (pc 1936) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 60 -> pc 1942; line 1546)] | |
| [Annotation: Logged (bytecode offset 1936)] | |
| decont r10(34), r18(6) | |
| Successors: 102, 24, 22, 111 | |
| Predecessors: 96 | |
| Dominance children: 102 | |
| BB 102 (0x7f844403c010): | |
| line: 1546 (pc 1942) | |
| Instructions: | |
| smrt_intify r19(23), r10(34) | |
| Successors: 103, 24, 22, 111 | |
| Predecessors: 101 | |
| Dominance children: 103 | |
| BB 103 (0x7f844403c070): | |
| line: 1546 (pc 1948) | |
| Instructions: | |
| const_i64_16 r41(5), liti16(10) | |
| eq_i r41(6), r19(23), r41(5) | |
| unless_i r41(6), BB(108) | |
| Successors: 108, 104 | |
| Predecessors: 102 | |
| Dominance children: 104, 108 | |
| BB 104 (0x7f844403c0d0): | |
| line: 1550 (pc 1970) | |
| Instructions: | |
| const_s r26(12), lits(lexical) | |
| atkey_u r35(8), r13(6), r17(5) | |
| coerce_ui r19(24), r35(8) | |
| wval r10(35), liti16(1), liti16(8) (P6int: uint64) | |
| [Annotation: INS Deopt One (idx 61 -> pc 2006; line 1550)] | |
| [Annotation: Logged (bytecode offset 2000)] | |
| decont r42(8), r1(6) | |
| Successors: 105, 24, 22, 111 | |
| Predecessors: 103 | |
| Dominance children: 105 | |
| BB 105 (0x7f8444041160): | |
| line: 1550 (pc 2006) | |
| Instructions: | |
| findmeth r40(7), r42(8), lits(symbol) | |
| Successors: 106, 24, 22, 111 | |
| Predecessors: 104 | |
| Dominance children: 106 | |
| BB 106 (0x7f84440411c0): | |
| line: 1550 (pc 2016) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 62 -> pc 2016; line 1550)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(12) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(24) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(35) | |
| [Annotation: INS Deopt All (idx 64 -> pc 2080; line 1550)] | |
| [Annotation: INS Deopt One (idx 63 -> pc 2080; line 1550)] | |
| [Annotation: Logged (bytecode offset 2074)] | |
| invoke_o r40(8), r40(7) | |
| Successors: 107, 24, 22, 111 | |
| Predecessors: 105 | |
| Dominance children: 107 | |
| BB 107 (0x7f8444041220): | |
| line: 1550 (pc 2080) | |
| Instructions: | |
| goto BB(110) | |
| Successors: 110 | |
| Predecessors: 106 | |
| Dominance children: | |
| BB 108 (0x7f8444041280): | |
| line: 1553 (pc 2086) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 65 -> pc 2094; line 1553)] | |
| [Annotation: Logged (bytecode offset 2086)] | |
| getlex_no r10(36), lits(&die) | |
| [Annotation: INS Deopt One (idx 66 -> pc 2100; line 1553)] | |
| [Annotation: Logged (bytecode offset 2094)] | |
| decont r10(37), r10(36) | |
| Successors: 109, 24, 22, 111 | |
| Predecessors: 103 | |
| Dominance children: 109 | |
| BB 109 (0x7f84440412e0): | |
| line: 1553 (pc 2100) | |
| Instructions: | |
| const_s r26(13), lits(Unhandled lexical type) | |
| [Annotation: INS Deopt One (idx 67 -> pc 2108; line 1553)] | |
| prepargs callsite(0x560f5b9ee530, 1 arg, 1 pos, nonflattening, interned) | |
| arg_s liti16(0), r26(13) | |
| [Annotation: INS Deopt All (idx 68 -> pc 2122; line 1553)] | |
| [Annotation: Logged (bytecode offset 2118)] | |
| invoke_v r10(37) | |
| Successors: 110, 24, 22, 111 | |
| Predecessors: 108 | |
| Dominance children: | |
| BB 110 (0x7f8444041340): | |
| line: 1553 (pc 2122) | |
| Instructions: | |
| PHI r42(9), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(7) | |
| PHI r41(7), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6) | |
| PHI r40(9), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(8), r40(5) | |
| PHI r39(7), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6) | |
| PHI r38(9), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(8), r38(5), r38(5) | |
| PHI r37(7), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6) | |
| PHI r36(9), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(8), r36(5), r36(5), r36(5) | |
| PHI r35(9), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(6), r35(7), r35(8), r35(4) | |
| PHI r34(7), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6) | |
| PHI r33(9), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(8), r33(5), r33(5), r33(5), r33(5) | |
| PHI r32(7), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6) | |
| PHI r31(9), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5) | |
| PHI r30(7), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6) | |
| PHI r29(9), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5) | |
| PHI r28(7), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6) | |
| PHI r27(9), r27(5), r27(5), r27(5), r27(5), r27(6), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5) | |
| PHI r26(14), r26(4), r26(4), r26(4), r26(4), r26(5), r26(6), r26(7), r26(8), r26(9), r26(10), r26(11), r26(12), r26(13) | |
| PHI r25(7), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6) | |
| PHI r24(9), r24(5), r24(5), r24(5), r24(6), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5) | |
| PHI r23(6), r23(4), r23(4), r23(4), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4) | |
| PHI r22(7), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6) | |
| PHI r21(7), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6) | |
| PHI r20(7), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6) | |
| PHI r19(25), r19(4), r19(6), r19(8), r19(9), r19(10), r19(12), r19(14), r19(16), r19(18), r19(20), r19(22), r19(24), r19(23) | |
| PHI r18(7), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6) | |
| PHI r10(38), r10(14), r10(15), r10(17), r10(19), r10(21), r10(23), r10(25), r10(27), r10(29), r10(31), r10(33), r10(35), r10(37) | |
| PHI r9(12), r9(9), r9(9), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9) | |
| PHI r8(13), r8(9), r8(9), r8(10), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9) | |
| PHI r6(20), r6(14), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17) | |
| PHI r3(19), r3(14), r3(15), r3(16), r3(17), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14) | |
| goto BB(22) | |
| Successors: 22 | |
| Predecessors: 30, 37, 44, 51, 58, 65, 72, 79, 86, 93, 100, 107, 109 | |
| Dominance children: | |
| BB 111 (0x7f84440413a0): | |
| line: 1553 (pc 2128) | |
| Instructions: | |
| PHI r42(10), r42(5), r42(6), r42(6), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(8), r42(8), r42(7), r42(7) | |
| PHI r41(8), r41(2), r41(3), r41(3), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6), r41(6), r41(6), r41(6) | |
| PHI r40(10), r40(3), r40(4), r40(4), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(6), r40(6), r40(5), r40(5), r40(5), r40(7), r40(8), r40(5), r40(5) | |
| PHI r39(8), r39(2), r39(3), r39(3), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6) | |
| PHI r38(10), r38(3), r38(4), r38(4), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(6), r38(6), r38(5), r38(5), r38(5), r38(7), r38(8), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5) | |
| PHI r37(8), r37(2), r37(3), r37(3), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6) | |
| PHI r36(10), r36(3), r36(4), r36(4), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(6), r36(6), r36(5), r36(5), r36(5), r36(7), r36(8), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5) | |
| PHI r35(10), r35(2), r35(3), r35(3), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(5), r35(5), r35(4), r35(4), r35(6), r35(6), r35(6), r35(4), r35(4), r35(7), r35(7), r35(7), r35(4), r35(4), r35(8), r35(8), r35(8), r35(4), r35(4) | |
| PHI r34(8), r34(2), r34(3), r34(3), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6) | |
| PHI r33(10), r33(3), r33(4), r33(4), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(6), r33(6), r33(5), r33(5), r33(5), r33(7), r33(8), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5) | |
| PHI r32(8), r32(2), r32(3), r32(3), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6) | |
| PHI r31(10), r31(3), r31(4), r31(4), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(6), r31(6), r31(5), r31(5), r31(5), r31(7), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5) | |
| PHI r30(8), r30(2), r30(3), r30(3), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6) | |
| PHI r29(10), r29(3), r29(4), r29(4), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(6), r29(6), r29(5), r29(5), r29(5), r29(7), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5) | |
| PHI r28(8), r28(2), r28(3), r28(3), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6) | |
| PHI r27(10), r27(3), r27(4), r27(4), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(6), r27(6), r27(6), r27(5), r27(5), r27(5), r27(7), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5) | |
| PHI r26(15), r26(2), r26(3), r26(3), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(5), r26(5), r26(5), r26(4), r26(4), r26(6), r26(6), r26(6), r26(4), r26(4), r26(7), r26(7), r26(7), r26(4), r26(4), r26(8), r26(8), r26(8), r26(4), r26(4), r26(9), r26(9), r26(9), r26(4), r26(4), r26(10), r26(10), r26(10), r26(4), r26(4), r26(11), r26(11), r26(11), r26(4), r26(4), r26(12), r26(12), r26(12), r26(4), r26(13) | |
| PHI r25(8), r25(2), r25(3), r25(3), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6) | |
| PHI r24(10), r24(3), r24(4), r24(4), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(6), r24(6), r24(6), r24(5), r24(5), r24(5), r24(7), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5) | |
| PHI r23(7), r23(2), r23(3), r23(3), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(5), r23(5), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4) | |
| PHI r22(8), r22(2), r22(3), r22(3), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6) | |
| PHI r21(8), r21(2), r21(3), r21(3), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6) | |
| PHI r20(8), r20(2), r20(3), r20(3), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6) | |
| PHI r19(26), r19(2), r19(3), r19(3), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(5), r19(6), r19(6), r19(6), r19(6), r19(6), r19(7), r19(8), r19(8), r19(8), r19(7), r19(9), r19(9), r19(9), r19(9), r19(9), r19(10), r19(10), r19(10), r19(10), r19(10), r19(11), r19(12), r19(12), r19(12), r19(11), r19(13), r19(14), r19(14), r19(14), r19(13), r19(15), r19(16), r19(16), r19(16), r19(15), r19(17), r19(18), r19(18), r19(18), r19(17), r19(19), r19(20), r19(20), r19(20), r19(19), r19(21), r19(22), r19(22), r19(22), r19(21), r19(23), r19(24), r19(24), r19(24), r19(23), r19(23) | |
| PHI r18(8), r18(3), r18(4), r18(4), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6) | |
| PHI r17(6), r17(2), r17(3), r17(3), r17(4), r17(4), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5) | |
| PHI r16(7), r16(3), r16(4), r16(4), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6) | |
| PHI r15(7), r15(3), r15(5), r15(5), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6) | |
| PHI r14(6), r14(3), r14(4), r14(4), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5) | |
| PHI r13(7), r13(4), r13(5), r13(5), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6) | |
| PHI r12(6), r12(3), r12(4), r12(4), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5) | |
| PHI r11(6), r11(3), r11(4), r11(4), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5) | |
| PHI r10(39), r10(11), r10(12), r10(12), r10(13), r10(13), r10(13), r10(13), r10(13), r10(14), r10(14), r10(14), r10(14), r10(15), r10(15), r10(15), r10(16), r10(16), r10(17), r10(17), r10(17), r10(18), r10(18), r10(19), r10(19), r10(19), r10(20), r10(20), r10(21), r10(21), r10(21), r10(22), r10(22), r10(23), r10(23), r10(23), r10(24), r10(24), r10(25), r10(25), r10(25), r10(26), r10(26), r10(27), r10(27), r10(27), r10(28), r10(28), r10(29), r10(29), r10(29), r10(30), r10(30), r10(31), r10(31), r10(31), r10(32), r10(32), r10(33), r10(33), r10(33), r10(34), r10(34), r10(35), r10(35), r10(35), r10(37), r10(37) | |
| PHI r9(13), r9(7), r9(8), r9(8), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(10), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9) | |
| PHI r8(14), r8(7), r8(8), r8(8), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(10), r8(10), r8(10), r8(9), r8(9), r8(9), r8(11), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9) | |
| PHI r7(8), r7(5), r7(6), r7(6), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7) | |
| PHI r6(21), r6(11), r6(12), r6(12), r6(13), r6(13), r6(14), r6(14), r6(14), r6(14), r6(14), r6(17), r6(17), r6(17), r6(18), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17) | |
| PHI r5(19), r5(10), r5(13), r5(13), r5(16), r5(16), r5(16), r5(17), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18), r5(18) | |
| PHI r4(14), r4(11), r4(12), r4(12), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13) | |
| PHI r3(20), r3(11), r3(12), r3(12), r3(13), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(15), r3(15), r3(15), r3(14), r3(14), r3(16), r3(16), r3(16), r3(14), r3(14), r3(17), r3(17), r3(17), r3(14), r3(14), r3(18), r3(18), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14) | |
| PHI r2(7), r2(4), r2(5), r2(5), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6) | |
| PHI r1(7), r1(4), r1(5), r1(5), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6) | |
| PHI r0(7), r0(4), r0(5), r0(5), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6) | |
| [Annotation: FH Goto (2)] | |
| [Annotation: FH End (2)] | |
| [Annotation: FH End (1)] | |
| [Annotation: FH End (0)] | |
| ctxouter r5(20), r2(7) | |
| set r2(8), r5(20) | |
| null r5(21) | |
| goto BB(19) | |
| Successors: 19 | |
| Predecessors: 20, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 38, 39, 41, 42, 43, 45, 46, 48, 49, 50, 52, 53, 55, 56, 57, 59, 60, 62, 63, 64, 66, 67, 69, 70, 71, 73, 74, 76, 77, 78, 80, 81, 83, 84, 85, 87, 88, 90, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, 106, 108, 109 | |
| Dominance children: | |
| BB 112 (0x7f8444041400): | |
| line: 1553 (pc 2150) | |
| Instructions: | |
| set r10(10), r4(10) | |
| Successors: 113 | |
| Predecessors: 19 | |
| Dominance children: | |
| BB 113 (0x7f8444041460): | |
| line: 1553 (pc 2156) | |
| Instructions: | |
| PHI r42(11), r42(3), r42(4) | |
| PHI r41(9), r41(0), r41(1) | |
| PHI r40(11), r40(1), r40(2) | |
| PHI r39(9), r39(0), r39(1) | |
| PHI r38(11), r38(1), r38(2) | |
| PHI r37(9), r37(0), r37(1) | |
| PHI r36(11), r36(1), r36(2) | |
| PHI r35(11), r35(0), r35(1) | |
| PHI r34(9), r34(0), r34(1) | |
| PHI r33(11), r33(1), r33(2) | |
| PHI r32(9), r32(0), r32(1) | |
| PHI r31(11), r31(1), r31(2) | |
| PHI r30(9), r30(0), r30(1) | |
| PHI r29(11), r29(1), r29(2) | |
| PHI r28(9), r28(0), r28(1) | |
| PHI r27(11), r27(1), r27(2) | |
| PHI r26(16), r26(0), r26(1) | |
| PHI r25(9), r25(0), r25(1) | |
| PHI r24(11), r24(1), r24(2) | |
| PHI r23(8), r23(0), r23(1) | |
| PHI r22(9), r22(0), r22(1) | |
| PHI r21(9), r21(0), r21(1) | |
| PHI r20(9), r20(0), r20(1) | |
| PHI r19(27), r19(0), r19(1) | |
| PHI r18(9), r18(1), r18(2) | |
| PHI r17(7), r17(0), r17(1) | |
| PHI r16(8), r16(1), r16(2) | |
| PHI r15(8), r15(1), r15(2) | |
| PHI r14(7), r14(0), r14(1) | |
| PHI r13(8), r13(1), r13(2) | |
| PHI r12(7), r12(0), r12(2) | |
| PHI r11(7), r11(1), r11(2) | |
| PHI r10(40), r10(8), r10(10) | |
| PHI r9(14), r9(5), r9(6) | |
| PHI r8(15), r8(5), r8(6) | |
| PHI r7(9), r7(3), r7(4) | |
| PHI r6(22), r6(9), r6(10) | |
| PHI r5(22), r5(7), r5(8) | |
| PHI r4(15), r4(8), r4(10) | |
| PHI r3(21), r3(9), r3(10) | |
| PHI r2(9), r2(2), r2(3) | |
| PHI r1(8), r1(2), r1(3) | |
| PHI r0(8), r0(2), r0(3) | |
| return_o r10(40) | |
| Successors: | |
| Predecessors: 17, 112 | |
| Dominance children: | |
| Frame size: 3376 bytes | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(56)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="TC"]; | |
| n_0010 [label="ADDR(16)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8)"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="ADDR(1760)"]; | |
| n_0018 -> n_0014; | |
| n_0022 [label="LOAD(8):obj"]; | |
| n_0022 -> n_0018; | |
| n_0593 [label="STORE(8)"]; | |
| n_0593 -> n_0004; | |
| n_0593 -> n_0022; | |
| n_0026 [label="LOCAL"]; | |
| n_0028 [label="ADDR(64)"]; | |
| n_0028 -> n_0026; | |
| n_0032 [label="TC"]; | |
| n_0034 [label="ADDR(16)"]; | |
| n_0034 -> n_0032; | |
| n_0038 [label="LOAD(8)"]; | |
| n_0038 -> n_0034; | |
| n_0042 [label="ADDR(1760)"]; | |
| n_0042 -> n_0038; | |
| n_0046 [label="LOAD(8):obj"]; | |
| n_0046 -> n_0042; | |
| n_0598 [label="STORE(8)"]; | |
| n_0598 -> n_0028; | |
| n_0598 -> n_0046; | |
| n_0050 [label="LOCAL"]; | |
| n_0052 [label="ADDR(72)"]; | |
| n_0052 -> n_0050; | |
| n_0056 [label="TC"]; | |
| n_0058 [label="ADDR(16)"]; | |
| n_0058 -> n_0056; | |
| n_0062 [label="LOAD(8)"]; | |
| n_0062 -> n_0058; | |
| n_0066 [label="ADDR(1760)"]; | |
| n_0066 -> n_0062; | |
| n_0070 [label="LOAD(8):obj"]; | |
| n_0070 -> n_0066; | |
| n_0603 [label="STORE(8)"]; | |
| n_0603 -> n_0052; | |
| n_0603 -> n_0070; | |
| n_0074 [label="LOCAL"]; | |
| n_0076 [label="ADDR(120)"]; | |
| n_0076 -> n_0074; | |
| n_0080 [label="TC"]; | |
| n_0082 [label="ADDR(16)"]; | |
| n_0082 -> n_0080; | |
| n_0086 [label="LOAD(8)"]; | |
| n_0086 -> n_0082; | |
| n_0090 [label="ADDR(1760)"]; | |
| n_0090 -> n_0086; | |
| n_0094 [label="LOAD(8):obj"]; | |
| n_0094 -> n_0090; | |
| n_0608 [label="STORE(8)"]; | |
| n_0608 -> n_0076; | |
| n_0608 -> n_0094; | |
| n_0098 [label="LOCAL"]; | |
| n_0100 [label="ADDR(128)"]; | |
| n_0100 -> n_0098; | |
| n_0104 [label="TC"]; | |
| n_0106 [label="ADDR(16)"]; | |
| n_0106 -> n_0104; | |
| n_0110 [label="LOAD(8)"]; | |
| n_0110 -> n_0106; | |
| n_0114 [label="ADDR(1760)"]; | |
| n_0114 -> n_0110; | |
| n_0118 [label="LOAD(8):obj"]; | |
| n_0118 -> n_0114; | |
| n_0613 [label="STORE(8)"]; | |
| n_0613 -> n_0100; | |
| n_0613 -> n_0118; | |
| n_0122 [label="LOCAL"]; | |
| n_0124 [label="ADDR(144)"]; | |
| n_0124 -> n_0122; | |
| n_0128 [label="TC"]; | |
| n_0130 [label="ADDR(16)"]; | |
| n_0130 -> n_0128; | |
| n_0134 [label="LOAD(8)"]; | |
| n_0134 -> n_0130; | |
| n_0138 [label="ADDR(1760)"]; | |
| n_0138 -> n_0134; | |
| n_0142 [label="LOAD(8):obj"]; | |
| n_0142 -> n_0138; | |
| n_0618 [label="STORE(8)"]; | |
| n_0618 -> n_0124; | |
| n_0618 -> n_0142; | |
| n_0146 [label="LOCAL"]; | |
| n_0148 [label="ADDR(192)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="TC"]; | |
| n_0154 [label="ADDR(16)"]; | |
| n_0154 -> n_0152; | |
| n_0158 [label="LOAD(8)"]; | |
| n_0158 -> n_0154; | |
| n_0162 [label="ADDR(1760)"]; | |
| n_0162 -> n_0158; | |
| n_0166 [label="LOAD(8):obj"]; | |
| n_0166 -> n_0162; | |
| n_0623 [label="STORE(8)"]; | |
| n_0623 -> n_0148; | |
| n_0623 -> n_0166; | |
| n_0170 [label="LOCAL"]; | |
| n_0172 [label="ADDR(216)"]; | |
| n_0172 -> n_0170; | |
| n_0176 [label="TC"]; | |
| n_0178 [label="ADDR(16)"]; | |
| n_0178 -> n_0176; | |
| n_0182 [label="LOAD(8)"]; | |
| n_0182 -> n_0178; | |
| n_0186 [label="ADDR(1760)"]; | |
| n_0186 -> n_0182; | |
| n_0190 [label="LOAD(8):obj"]; | |
| n_0190 -> n_0186; | |
| n_0628 [label="STORE(8)"]; | |
| n_0628 -> n_0172; | |
| n_0628 -> n_0190; | |
| n_0194 [label="LOCAL"]; | |
| n_0196 [label="ADDR(232)"]; | |
| n_0196 -> n_0194; | |
| n_0200 [label="TC"]; | |
| n_0202 [label="ADDR(16)"]; | |
| n_0202 -> n_0200; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0210 [label="ADDR(1760)"]; | |
| n_0210 -> n_0206; | |
| n_0214 [label="LOAD(8):obj"]; | |
| n_0214 -> n_0210; | |
| n_0633 [label="STORE(8)"]; | |
| n_0633 -> n_0196; | |
| n_0633 -> n_0214; | |
| n_0218 [label="LOCAL"]; | |
| n_0220 [label="ADDR(248)"]; | |
| n_0220 -> n_0218; | |
| n_0224 [label="TC"]; | |
| n_0226 [label="ADDR(16)"]; | |
| n_0226 -> n_0224; | |
| n_0230 [label="LOAD(8)"]; | |
| n_0230 -> n_0226; | |
| n_0234 [label="ADDR(1760)"]; | |
| n_0234 -> n_0230; | |
| n_0238 [label="LOAD(8):obj"]; | |
| n_0238 -> n_0234; | |
| n_0638 [label="STORE(8)"]; | |
| n_0638 -> n_0220; | |
| n_0638 -> n_0238; | |
| n_0242 [label="LOCAL"]; | |
| n_0244 [label="ADDR(264)"]; | |
| n_0244 -> n_0242; | |
| n_0248 [label="TC"]; | |
| n_0250 [label="ADDR(16)"]; | |
| n_0250 -> n_0248; | |
| n_0254 [label="LOAD(8)"]; | |
| n_0254 -> n_0250; | |
| n_0258 [label="ADDR(1760)"]; | |
| n_0258 -> n_0254; | |
| n_0262 [label="LOAD(8):obj"]; | |
| n_0262 -> n_0258; | |
| n_0643 [label="STORE(8)"]; | |
| n_0643 -> n_0244; | |
| n_0643 -> n_0262; | |
| n_0266 [label="LOCAL"]; | |
| n_0268 [label="ADDR(288)"]; | |
| n_0268 -> n_0266; | |
| n_0272 [label="TC"]; | |
| n_0274 [label="ADDR(16)"]; | |
| n_0274 -> n_0272; | |
| n_0278 [label="LOAD(8)"]; | |
| n_0278 -> n_0274; | |
| n_0282 [label="ADDR(1760)"]; | |
| n_0282 -> n_0278; | |
| n_0286 [label="LOAD(8):obj"]; | |
| n_0286 -> n_0282; | |
| n_0648 [label="STORE(8)"]; | |
| n_0648 -> n_0268; | |
| n_0648 -> n_0286; | |
| n_0290 [label="LOCAL"]; | |
| n_0292 [label="ADDR(304)"]; | |
| n_0292 -> n_0290; | |
| n_0296 [label="TC"]; | |
| n_0298 [label="ADDR(16)"]; | |
| n_0298 -> n_0296; | |
| n_0302 [label="LOAD(8)"]; | |
| n_0302 -> n_0298; | |
| n_0306 [label="ADDR(1760)"]; | |
| n_0306 -> n_0302; | |
| n_0310 [label="LOAD(8):obj"]; | |
| n_0310 -> n_0306; | |
| n_0653 [label="STORE(8)"]; | |
| n_0653 -> n_0292; | |
| n_0653 -> n_0310; | |
| n_0314 [label="LOCAL"]; | |
| n_0316 [label="ADDR(320)"]; | |
| n_0316 -> n_0314; | |
| n_0320 [label="TC"]; | |
| n_0322 [label="ADDR(16)"]; | |
| n_0322 -> n_0320; | |
| n_0326 [label="LOAD(8)"]; | |
| n_0326 -> n_0322; | |
| n_0330 [label="ADDR(1760)"]; | |
| n_0330 -> n_0326; | |
| n_0334 [label="LOAD(8):obj"]; | |
| n_0334 -> n_0330; | |
| n_0658 [label="STORE(8)"]; | |
| n_0658 -> n_0316; | |
| n_0658 -> n_0334; | |
| n_0338 [label="LOCAL"]; | |
| n_0340 [label="ADDR(0)"]; | |
| n_0340 -> n_0338; | |
| n_0348 [label="TC"]; | |
| n_0350 [label="ADDR(432)"]; | |
| n_0350 -> n_0348; | |
| n_0354 [label="LOAD(8)"]; | |
| n_0354 -> n_0350; | |
| n_0358 [label="ADDR(96)"]; | |
| n_0358 -> n_0354; | |
| n_0362 [label="LOAD(8)"]; | |
| n_0362 -> n_0358; | |
| n_0344 [label="CONST(0, 2)"]; | |
| n_0366 [label="IDX(8)"]; | |
| n_0366 -> n_0362; | |
| n_0366 -> n_0344; | |
| n_0371 [label="LOAD(8):obj"]; | |
| n_0371 -> n_0366; | |
| n_0573 [label="STORE(8)"]; | |
| n_0573 -> n_0340; | |
| n_0573 -> n_0371; | |
| n_0375 [label="LOCAL"]; | |
| n_0377 [label="ADDR(8)"]; | |
| n_0377 -> n_0375; | |
| n_0385 [label="TC"]; | |
| n_0387 [label="ADDR(432)"]; | |
| n_0387 -> n_0385; | |
| n_0391 [label="LOAD(8)"]; | |
| n_0391 -> n_0387; | |
| n_0395 [label="ADDR(96)"]; | |
| n_0395 -> n_0391; | |
| n_0399 [label="LOAD(8)"]; | |
| n_0399 -> n_0395; | |
| n_0381 [label="CONST(1, 2)"]; | |
| n_0403 [label="IDX(8)"]; | |
| n_0403 -> n_0399; | |
| n_0403 -> n_0381; | |
| n_0408 [label="LOAD(8):obj"]; | |
| n_0408 -> n_0403; | |
| n_0578 [label="STORE(8)"]; | |
| n_0578 -> n_0377; | |
| n_0578 -> n_0408; | |
| n_0412 [label="LOCAL"]; | |
| n_0414 [label="ADDR(24)"]; | |
| n_0414 -> n_0412; | |
| n_0422 [label="CU"]; | |
| n_0424 [label="ADDR(104)"]; | |
| n_0424 -> n_0422; | |
| n_0428 [label="LOAD(8)"]; | |
| n_0428 -> n_0424; | |
| n_0418 [label="CONST(624, 4)"]; | |
| n_0432 [label="IDX(8)"]; | |
| n_0432 -> n_0428; | |
| n_0432 -> n_0418; | |
| n_0437 [label="LOAD(8)"]; | |
| n_0437 -> n_0432; | |
| n_0441 [label="DISCARD"]; | |
| n_0441 -> n_0437; | |
| n_0444 [label="NZ"]; | |
| n_0444 -> n_0437; | |
| n_0447 [label="CONST_PTR(0)"]; | |
| n_0450 [label="TC"]; | |
| n_0452 [label="CARG(0)"]; | |
| n_0452 -> n_0450; | |
| n_0456 [label="CARG(0)"]; | |
| n_0456 -> n_0422; | |
| n_0460 [label="CARG(1)"]; | |
| n_0460 -> n_0418; | |
| n_0464 [label="ARGLIST"]; | |
| n_0464 -> n_0452; | |
| n_0464 -> n_0456; | |
| n_0464 -> n_0460; | |
| n_0469 [label="CALL(8)"]; | |
| n_0469 -> n_0447; | |
| n_0469 -> n_0464; | |
| n_0474 [label="IF"]; | |
| n_0474 -> n_0444; | |
| n_0474 -> n_0437; | |
| n_0474 -> n_0469; | |
| n_0479 [label="DO:str"]; | |
| n_0479 -> n_0441; | |
| n_0479 -> n_0474; | |
| n_0583 [label="STORE(8)"]; | |
| n_0583 -> n_0414; | |
| n_0583 -> n_0479; | |
| n_0483 [label="LOCAL"]; | |
| n_0485 [label="ADDR(32)"]; | |
| n_0485 -> n_0483; | |
| n_0489 [label="CONST_PTR(1)"]; | |
| n_0492 [label="TC"]; | |
| n_0494 [label="CARG(0)"]; | |
| n_0494 -> n_0492; | |
| n_0498 [label="CARG(0)"]; | |
| n_0498 -> n_0479; | |
| n_0502 [label="TC"]; | |
| n_0504 [label="ADDR(432)"]; | |
| n_0504 -> n_0502; | |
| n_0508 [label="LOAD(8)"]; | |
| n_0508 -> n_0504; | |
| n_0512 [label="ADDR(56)"]; | |
| n_0512 -> n_0508; | |
| n_0516 [label="LOAD(8)"]; | |
| n_0516 -> n_0512; | |
| n_0520 [label="CARG(0)"]; | |
| n_0520 -> n_0516; | |
| n_0524 [label="ARGLIST"]; | |
| n_0524 -> n_0494; | |
| n_0524 -> n_0498; | |
| n_0524 -> n_0520; | |
| n_0529 [label="CALL(8):obj"]; | |
| n_0529 -> n_0489; | |
| n_0529 -> n_0524; | |
| n_0588 [label="STORE(8)"]; | |
| n_0588 -> n_0485; | |
| n_0588 -> n_0529; | |
| n_0537 [label="NZ:obj"]; | |
| n_0537 -> n_0529; | |
| n_0540 [label="TC"]; | |
| n_0542 [label="ADDR(16)"]; | |
| n_0542 -> n_0540; | |
| n_0546 [label="LOAD(8)"]; | |
| n_0546 -> n_0542; | |
| n_0550 [label="ADDR(1760)"]; | |
| n_0550 -> n_0546; | |
| n_0554 [label="LOAD(8)"]; | |
| n_0554 -> n_0550; | |
| n_0558 [label="NE:obj"]; | |
| n_0558 -> n_0529; | |
| n_0558 -> n_0554; | |
| n_0562 [label="ALL"]; | |
| n_0562 -> n_0537; | |
| n_0562 -> n_0558; | |
| n_0534 [label="LABEL(8)"]; | |
| n_0566 [label="BRANCH"]; | |
| n_0566 -> n_0534; | |
| n_0569 [label="WHEN"]; | |
| n_0569 -> n_0562; | |
| n_0569 -> n_0566; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-92) | |
| 0: (local) | |
| 1: (tc) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (store (addr reg $ofs) reg $size) | |
| 5: (local) | |
| 6: (tc) | |
| 7: (load (addr reg $ofs) $size) | |
| 8: (load (addr reg $ofs) $size) | |
| 9: (store (addr reg $ofs) reg $size) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (store (addr reg $ofs) reg $size) | |
| 15: (local) | |
| 16: (tc) | |
| 17: (load (addr reg $ofs) $size) | |
| 18: (load (addr reg $ofs) $size) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (tc) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (store (addr reg $ofs) reg $size) | |
| 25: (local) | |
| 26: (tc) | |
| 27: (load (addr reg $ofs) $size) | |
| 28: (load (addr reg $ofs) $size) | |
| 29: (store (addr reg $ofs) reg $size) | |
| 30: (local) | |
| 31: (tc) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (load (addr reg $ofs) $size) | |
| 34: (store (addr reg $ofs) reg $size) | |
| 35: (local) | |
| 36: (tc) | |
| 37: (load (addr reg $ofs) $size) | |
| 38: (load (addr reg $ofs) $size) | |
| 39: (store (addr reg $ofs) reg $size) | |
| 40: (local) | |
| 41: (tc) | |
| 42: (load (addr reg $ofs) $size) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (store (addr reg $ofs) reg $size) | |
| 45: (local) | |
| 46: (tc) | |
| 47: (load (addr reg $ofs) $size) | |
| 48: (load (addr reg $ofs) $size) | |
| 49: (store (addr reg $ofs) reg $size) | |
| 50: (local) | |
| 51: (tc) | |
| 52: (load (addr reg $ofs) $size) | |
| 53: (load (addr reg $ofs) $size) | |
| 54: (store (addr reg $ofs) reg $size) | |
| 55: (local) | |
| 56: (tc) | |
| 57: (load (addr reg $ofs) $size) | |
| 58: (load (addr reg $ofs) $size) | |
| 59: (store (addr reg $ofs) reg $size) | |
| 60: (local) | |
| 61: (tc) | |
| 62: (load (addr reg $ofs) $size) | |
| 63: (load (addr reg $ofs) $size) | |
| 64: (store (addr reg $ofs) reg $size) | |
| 65: (local) | |
| 66: (tc) | |
| 67: (load (addr reg $ofs) $size) | |
| 68: (load (addr reg $ofs) $size) | |
| 69: (store (addr reg $ofs) reg $size) | |
| 70: (local) | |
| 71: (tc) | |
| 72: (load (addr reg $ofs) $size) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (const $val $size) | |
| 75: (load (idx reg reg $scale) $size) | |
| 76: (store (addr reg $ofs) reg $size) | |
| 77: (local) | |
| 78: (tc) | |
| 79: (load (addr reg $ofs) $size) | |
| 80: (load (addr reg $ofs) $size) | |
| 81: (const $val $size) | |
| 82: (load (idx reg reg $scale) $size) | |
| 83: (store (addr reg $ofs) reg $size) | |
| 84: (local) | |
| 85: (cu) | |
| 86: (load (addr reg $ofs) $size) | |
| 87: (const $val $size) | |
| 88: (load (idx reg reg $scale) $size) | |
| 89: (discard reg) | |
| 90: (nz (load (idx reg reg $scl) $size)) | |
| 91: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [92-93) | |
| 92: (branch :after) | |
| -> { 3 } | |
| Block{2} [93-100) | |
| 93: (label :fail) | |
| 94: (tc) | |
| 95: (carg reg) | |
| 96: (carg reg) | |
| 97: (carg reg) | |
| 98: (arglist c_arg) | |
| 99: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [100-117) | |
| 100: (branch :after) | |
| 101: (if flag reg) | |
| 102: (do void reg) | |
| 103: (store (addr reg $ofs) reg $size) | |
| 104: (local) | |
| 105: (tc) | |
| 106: (carg reg) | |
| 107: (carg reg) | |
| 108: (tc) | |
| 109: (load (addr reg $ofs) $size) | |
| 110: (load (addr reg $ofs) $size) | |
| 111: (carg reg) | |
| 112: (arglist c_arg) | |
| 113: (call (const_ptr $ptr) c_args $size) | |
| 114: (store (addr reg $ofs) reg $size) | |
| 115: (nz reg) | |
| 116: (conditional-branch :fail) | |
| -> { 4, 6 } | |
| Block{4} [117-122) | |
| 117: (tc) | |
| 118: (load (addr reg $ofs) $size) | |
| 119: (load (addr reg $ofs) $size) | |
| 120: (ne reg reg) | |
| 121: (conditional-branch :fail) | |
| -> { 5, 6 } | |
| Block{5} [122-124) | |
| 122: (all flag) | |
| 123: (branch (label $name)) | |
| -> { 6 } | |
| Block{6} [124-126) | |
| 124: (label :fail) | |
| 125: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0016 [label="CONST_PTR(0)"]; | |
| n_0019 [label="TC"]; | |
| n_0021 [label="CARG(0)"]; | |
| n_0021 -> n_0019; | |
| n_0025 [label="CU"]; | |
| n_0027 [label="CARG(0)"]; | |
| n_0027 -> n_0025; | |
| n_0008 [label="CONST(0, 2)"]; | |
| n_0031 [label="CARG(1)"]; | |
| n_0031 -> n_0008; | |
| n_0012 [label="CONST(0, 2)"]; | |
| n_0035 [label="CARG(1)"]; | |
| n_0035 -> n_0012; | |
| n_0039 [label="ARGLIST"]; | |
| n_0039 -> n_0021; | |
| n_0039 -> n_0027; | |
| n_0039 -> n_0031; | |
| n_0039 -> n_0035; | |
| n_0045 [label="CALL(8):obj"]; | |
| n_0045 -> n_0016; | |
| n_0045 -> n_0039; | |
| n_0050 [label="LOCAL"]; | |
| n_0052 [label="ADDR(56)"]; | |
| n_0052 -> n_0050; | |
| n_0056 [label="ADDR(16)"]; | |
| n_0056 -> n_0045; | |
| n_0060 [label="LOAD(8)"]; | |
| n_0060 -> n_0056; | |
| n_0064 [label="ADDR(128)"]; | |
| n_0064 -> n_0060; | |
| n_0068 [label="LOAD(8)"]; | |
| n_0068 -> n_0064; | |
| n_0072 [label="DISCARD"]; | |
| n_0072 -> n_0068; | |
| n_0075 [label="NZ"]; | |
| n_0075 -> n_0068; | |
| n_0078 [label="TC"]; | |
| n_0080 [label="ADDR(16)"]; | |
| n_0080 -> n_0078; | |
| n_0084 [label="LOAD(8)"]; | |
| n_0084 -> n_0080; | |
| n_0088 [label="ADDR(1760)"]; | |
| n_0088 -> n_0084; | |
| n_0092 [label="LOAD(8)"]; | |
| n_0092 -> n_0088; | |
| n_0096 [label="IF"]; | |
| n_0096 -> n_0075; | |
| n_0096 -> n_0068; | |
| n_0096 -> n_0092; | |
| n_0101 [label="DO:obj"]; | |
| n_0101 -> n_0072; | |
| n_0101 -> n_0096; | |
| n_0366 [label="STORE(8)"]; | |
| n_0366 -> n_0052; | |
| n_0366 -> n_0101; | |
| n_0105 [label="LOCAL"]; | |
| n_0107 [label="ADDR(24)"]; | |
| n_0107 -> n_0105; | |
| n_0115 [label="CU"]; | |
| n_0117 [label="ADDR(104)"]; | |
| n_0117 -> n_0115; | |
| n_0121 [label="LOAD(8)"]; | |
| n_0121 -> n_0117; | |
| n_0111 [label="CONST(625, 4)"]; | |
| n_0125 [label="IDX(8)"]; | |
| n_0125 -> n_0121; | |
| n_0125 -> n_0111; | |
| n_0130 [label="LOAD(8)"]; | |
| n_0130 -> n_0125; | |
| n_0134 [label="DISCARD"]; | |
| n_0134 -> n_0130; | |
| n_0137 [label="NZ"]; | |
| n_0137 -> n_0130; | |
| n_0140 [label="CONST_PTR(1)"]; | |
| n_0143 [label="TC"]; | |
| n_0145 [label="CARG(0)"]; | |
| n_0145 -> n_0143; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0115; | |
| n_0153 [label="CARG(1)"]; | |
| n_0153 -> n_0111; | |
| n_0157 [label="ARGLIST"]; | |
| n_0157 -> n_0145; | |
| n_0157 -> n_0149; | |
| n_0157 -> n_0153; | |
| n_0162 [label="CALL(8)"]; | |
| n_0162 -> n_0140; | |
| n_0162 -> n_0157; | |
| n_0167 [label="IF"]; | |
| n_0167 -> n_0137; | |
| n_0167 -> n_0130; | |
| n_0167 -> n_0162; | |
| n_0172 [label="DO:str"]; | |
| n_0172 -> n_0134; | |
| n_0172 -> n_0167; | |
| n_0361 [label="STORE(8)"]; | |
| n_0361 -> n_0107; | |
| n_0361 -> n_0172; | |
| n_0182 [label="ADDR(12)"]; | |
| n_0182 -> n_0101; | |
| n_0186 [label="LOAD(2)"]; | |
| n_0186 -> n_0182; | |
| n_0190 [label="CONST(1, 2)"]; | |
| n_0194 [label="AND"]; | |
| n_0194 -> n_0186; | |
| n_0194 -> n_0190; | |
| n_0198 [label="NZ"]; | |
| n_0198 -> n_0194; | |
| n_0176 [label="LOCAL"]; | |
| n_0178 [label="ADDR(64)"]; | |
| n_0178 -> n_0176; | |
| n_0201 [label="TC"]; | |
| n_0203 [label="ADDR(16)"]; | |
| n_0203 -> n_0201; | |
| n_0207 [label="LOAD(8)"]; | |
| n_0207 -> n_0203; | |
| n_0211 [label="ADDR(1760)"]; | |
| n_0211 -> n_0207; | |
| n_0215 [label="LOAD(8)"]; | |
| n_0215 -> n_0211; | |
| n_0219 [label="STORE(8)"]; | |
| n_0219 -> n_0178; | |
| n_0219 -> n_0215; | |
| n_0224 [label="ADDR(16)"]; | |
| n_0224 -> n_0101; | |
| n_0228 [label="LOAD(8)"]; | |
| n_0228 -> n_0224; | |
| n_0232 [label="ADDR(16)"]; | |
| n_0232 -> n_0228; | |
| n_0236 [label="LOAD(8)"]; | |
| n_0236 -> n_0232; | |
| n_0240 [label="ADDR(288)"]; | |
| n_0240 -> n_0236; | |
| n_0244 [label="LOAD(8)"]; | |
| n_0244 -> n_0240; | |
| n_0248 [label="TC"]; | |
| n_0250 [label="CARG(0)"]; | |
| n_0250 -> n_0248; | |
| n_0254 [label="ADDR(16)"]; | |
| n_0254 -> n_0101; | |
| n_0258 [label="LOAD(8)"]; | |
| n_0258 -> n_0254; | |
| n_0262 [label="CARG(0)"]; | |
| n_0262 -> n_0258; | |
| n_0266 [label="CARG(0)"]; | |
| n_0266 -> n_0101; | |
| n_0270 [label="ADDR(24)"]; | |
| n_0270 -> n_0101; | |
| n_0274 [label="CARG(0)"]; | |
| n_0274 -> n_0270; | |
| n_0278 [label="CARG(0)"]; | |
| n_0278 -> n_0172; | |
| n_0282 [label="CARG(0)"]; | |
| n_0282 -> n_0178; | |
| n_0286 [label="CONST(8, 8)"]; | |
| n_0290 [label="CARG(1)"]; | |
| n_0290 -> n_0286; | |
| n_0294 [label="ARGLIST"]; | |
| n_0294 -> n_0250; | |
| n_0294 -> n_0262; | |
| n_0294 -> n_0266; | |
| n_0294 -> n_0274; | |
| n_0294 -> n_0278; | |
| n_0294 -> n_0282; | |
| n_0294 -> n_0290; | |
| n_0303 [label="CALLV"]; | |
| n_0303 -> n_0244; | |
| n_0303 -> n_0294; | |
| n_0307 [label="IFV"]; | |
| n_0307 -> n_0198; | |
| n_0307 -> n_0219; | |
| n_0307 -> n_0303; | |
| n_0312 [label="LOCAL"]; | |
| n_0314 [label="ADDR(64)"]; | |
| n_0314 -> n_0312; | |
| n_0318 [label="LOAD(8):obj"]; | |
| n_0318 -> n_0314; | |
| n_0325 [label="NZ:obj"]; | |
| n_0325 -> n_0318; | |
| n_0328 [label="TC"]; | |
| n_0330 [label="ADDR(16)"]; | |
| n_0330 -> n_0328; | |
| n_0334 [label="LOAD(8)"]; | |
| n_0334 -> n_0330; | |
| n_0338 [label="ADDR(1760)"]; | |
| n_0338 -> n_0334; | |
| n_0342 [label="LOAD(8)"]; | |
| n_0342 -> n_0338; | |
| n_0346 [label="NE:obj"]; | |
| n_0346 -> n_0318; | |
| n_0346 -> n_0342; | |
| n_0350 [label="ALL"]; | |
| n_0350 -> n_0325; | |
| n_0350 -> n_0346; | |
| n_0322 [label="LABEL(4)"]; | |
| n_0354 [label="BRANCH"]; | |
| n_0354 -> n_0322; | |
| n_0357 [label="WHEN"]; | |
| n_0357 -> n_0350; | |
| n_0357 -> n_0354; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-16) | |
| 0: (tc) | |
| 1: (carg reg) | |
| 2: (cu) | |
| 3: (carg reg) | |
| 4: (const $val $size) | |
| 5: (carg reg) | |
| 6: (const $val $size) | |
| 7: (carg reg) | |
| 8: (arglist c_arg) | |
| 9: (call (const_ptr $ptr) c_args $size) | |
| 10: (local) | |
| 11: (load (addr reg $ofs) $size) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (discard reg) | |
| 14: (nz (load (addr reg $ofs) $size)) | |
| 15: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [16-17) | |
| 16: (branch :after) | |
| -> { 3 } | |
| Block{2} [17-21) | |
| 17: (label :fail) | |
| 18: (tc) | |
| 19: (load (addr reg $ofs) $size) | |
| 20: (load (addr reg $ofs) $size) | |
| -> { 3 } | |
| Block{3} [21-33) | |
| 21: (branch :after) | |
| 22: (if flag reg) | |
| 23: (do void reg) | |
| 24: (store (addr reg $ofs) reg $size) | |
| 25: (local) | |
| 26: (cu) | |
| 27: (load (addr reg $ofs) $size) | |
| 28: (const $val $size) | |
| 29: (load (idx reg reg $scale) $size) | |
| 30: (discard reg) | |
| 31: (nz (load (idx reg reg $scl) $size)) | |
| 32: (conditional-branch: fail) | |
| -> { 4, 5 } | |
| Block{4} [33-34) | |
| 33: (branch :after) | |
| -> { 6 } | |
| Block{5} [34-41) | |
| 34: (label :fail) | |
| 35: (tc) | |
| 36: (carg reg) | |
| 37: (carg reg) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (call (const_ptr $ptr) c_args $size) | |
| -> { 6 } | |
| Block{6} [41-47) | |
| 41: (branch :after) | |
| 42: (if flag reg) | |
| 43: (do void reg) | |
| 44: (store (addr reg $ofs) reg $size) | |
| 45: (nz (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 46: (conditional-branch: fail) | |
| -> { 7, 8 } | |
| Block{7} [47-53) | |
| 47: (local) | |
| 48: (tc) | |
| 49: (load (addr reg $ofs) $size) | |
| 50: (load (addr reg $ofs) $size) | |
| 51: (store (addr reg $ofs) reg $size) | |
| 52: (branch :after) | |
| -> { 9 } | |
| Block{8} [53-70) | |
| 53: (label :fail) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (tc) | |
| 57: (carg reg) | |
| 58: (load (addr reg $ofs) $size) | |
| 59: (carg reg) | |
| 60: (carg reg) | |
| 61: (addr reg $ofs) | |
| 62: (carg reg) | |
| 63: (carg reg) | |
| 64: (addr reg $ofs) | |
| 65: (carg reg) | |
| 66: (const $val $size) | |
| 67: (carg reg) | |
| 68: (arglist c_arg) | |
| 69: (callv (load (addr reg $ofs) $sz) c_args) | |
| -> { 9 } | |
| Block{9} [70-75) | |
| 70: (branch :after) | |
| 71: (ifv flag void) | |
| 72: (local) | |
| 73: (nz (load (addr reg $ofs) $size)) | |
| 74: (conditional-branch :fail) | |
| -> { 10, 12 } | |
| Block{10} [75-81) | |
| 75: (load (addr reg $ofs) $size) | |
| 76: (tc) | |
| 77: (load (addr reg $ofs) $size) | |
| 78: (load (addr reg $ofs) $size) | |
| 79: (ne reg reg) | |
| 80: (conditional-branch :fail) | |
| -> { 11, 12 } | |
| Block{11} [81-83) | |
| 81: (all flag) | |
| 82: (branch (label $name)) | |
| -> { 12 } | |
| Block{12} [83-85) | |
| 83: (label :fail) | |
| 84: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(625, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0331 [label="STORE(8)"]; | |
| n_0331 -> n_0004; | |
| n_0331 -> n_0069; | |
| n_0087 [label="CONST_PTR(1)"]; | |
| n_0090 [label="TC"]; | |
| n_0092 [label="CARG(0)"]; | |
| n_0092 -> n_0090; | |
| n_0079 [label="CONST(32, 2)"]; | |
| n_0096 [label="CARG(1)"]; | |
| n_0096 -> n_0079; | |
| n_0100 [label="ARGLIST"]; | |
| n_0100 -> n_0092; | |
| n_0100 -> n_0096; | |
| n_0104 [label="CALL(8)"]; | |
| n_0104 -> n_0087; | |
| n_0104 -> n_0100; | |
| n_0109 [label="DISCARD"]; | |
| n_0109 -> n_0104; | |
| n_0112 [label="ADDR(16)"]; | |
| n_0112 -> n_0104; | |
| n_0116 [label="TC"]; | |
| n_0118 [label="ADDR(432)"]; | |
| n_0118 -> n_0116; | |
| n_0122 [label="LOAD(8)"]; | |
| n_0122 -> n_0118; | |
| n_0126 [label="ADDR(120)"]; | |
| n_0126 -> n_0122; | |
| n_0130 [label="LOAD(8)"]; | |
| n_0130 -> n_0126; | |
| n_0083 [label="CONST(0, 2)"]; | |
| n_0134 [label="IDX(8)"]; | |
| n_0134 -> n_0130; | |
| n_0134 -> n_0083; | |
| n_0139 [label="LOAD(8)"]; | |
| n_0139 -> n_0134; | |
| n_0143 [label="STORE(8)"]; | |
| n_0143 -> n_0112; | |
| n_0143 -> n_0139; | |
| n_0148 [label="ADDR(14)"]; | |
| n_0148 -> n_0104; | |
| n_0152 [label="STORE(2)"]; | |
| n_0152 -> n_0148; | |
| n_0152 -> n_0079; | |
| n_0157 [label="ADDR(8)"]; | |
| n_0157 -> n_0104; | |
| n_0161 [label="TC"]; | |
| n_0163 [label="ADDR(0)"]; | |
| n_0163 -> n_0161; | |
| n_0167 [label="LOAD(4)"]; | |
| n_0167 -> n_0163; | |
| n_0171 [label="STORE(4)"]; | |
| n_0171 -> n_0157; | |
| n_0171 -> n_0167; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(80)"]; | |
| n_0075 -> n_0073; | |
| n_0176 [label="STORE(8)"]; | |
| n_0176 -> n_0075; | |
| n_0176 -> n_0104; | |
| n_0181 [label="DOV"]; | |
| n_0181 -> n_0109; | |
| n_0181 -> n_0143; | |
| n_0181 -> n_0152; | |
| n_0181 -> n_0171; | |
| n_0181 -> n_0176; | |
| n_0188 [label="LOCAL"]; | |
| n_0190 [label="ADDR(56)"]; | |
| n_0190 -> n_0188; | |
| n_0194 [label="LOAD(8):obj"]; | |
| n_0194 -> n_0190; | |
| n_0208 [label="ADDR(16)"]; | |
| n_0208 -> n_0194; | |
| n_0212 [label="LOAD(8)"]; | |
| n_0212 -> n_0208; | |
| n_0216 [label="ADDR(16)"]; | |
| n_0216 -> n_0212; | |
| n_0220 [label="LOAD(8)"]; | |
| n_0220 -> n_0216; | |
| n_0224 [label="ADDR(296)"]; | |
| n_0224 -> n_0220; | |
| n_0228 [label="LOAD(8)"]; | |
| n_0228 -> n_0224; | |
| n_0232 [label="TC"]; | |
| n_0234 [label="CARG(0)"]; | |
| n_0234 -> n_0232; | |
| n_0238 [label="ADDR(16)"]; | |
| n_0238 -> n_0194; | |
| n_0242 [label="LOAD(8)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CARG(0)"]; | |
| n_0246 -> n_0242; | |
| n_0250 [label="CARG(0)"]; | |
| n_0250 -> n_0194; | |
| n_0254 [label="ADDR(24)"]; | |
| n_0254 -> n_0194; | |
| n_0258 [label="CARG(0)"]; | |
| n_0258 -> n_0254; | |
| n_0262 [label="CARG(0)"]; | |
| n_0262 -> n_0069; | |
| n_0198 [label="LOCAL"]; | |
| n_0200 [label="ADDR(80)"]; | |
| n_0200 -> n_0198; | |
| n_0204 [label="LOAD(8):obj"]; | |
| n_0204 -> n_0200; | |
| n_0266 [label="CARG(0)"]; | |
| n_0266 -> n_0204; | |
| n_0270 [label="CONST(8, 8)"]; | |
| n_0274 [label="CARG(1)"]; | |
| n_0274 -> n_0270; | |
| n_0278 [label="ARGLIST"]; | |
| n_0278 -> n_0234; | |
| n_0278 -> n_0246; | |
| n_0278 -> n_0250; | |
| n_0278 -> n_0258; | |
| n_0278 -> n_0262; | |
| n_0278 -> n_0266; | |
| n_0278 -> n_0274; | |
| n_0287 [label="CALLV"]; | |
| n_0287 -> n_0228; | |
| n_0287 -> n_0278; | |
| n_0291 [label="CONST_PTR(2)"]; | |
| n_0294 [label="TC"]; | |
| n_0296 [label="CARG(0)"]; | |
| n_0296 -> n_0294; | |
| n_0300 [label="CARG(0)"]; | |
| n_0300 -> n_0194; | |
| n_0304 [label="ARGLIST"]; | |
| n_0304 -> n_0296; | |
| n_0304 -> n_0300; | |
| n_0308 [label="CALLV"]; | |
| n_0308 -> n_0291; | |
| n_0308 -> n_0304; | |
| n_0312 [label="DOV"]; | |
| n_0312 -> n_0287; | |
| n_0312 -> n_0308; | |
| n_0316 [label="LOCAL"]; | |
| n_0318 [label="ADDR(72)"]; | |
| n_0318 -> n_0316; | |
| n_0322 [label="COPY:obj"]; | |
| n_0322 -> n_0204; | |
| n_0336 [label="STORE(8)"]; | |
| n_0336 -> n_0318; | |
| n_0336 -> n_0322; | |
| n_0325 [label="LABEL(5)"]; | |
| n_0328 [label="BRANCH"]; | |
| n_0328 -> n_0325; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-69) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (tc) | |
| 21: (carg reg) | |
| 22: (const $val $size) | |
| 23: (carg reg) | |
| 24: (arglist c_arg) | |
| 25: (call (const_ptr $ptr) c_args $size) | |
| 26: (discard reg) | |
| 27: (tc) | |
| 28: (load (addr reg $ofs) $size) | |
| 29: (load (addr reg $ofs) $size) | |
| 30: (const $val $size) | |
| 31: (load (idx reg reg $scale) $size) | |
| 32: (store (addr reg $ofs) reg $size) | |
| 33: (store (addr reg $ofs) reg $size) | |
| 34: (tc) | |
| 35: (load (addr reg $ofs) $size) | |
| 36: (store (addr reg $ofs) reg $size) | |
| 37: (local) | |
| 38: (store (addr reg $ofs) reg $size) | |
| 39: (dov void void) | |
| 40: (local) | |
| 41: (load (addr reg $ofs) $size) | |
| 42: (load (addr reg $ofs) $size) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (tc) | |
| 45: (carg reg) | |
| 46: (load (addr reg $ofs) $size) | |
| 47: (carg reg) | |
| 48: (carg reg) | |
| 49: (addr reg $ofs) | |
| 50: (carg reg) | |
| 51: (carg reg) | |
| 52: (local) | |
| 53: (load (addr reg $ofs) $size) | |
| 54: (carg reg) | |
| 55: (const $val $size) | |
| 56: (carg reg) | |
| 57: (arglist c_arg) | |
| 58: (callv (load (addr reg $ofs) $sz) c_args) | |
| 59: (tc) | |
| 60: (carg reg) | |
| 61: (carg reg) | |
| 62: (arglist c_arg) | |
| 63: (callv (const_ptr $ptr) c_args) | |
| 64: (dov void void) | |
| 65: (local) | |
| 66: (copy reg) | |
| 67: (store (addr reg $ofs) reg $size) | |
| 68: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(72)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(64)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(48)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(72)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0060 [label="STORE(8)"]; | |
| n_0060 -> n_0004; | |
| n_0060 -> n_0018; | |
| n_0024 [label="NZ:obj"]; | |
| n_0024 -> n_0014; | |
| n_0027 [label="TC"]; | |
| n_0029 [label="ADDR(16)"]; | |
| n_0029 -> n_0027; | |
| n_0033 [label="LOAD(8)"]; | |
| n_0033 -> n_0029; | |
| n_0037 [label="ADDR(1760)"]; | |
| n_0037 -> n_0033; | |
| n_0041 [label="LOAD(8)"]; | |
| n_0041 -> n_0037; | |
| n_0045 [label="NE:obj"]; | |
| n_0045 -> n_0014; | |
| n_0045 -> n_0041; | |
| n_0049 [label="ALL"]; | |
| n_0049 -> n_0024; | |
| n_0049 -> n_0045; | |
| n_0021 [label="LABEL(7)"]; | |
| n_0053 [label="BRANCH"]; | |
| n_0053 -> n_0021; | |
| n_0056 [label="WHEN"]; | |
| n_0056 -> n_0049; | |
| n_0056 -> n_0053; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-7) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| 5: (nz (load (addr reg $ofs) $size)) | |
| 6: (conditional-branch :fail) | |
| -> { 1, 3 } | |
| Block{1} [7-12) | |
| 7: (tc) | |
| 8: (load (addr reg $ofs) $size) | |
| 9: (load (addr reg $ofs) $size) | |
| 10: (ne reg reg) | |
| 11: (conditional-branch :fail) | |
| -> { 2, 3 } | |
| Block{2} [12-14) | |
| 12: (all flag) | |
| 13: (branch (label $name)) | |
| -> { 3 } | |
| Block{3} [14-16) | |
| 14: (label :fail) | |
| 15: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(626, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0105 [label="STORE(8)"]; | |
| n_0105 -> n_0004; | |
| n_0105 -> n_0069; | |
| n_0079 [label="CONST_PTR(1)"]; | |
| n_0082 [label="TC"]; | |
| n_0084 [label="CARG(0)"]; | |
| n_0084 -> n_0082; | |
| n_0088 [label="CARG(0)"]; | |
| n_0088 -> n_0069; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(48)"]; | |
| n_0075 -> n_0073; | |
| n_0092 [label="CARG(0)"]; | |
| n_0092 -> n_0075; | |
| n_0096 [label="ARGLIST"]; | |
| n_0096 -> n_0084; | |
| n_0096 -> n_0088; | |
| n_0096 -> n_0092; | |
| n_0101 [label="CALLV"]; | |
| n_0101 -> n_0079; | |
| n_0101 -> n_0096; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-28) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (tc) | |
| 21: (carg reg) | |
| 22: (carg reg) | |
| 23: (local) | |
| 24: (addr reg $ofs) | |
| 25: (carg reg) | |
| 26: (arglist c_arg) | |
| 27: (callv (const_ptr $ptr) c_args) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(40)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(48)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0027 [label="STORE(8)"]; | |
| n_0027 -> n_0004; | |
| n_0027 -> n_0018; | |
| n_0021 [label="LABEL(9)"]; | |
| n_0024 [label="BRANCH"]; | |
| n_0024 -> n_0021; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-6) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| 5: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(40)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(32)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(627, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0268 [label="STORE(8)"]; | |
| n_0268 -> n_0004; | |
| n_0268 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(40)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0089 [label="ADDR(12)"]; | |
| n_0089 -> n_0085; | |
| n_0093 [label="LOAD(2)"]; | |
| n_0093 -> n_0089; | |
| n_0097 [label="CONST(1, 2)"]; | |
| n_0101 [label="AND"]; | |
| n_0101 -> n_0093; | |
| n_0101 -> n_0097; | |
| n_0105 [label="NZ"]; | |
| n_0105 -> n_0101; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(40)"]; | |
| n_0075 -> n_0073; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="ADDR(16)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="LOAD(8)"]; | |
| n_0114 -> n_0110; | |
| n_0118 [label="ADDR(1760)"]; | |
| n_0118 -> n_0114; | |
| n_0122 [label="LOAD(8)"]; | |
| n_0122 -> n_0118; | |
| n_0126 [label="STORE(8)"]; | |
| n_0126 -> n_0075; | |
| n_0126 -> n_0122; | |
| n_0131 [label="ADDR(16)"]; | |
| n_0131 -> n_0085; | |
| n_0135 [label="LOAD(8)"]; | |
| n_0135 -> n_0131; | |
| n_0139 [label="ADDR(16)"]; | |
| n_0139 -> n_0135; | |
| n_0143 [label="LOAD(8)"]; | |
| n_0143 -> n_0139; | |
| n_0147 [label="ADDR(288)"]; | |
| n_0147 -> n_0143; | |
| n_0151 [label="LOAD(8)"]; | |
| n_0151 -> n_0147; | |
| n_0155 [label="TC"]; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0155; | |
| n_0161 [label="ADDR(16)"]; | |
| n_0161 -> n_0085; | |
| n_0165 [label="LOAD(8)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="CARG(0)"]; | |
| n_0169 -> n_0165; | |
| n_0173 [label="CARG(0)"]; | |
| n_0173 -> n_0085; | |
| n_0177 [label="ADDR(24)"]; | |
| n_0177 -> n_0085; | |
| n_0181 [label="CARG(0)"]; | |
| n_0181 -> n_0177; | |
| n_0185 [label="CARG(0)"]; | |
| n_0185 -> n_0069; | |
| n_0189 [label="CARG(0)"]; | |
| n_0189 -> n_0075; | |
| n_0193 [label="CONST(8, 8)"]; | |
| n_0197 [label="CARG(1)"]; | |
| n_0197 -> n_0193; | |
| n_0201 [label="ARGLIST"]; | |
| n_0201 -> n_0157; | |
| n_0201 -> n_0169; | |
| n_0201 -> n_0173; | |
| n_0201 -> n_0181; | |
| n_0201 -> n_0185; | |
| n_0201 -> n_0189; | |
| n_0201 -> n_0197; | |
| n_0210 [label="CALLV"]; | |
| n_0210 -> n_0151; | |
| n_0210 -> n_0201; | |
| n_0214 [label="IFV"]; | |
| n_0214 -> n_0105; | |
| n_0214 -> n_0126; | |
| n_0214 -> n_0210; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(40)"]; | |
| n_0221 -> n_0219; | |
| n_0225 [label="LOAD(8):obj"]; | |
| n_0225 -> n_0221; | |
| n_0232 [label="NZ:obj"]; | |
| n_0232 -> n_0225; | |
| n_0235 [label="TC"]; | |
| n_0237 [label="ADDR(16)"]; | |
| n_0237 -> n_0235; | |
| n_0241 [label="LOAD(8)"]; | |
| n_0241 -> n_0237; | |
| n_0245 [label="ADDR(1760)"]; | |
| n_0245 -> n_0241; | |
| n_0249 [label="LOAD(8)"]; | |
| n_0249 -> n_0245; | |
| n_0253 [label="NE:obj"]; | |
| n_0253 -> n_0225; | |
| n_0253 -> n_0249; | |
| n_0257 [label="ALL"]; | |
| n_0257 -> n_0232; | |
| n_0257 -> n_0253; | |
| n_0229 [label="LABEL(11)"]; | |
| n_0261 [label="BRANCH"]; | |
| n_0261 -> n_0229; | |
| n_0264 [label="WHEN"]; | |
| n_0264 -> n_0257; | |
| n_0264 -> n_0261; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-24) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (nz (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 23: (conditional-branch: fail) | |
| -> { 4, 5 } | |
| Block{4} [24-30) | |
| 24: (local) | |
| 25: (tc) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (load (addr reg $ofs) $size) | |
| 28: (store (addr reg $ofs) reg $size) | |
| 29: (branch :after) | |
| -> { 6 } | |
| Block{5} [30-47) | |
| 30: (label :fail) | |
| 31: (load (addr reg $ofs) $size) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (tc) | |
| 34: (carg reg) | |
| 35: (load (addr reg $ofs) $size) | |
| 36: (carg reg) | |
| 37: (carg reg) | |
| 38: (addr reg $ofs) | |
| 39: (carg reg) | |
| 40: (carg reg) | |
| 41: (addr reg $ofs) | |
| 42: (carg reg) | |
| 43: (const $val $size) | |
| 44: (carg reg) | |
| 45: (arglist c_arg) | |
| 46: (callv (load (addr reg $ofs) $sz) c_args) | |
| -> { 6 } | |
| Block{6} [47-52) | |
| 47: (branch :after) | |
| 48: (ifv flag void) | |
| 49: (local) | |
| 50: (nz (load (addr reg $ofs) $size)) | |
| 51: (conditional-branch :fail) | |
| -> { 7, 9 } | |
| Block{7} [52-58) | |
| 52: (load (addr reg $ofs) $size) | |
| 53: (tc) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (ne reg reg) | |
| 57: (conditional-branch :fail) | |
| -> { 8, 9 } | |
| Block{8} [58-60) | |
| 58: (all flag) | |
| 59: (branch (label $name)) | |
| -> { 9 } | |
| Block{9} [60-62) | |
| 60: (label :fail) | |
| 61: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(48)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="TC"]; | |
| n_0014 [label="ADDR(432)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0022 [label="ADDR(120)"]; | |
| n_0022 -> n_0018; | |
| n_0026 [label="LOAD(8)"]; | |
| n_0026 -> n_0022; | |
| n_0008 [label="CONST(1, 2)"]; | |
| n_0030 [label="IDX(8)"]; | |
| n_0030 -> n_0026; | |
| n_0030 -> n_0008; | |
| n_0035 [label="LOAD(8):obj"]; | |
| n_0035 -> n_0030; | |
| n_0045 [label="STORE(8)"]; | |
| n_0045 -> n_0004; | |
| n_0045 -> n_0035; | |
| n_0039 [label="LABEL(12)"]; | |
| n_0042 [label="BRANCH"]; | |
| n_0042 -> n_0039; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (tc) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (const $val $size) | |
| 5: (load (idx reg reg $scale) $size) | |
| 6: (store (addr reg $ofs) reg $size) | |
| 7: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(48)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(40)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(628, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0268 [label="STORE(8)"]; | |
| n_0268 -> n_0004; | |
| n_0268 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(48)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0089 [label="ADDR(12)"]; | |
| n_0089 -> n_0085; | |
| n_0093 [label="LOAD(2)"]; | |
| n_0093 -> n_0089; | |
| n_0097 [label="CONST(1, 2)"]; | |
| n_0101 [label="AND"]; | |
| n_0101 -> n_0093; | |
| n_0101 -> n_0097; | |
| n_0105 [label="NZ"]; | |
| n_0105 -> n_0101; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(48)"]; | |
| n_0075 -> n_0073; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="ADDR(16)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="LOAD(8)"]; | |
| n_0114 -> n_0110; | |
| n_0118 [label="ADDR(1760)"]; | |
| n_0118 -> n_0114; | |
| n_0122 [label="LOAD(8)"]; | |
| n_0122 -> n_0118; | |
| n_0126 [label="STORE(8)"]; | |
| n_0126 -> n_0075; | |
| n_0126 -> n_0122; | |
| n_0131 [label="ADDR(16)"]; | |
| n_0131 -> n_0085; | |
| n_0135 [label="LOAD(8)"]; | |
| n_0135 -> n_0131; | |
| n_0139 [label="ADDR(16)"]; | |
| n_0139 -> n_0135; | |
| n_0143 [label="LOAD(8)"]; | |
| n_0143 -> n_0139; | |
| n_0147 [label="ADDR(288)"]; | |
| n_0147 -> n_0143; | |
| n_0151 [label="LOAD(8)"]; | |
| n_0151 -> n_0147; | |
| n_0155 [label="TC"]; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0155; | |
| n_0161 [label="ADDR(16)"]; | |
| n_0161 -> n_0085; | |
| n_0165 [label="LOAD(8)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="CARG(0)"]; | |
| n_0169 -> n_0165; | |
| n_0173 [label="CARG(0)"]; | |
| n_0173 -> n_0085; | |
| n_0177 [label="ADDR(24)"]; | |
| n_0177 -> n_0085; | |
| n_0181 [label="CARG(0)"]; | |
| n_0181 -> n_0177; | |
| n_0185 [label="CARG(0)"]; | |
| n_0185 -> n_0069; | |
| n_0189 [label="CARG(0)"]; | |
| n_0189 -> n_0075; | |
| n_0193 [label="CONST(8, 8)"]; | |
| n_0197 [label="CARG(1)"]; | |
| n_0197 -> n_0193; | |
| n_0201 [label="ARGLIST"]; | |
| n_0201 -> n_0157; | |
| n_0201 -> n_0169; | |
| n_0201 -> n_0173; | |
| n_0201 -> n_0181; | |
| n_0201 -> n_0185; | |
| n_0201 -> n_0189; | |
| n_0201 -> n_0197; | |
| n_0210 [label="CALLV"]; | |
| n_0210 -> n_0151; | |
| n_0210 -> n_0201; | |
| n_0214 [label="IFV"]; | |
| n_0214 -> n_0105; | |
| n_0214 -> n_0126; | |
| n_0214 -> n_0210; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(48)"]; | |
| n_0221 -> n_0219; | |
| n_0225 [label="LOAD(8):obj"]; | |
| n_0225 -> n_0221; | |
| n_0232 [label="NZ:obj"]; | |
| n_0232 -> n_0225; | |
| n_0235 [label="TC"]; | |
| n_0237 [label="ADDR(16)"]; | |
| n_0237 -> n_0235; | |
| n_0241 [label="LOAD(8)"]; | |
| n_0241 -> n_0237; | |
| n_0245 [label="ADDR(1760)"]; | |
| n_0245 -> n_0241; | |
| n_0249 [label="LOAD(8)"]; | |
| n_0249 -> n_0245; | |
| n_0253 [label="NE:obj"]; | |
| n_0253 -> n_0225; | |
| n_0253 -> n_0249; | |
| n_0257 [label="ALL"]; | |
| n_0257 -> n_0232; | |
| n_0257 -> n_0253; | |
| n_0229 [label="LABEL(14)"]; | |
| n_0261 [label="BRANCH"]; | |
| n_0261 -> n_0229; | |
| n_0264 [label="WHEN"]; | |
| n_0264 -> n_0257; | |
| n_0264 -> n_0261; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-24) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (nz (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 23: (conditional-branch: fail) | |
| -> { 4, 5 } | |
| Block{4} [24-30) | |
| 24: (local) | |
| 25: (tc) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (load (addr reg $ofs) $size) | |
| 28: (store (addr reg $ofs) reg $size) | |
| 29: (branch :after) | |
| -> { 6 } | |
| Block{5} [30-47) | |
| 30: (label :fail) | |
| 31: (load (addr reg $ofs) $size) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (tc) | |
| 34: (carg reg) | |
| 35: (load (addr reg $ofs) $size) | |
| 36: (carg reg) | |
| 37: (carg reg) | |
| 38: (addr reg $ofs) | |
| 39: (carg reg) | |
| 40: (carg reg) | |
| 41: (addr reg $ofs) | |
| 42: (carg reg) | |
| 43: (const $val $size) | |
| 44: (carg reg) | |
| 45: (arglist c_arg) | |
| 46: (callv (load (addr reg $ofs) $sz) c_args) | |
| -> { 6 } | |
| Block{6} [47-52) | |
| 47: (branch :after) | |
| 48: (ifv flag void) | |
| 49: (local) | |
| 50: (nz (load (addr reg $ofs) $size)) | |
| 51: (conditional-branch :fail) | |
| -> { 7, 9 } | |
| Block{7} [52-58) | |
| 52: (load (addr reg $ofs) $size) | |
| 53: (tc) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (ne reg reg) | |
| 57: (conditional-branch :fail) | |
| -> { 8, 9 } | |
| Block{8} [58-60) | |
| 58: (all flag) | |
| 59: (branch (label $name)) | |
| -> { 9 } | |
| Block{9} [60-62) | |
| 60: (label :fail) | |
| 61: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(32)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="TC"]; | |
| n_0014 [label="ADDR(432)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0022 [label="ADDR(120)"]; | |
| n_0022 -> n_0018; | |
| n_0026 [label="LOAD(8)"]; | |
| n_0026 -> n_0022; | |
| n_0008 [label="CONST(1, 2)"]; | |
| n_0030 [label="IDX(8)"]; | |
| n_0030 -> n_0026; | |
| n_0030 -> n_0008; | |
| n_0035 [label="LOAD(8):obj"]; | |
| n_0035 -> n_0030; | |
| n_0045 [label="STORE(8)"]; | |
| n_0045 -> n_0004; | |
| n_0045 -> n_0035; | |
| n_0039 [label="LABEL(15)"]; | |
| n_0042 [label="BRANCH"]; | |
| n_0042 -> n_0039; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (tc) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (const $val $size) | |
| 5: (load (idx reg reg $scale) $size) | |
| 6: (store (addr reg $ofs) reg $size) | |
| 7: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(32)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(48)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(16)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(32)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0130 [label="STORE(8)"]; | |
| n_0130 -> n_0004; | |
| n_0130 -> n_0018; | |
| n_0027 [label="NZ:obj"]; | |
| n_0027 -> n_0018; | |
| n_0030 [label="ADDR(12)"]; | |
| n_0030 -> n_0018; | |
| n_0034 [label="LOAD(2)"]; | |
| n_0034 -> n_0030; | |
| n_0038 [label="CONST(1, 2)"]; | |
| n_0042 [label="AND"]; | |
| n_0042 -> n_0034; | |
| n_0042 -> n_0038; | |
| n_0046 [label="ZR"]; | |
| n_0046 -> n_0042; | |
| n_0049 [label="ADDR(16)"]; | |
| n_0049 -> n_0018; | |
| n_0053 [label="LOAD(8)"]; | |
| n_0053 -> n_0049; | |
| n_0057 [label="ADDR(64)"]; | |
| n_0057 -> n_0053; | |
| n_0061 [label="LOAD(8)"]; | |
| n_0061 -> n_0057; | |
| n_0065 [label="NZ"]; | |
| n_0065 -> n_0061; | |
| n_0068 [label="ALL"]; | |
| n_0068 -> n_0027; | |
| n_0068 -> n_0046; | |
| n_0068 -> n_0065; | |
| n_0073 [label="ADDR(16)"]; | |
| n_0073 -> n_0018; | |
| n_0077 [label="LOAD(8)"]; | |
| n_0077 -> n_0073; | |
| n_0081 [label="ADDR(64)"]; | |
| n_0081 -> n_0077; | |
| n_0085 [label="LOAD(8)"]; | |
| n_0085 -> n_0081; | |
| n_0089 [label="ADDR(8)"]; | |
| n_0089 -> n_0085; | |
| n_0093 [label="LOAD(8)"]; | |
| n_0093 -> n_0089; | |
| n_0097 [label="TC"]; | |
| n_0099 [label="CARG(0)"]; | |
| n_0099 -> n_0097; | |
| n_0103 [label="CARG(0)"]; | |
| n_0103 -> n_0018; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(32)"]; | |
| n_0023 -> n_0021; | |
| n_0107 [label="CARG(0)"]; | |
| n_0107 -> n_0023; | |
| n_0111 [label="ARGLIST"]; | |
| n_0111 -> n_0099; | |
| n_0111 -> n_0103; | |
| n_0111 -> n_0107; | |
| n_0116 [label="CALLV"]; | |
| n_0116 -> n_0093; | |
| n_0116 -> n_0111; | |
| n_0120 [label="STORE(8)"]; | |
| n_0120 -> n_0023; | |
| n_0120 -> n_0018; | |
| n_0125 [label="IFV"]; | |
| n_0125 -> n_0068; | |
| n_0125 -> n_0116; | |
| n_0125 -> n_0120; | |
| n_0135 [label="LOCAL"]; | |
| n_0137 [label="ADDR(88)"]; | |
| n_0137 -> n_0135; | |
| n_0141 [label="LOCAL"]; | |
| n_0143 [label="ADDR(32)"]; | |
| n_0143 -> n_0141; | |
| n_0147 [label="LOAD(8):obj"]; | |
| n_0147 -> n_0143; | |
| n_0151 [label="NZ:obj"]; | |
| n_0151 -> n_0147; | |
| n_0154 [label="ADDR(12)"]; | |
| n_0154 -> n_0147; | |
| n_0158 [label="LOAD(2)"]; | |
| n_0158 -> n_0154; | |
| n_0162 [label="CONST(1, 2)"]; | |
| n_0166 [label="AND"]; | |
| n_0166 -> n_0158; | |
| n_0166 -> n_0162; | |
| n_0170 [label="ZR"]; | |
| n_0170 -> n_0166; | |
| n_0173 [label="ALL"]; | |
| n_0173 -> n_0151; | |
| n_0173 -> n_0170; | |
| n_0177 [label="CONST(1, 8)"]; | |
| n_0181 [label="CONST(0, 8)"]; | |
| n_0185 [label="IF:int64"]; | |
| n_0185 -> n_0173; | |
| n_0185 -> n_0177; | |
| n_0185 -> n_0181; | |
| n_0190 [label="STORE(8)"]; | |
| n_0190 -> n_0137; | |
| n_0190 -> n_0185; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-7) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| 5: (nz reg) | |
| 6: (conditional-branch :fail) | |
| -> { 1, 4 } | |
| Block{1} [7-9) | |
| 7: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 8: (conditional-branch :fail) | |
| -> { 2, 4 } | |
| Block{2} [9-12) | |
| 9: (load (addr reg $ofs) $size) | |
| 10: (nz (load (addr reg $ofs) $size)) | |
| 11: (conditional-branch :fail) | |
| -> { 3, 4 } | |
| Block{3} [12-24) | |
| 12: (all flag) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (load (addr reg $ofs) $size) | |
| 15: (tc) | |
| 16: (carg reg) | |
| 17: (carg reg) | |
| 18: (local) | |
| 19: (addr reg $ofs) | |
| 20: (carg reg) | |
| 21: (arglist c_arg) | |
| 22: (callv (load (addr reg $ofs) $sz) c_args) | |
| 23: (branch :after) | |
| -> { 5 } | |
| Block{4} [24-26) | |
| 24: (label :fail) | |
| 25: (store (addr reg $ofs) reg $size) | |
| -> { 5 } | |
| Block{5} [26-32) | |
| 26: (branch :after) | |
| 27: (ifv flag void) | |
| 28: (local) | |
| 29: (local) | |
| 30: (nz (load (addr reg $ofs) $size)) | |
| 31: (conditional-branch :fail) | |
| -> { 6, 8 } | |
| Block{6} [32-35) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 34: (conditional-branch :fail) | |
| -> { 7, 8 } | |
| Block{7} [35-38) | |
| 35: (all flag) | |
| 36: (const $val $size) | |
| 37: (branch :after) | |
| -> { 9 } | |
| Block{8} [38-40) | |
| 38: (label :fail) | |
| 39: (const $val $size) | |
| -> { 9 } | |
| Block{9} [40-43) | |
| 40: (branch :after) | |
| 41: (if flag reg) | |
| 42: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(32)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="TC"]; | |
| n_0010 [label="ADDR(16)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8)"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="ADDR(1760)"]; | |
| n_0018 -> n_0014; | |
| n_0022 [label="LOAD(8):obj"]; | |
| n_0022 -> n_0018; | |
| n_0026 [label="STORE(8)"]; | |
| n_0026 -> n_0004; | |
| n_0026 -> n_0022; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (tc) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(96)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(16)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="ZR:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="FLAGVAL"]; | |
| n_0021 -> n_0018; | |
| n_0024 [label="TC"]; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0024; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="ADDR(1760)"]; | |
| n_0034 -> n_0030; | |
| n_0038 [label="LOAD(8)"]; | |
| n_0038 -> n_0034; | |
| n_0042 [label="EQ:obj"]; | |
| n_0042 -> n_0014; | |
| n_0042 -> n_0038; | |
| n_0046 [label="FLAGVAL"]; | |
| n_0046 -> n_0042; | |
| n_0049 [label="OR:int64"]; | |
| n_0049 -> n_0021; | |
| n_0049 -> n_0046; | |
| n_0066 [label="STORE(8)"]; | |
| n_0066 -> n_0004; | |
| n_0066 -> n_0049; | |
| n_0056 [label="NZ:int64"]; | |
| n_0056 -> n_0049; | |
| n_0053 [label="LABEL(99)"]; | |
| n_0059 [label="BRANCH"]; | |
| n_0059 -> n_0053; | |
| n_0062 [label="WHEN"]; | |
| n_0062 -> n_0056; | |
| n_0062 -> n_0059; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-14) | |
| 0: (local) | |
| 1: (local) | |
| 2: (zr (load (addr reg $ofs) $size)) | |
| 3: (flagval flag) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (tc) | |
| 6: (load (addr reg $ofs) $size) | |
| 7: (load (addr reg $ofs) $size) | |
| 8: (eq reg reg) | |
| 9: (flagval flag) | |
| 10: (or reg reg) | |
| 11: (store (addr reg $ofs) reg $size) | |
| 12: (nz reg) | |
| 13: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [14-15) | |
| 14: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [15-17) | |
| 15: (label :fail) | |
| 16: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(120)"]; | |
| n_0004 -> n_0002; | |
| n_0018 [label="CONST_PTR(0)"]; | |
| n_0021 [label="TC"]; | |
| n_0023 [label="CARG(0)"]; | |
| n_0023 -> n_0021; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(104)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0027 [label="CARG(0)"]; | |
| n_0027 -> n_0014; | |
| n_0031 [label="ARGLIST"]; | |
| n_0031 -> n_0023; | |
| n_0031 -> n_0027; | |
| n_0035 [label="CALL(8):obj"]; | |
| n_0035 -> n_0018; | |
| n_0035 -> n_0031; | |
| n_0040 [label="STORE(8)"]; | |
| n_0040 -> n_0004; | |
| n_0040 -> n_0035; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-9) | |
| 0: (local) | |
| 1: (tc) | |
| 2: (carg reg) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (carg reg) | |
| 6: (arglist c_arg) | |
| 7: (call (const_ptr $ptr) c_args $size) | |
| 8: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(120)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="NZ:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="ADDR(12)"]; | |
| n_0021 -> n_0014; | |
| n_0025 [label="LOAD(2)"]; | |
| n_0025 -> n_0021; | |
| n_0029 [label="CONST(1, 2)"]; | |
| n_0033 [label="AND"]; | |
| n_0033 -> n_0025; | |
| n_0033 -> n_0029; | |
| n_0037 [label="ZR"]; | |
| n_0037 -> n_0033; | |
| n_0040 [label="ADDR(16)"]; | |
| n_0040 -> n_0014; | |
| n_0044 [label="LOAD(8)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="ADDR(64)"]; | |
| n_0048 -> n_0044; | |
| n_0052 [label="LOAD(8)"]; | |
| n_0052 -> n_0048; | |
| n_0056 [label="NZ"]; | |
| n_0056 -> n_0052; | |
| n_0059 [label="ALL"]; | |
| n_0059 -> n_0018; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0056; | |
| n_0064 [label="ADDR(16)"]; | |
| n_0064 -> n_0014; | |
| n_0068 [label="LOAD(8)"]; | |
| n_0068 -> n_0064; | |
| n_0072 [label="ADDR(64)"]; | |
| n_0072 -> n_0068; | |
| n_0076 [label="LOAD(8)"]; | |
| n_0076 -> n_0072; | |
| n_0080 [label="ADDR(8)"]; | |
| n_0080 -> n_0076; | |
| n_0084 [label="LOAD(8)"]; | |
| n_0084 -> n_0080; | |
| n_0088 [label="TC"]; | |
| n_0090 [label="CARG(0)"]; | |
| n_0090 -> n_0088; | |
| n_0094 [label="CARG(0)"]; | |
| n_0094 -> n_0014; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(40)"]; | |
| n_0004 -> n_0002; | |
| n_0098 [label="CARG(0)"]; | |
| n_0098 -> n_0004; | |
| n_0102 [label="ARGLIST"]; | |
| n_0102 -> n_0090; | |
| n_0102 -> n_0094; | |
| n_0102 -> n_0098; | |
| n_0107 [label="CALLV"]; | |
| n_0107 -> n_0084; | |
| n_0107 -> n_0102; | |
| n_0111 [label="STORE(8)"]; | |
| n_0111 -> n_0004; | |
| n_0111 -> n_0014; | |
| n_0116 [label="IFV"]; | |
| n_0116 -> n_0059; | |
| n_0116 -> n_0107; | |
| n_0116 -> n_0111; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-3) | |
| 0: (local) | |
| 1: (nz (load (addr reg $ofs) $size)) | |
| 2: (conditional-branch :fail) | |
| -> { 1, 4 } | |
| Block{1} [3-6) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 5: (conditional-branch :fail) | |
| -> { 2, 4 } | |
| Block{2} [6-10) | |
| 6: (load (addr reg $ofs) $size) | |
| 7: (load (addr reg $ofs) $size) | |
| 8: (nz (load (addr reg $ofs) $size)) | |
| 9: (conditional-branch :fail) | |
| -> { 3, 4 } | |
| Block{3} [10-24) | |
| 10: (all flag) | |
| 11: (load (addr reg $ofs) $size) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (tc) | |
| 15: (carg reg) | |
| 16: (load (addr reg $ofs) $size) | |
| 17: (carg reg) | |
| 18: (local) | |
| 19: (addr reg $ofs) | |
| 20: (carg reg) | |
| 21: (arglist c_arg) | |
| 22: (callv (load (addr reg $ofs) $sz) c_args) | |
| 23: (branch :after) | |
| -> { 5 } | |
| Block{4} [24-27) | |
| 24: (label :fail) | |
| 25: (load (addr reg $ofs) $size) | |
| 26: (store (addr reg $ofs) reg $size) | |
| -> { 5 } | |
| Block{5} [27-29) | |
| 27: (branch :after) | |
| 28: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0018 [label="CONST_PTR(0)"]; | |
| n_0021 [label="TC"]; | |
| n_0023 [label="CARG(0)"]; | |
| n_0023 -> n_0021; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(40)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0027 [label="CARG(0)"]; | |
| n_0027 -> n_0014; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(344)"]; | |
| n_0004 -> n_0002; | |
| n_0031 [label="CARG(0)"]; | |
| n_0031 -> n_0004; | |
| n_0035 [label="CONST(0, 8)"]; | |
| n_0039 [label="CARG(0)"]; | |
| n_0039 -> n_0035; | |
| n_0043 [label="CONST(0, 8)"]; | |
| n_0047 [label="CARG(0)"]; | |
| n_0047 -> n_0043; | |
| n_0051 [label="CONST(0, 8)"]; | |
| n_0055 [label="CARG(1)"]; | |
| n_0055 -> n_0051; | |
| n_0059 [label="ARGLIST"]; | |
| n_0059 -> n_0023; | |
| n_0059 -> n_0027; | |
| n_0059 -> n_0031; | |
| n_0059 -> n_0039; | |
| n_0059 -> n_0047; | |
| n_0059 -> n_0055; | |
| n_0067 [label="CALLV"]; | |
| n_0067 -> n_0018; | |
| n_0067 -> n_0059; | |
| n_0071 [label="LOCAL"]; | |
| n_0073 [label="ADDR(344)"]; | |
| n_0073 -> n_0071; | |
| n_0077 [label="LOAD(8):int64"]; | |
| n_0077 -> n_0073; | |
| n_0084 [label="ZR:int64"]; | |
| n_0084 -> n_0077; | |
| n_0081 [label="LABEL(98)"]; | |
| n_0087 [label="BRANCH"]; | |
| n_0087 -> n_0081; | |
| n_0090 [label="WHEN"]; | |
| n_0090 -> n_0084; | |
| n_0090 -> n_0087; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-19) | |
| 0: (tc) | |
| 1: (carg reg) | |
| 2: (local) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (carg reg) | |
| 5: (local) | |
| 6: (addr reg $ofs) | |
| 7: (carg reg) | |
| 8: (const $val $size) | |
| 9: (carg reg) | |
| 10: (const $val $size) | |
| 11: (carg reg) | |
| 12: (const $val $size) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (callv (const_ptr $ptr) c_args) | |
| 16: (local) | |
| 17: (zr (load (addr reg $ofs) $size)) | |
| 18: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [19-20) | |
| 19: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [20-22) | |
| 20: (label :fail) | |
| 21: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(120)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="ADDR(16)"]; | |
| n_0018 -> n_0014; | |
| n_0022 [label="LOAD(8)"]; | |
| n_0022 -> n_0018; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0022; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="ADDR(192)"]; | |
| n_0034 -> n_0030; | |
| n_0038 [label="LOAD(8)"]; | |
| n_0038 -> n_0034; | |
| n_0042 [label="TC"]; | |
| n_0044 [label="CARG(0)"]; | |
| n_0044 -> n_0042; | |
| n_0048 [label="ADDR(16)"]; | |
| n_0048 -> n_0014; | |
| n_0052 [label="LOAD(8)"]; | |
| n_0052 -> n_0048; | |
| n_0056 [label="CARG(0)"]; | |
| n_0056 -> n_0052; | |
| n_0060 [label="CARG(0)"]; | |
| n_0060 -> n_0014; | |
| n_0064 [label="ADDR(24)"]; | |
| n_0064 -> n_0014; | |
| n_0068 [label="CARG(0)"]; | |
| n_0068 -> n_0064; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(128)"]; | |
| n_0004 -> n_0002; | |
| n_0072 [label="CARG(0)"]; | |
| n_0072 -> n_0004; | |
| n_0076 [label="CONST(8, 8)"]; | |
| n_0080 [label="CARG(1)"]; | |
| n_0080 -> n_0076; | |
| n_0084 [label="ARGLIST"]; | |
| n_0084 -> n_0044; | |
| n_0084 -> n_0056; | |
| n_0084 -> n_0060; | |
| n_0084 -> n_0068; | |
| n_0084 -> n_0072; | |
| n_0084 -> n_0080; | |
| n_0092 [label="CALLV"]; | |
| n_0092 -> n_0038; | |
| n_0092 -> n_0084; | |
| n_0102 [label="LOCAL"]; | |
| n_0104 [label="ADDR(128)"]; | |
| n_0104 -> n_0102; | |
| n_0108 [label="LOAD(8):obj"]; | |
| n_0108 -> n_0104; | |
| n_0112 [label="NZ:obj"]; | |
| n_0112 -> n_0108; | |
| n_0115 [label="ADDR(12)"]; | |
| n_0115 -> n_0108; | |
| n_0119 [label="LOAD(2)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="CONST(1, 2)"]; | |
| n_0127 [label="AND"]; | |
| n_0127 -> n_0119; | |
| n_0127 -> n_0123; | |
| n_0131 [label="ZR"]; | |
| n_0131 -> n_0127; | |
| n_0134 [label="ADDR(16)"]; | |
| n_0134 -> n_0108; | |
| n_0138 [label="LOAD(8)"]; | |
| n_0138 -> n_0134; | |
| n_0142 [label="ADDR(64)"]; | |
| n_0142 -> n_0138; | |
| n_0146 [label="LOAD(8)"]; | |
| n_0146 -> n_0142; | |
| n_0150 [label="NZ"]; | |
| n_0150 -> n_0146; | |
| n_0153 [label="ALL"]; | |
| n_0153 -> n_0112; | |
| n_0153 -> n_0131; | |
| n_0153 -> n_0150; | |
| n_0158 [label="ADDR(16)"]; | |
| n_0158 -> n_0108; | |
| n_0162 [label="LOAD(8)"]; | |
| n_0162 -> n_0158; | |
| n_0166 [label="ADDR(64)"]; | |
| n_0166 -> n_0162; | |
| n_0170 [label="LOAD(8)"]; | |
| n_0170 -> n_0166; | |
| n_0174 [label="ADDR(8)"]; | |
| n_0174 -> n_0170; | |
| n_0178 [label="LOAD(8)"]; | |
| n_0178 -> n_0174; | |
| n_0182 [label="TC"]; | |
| n_0184 [label="CARG(0)"]; | |
| n_0184 -> n_0182; | |
| n_0188 [label="CARG(0)"]; | |
| n_0188 -> n_0108; | |
| n_0096 [label="LOCAL"]; | |
| n_0098 [label="ADDR(40)"]; | |
| n_0098 -> n_0096; | |
| n_0192 [label="CARG(0)"]; | |
| n_0192 -> n_0098; | |
| n_0196 [label="ARGLIST"]; | |
| n_0196 -> n_0184; | |
| n_0196 -> n_0188; | |
| n_0196 -> n_0192; | |
| n_0201 [label="CALLV"]; | |
| n_0201 -> n_0178; | |
| n_0201 -> n_0196; | |
| n_0205 [label="STORE(8)"]; | |
| n_0205 -> n_0098; | |
| n_0205 -> n_0108; | |
| n_0210 [label="IFV"]; | |
| n_0210 -> n_0153; | |
| n_0210 -> n_0201; | |
| n_0210 -> n_0205; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-21) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (tc) | |
| 5: (carg reg) | |
| 6: (load (addr reg $ofs) $size) | |
| 7: (carg reg) | |
| 8: (carg reg) | |
| 9: (addr reg $ofs) | |
| 10: (carg reg) | |
| 11: (local) | |
| 12: (addr reg $ofs) | |
| 13: (carg reg) | |
| 14: (const $val $size) | |
| 15: (carg reg) | |
| 16: (arglist c_arg) | |
| 17: (callv (load (addr reg $ofs) $sz) c_args) | |
| 18: (local) | |
| 19: (nz (load (addr reg $ofs) $size)) | |
| 20: (conditional-branch :fail) | |
| -> { 1, 4 } | |
| Block{1} [21-24) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 23: (conditional-branch :fail) | |
| -> { 2, 4 } | |
| Block{2} [24-28) | |
| 24: (load (addr reg $ofs) $size) | |
| 25: (load (addr reg $ofs) $size) | |
| 26: (nz (load (addr reg $ofs) $size)) | |
| 27: (conditional-branch :fail) | |
| -> { 3, 4 } | |
| Block{3} [28-42) | |
| 28: (all flag) | |
| 29: (load (addr reg $ofs) $size) | |
| 30: (load (addr reg $ofs) $size) | |
| 31: (load (addr reg $ofs) $size) | |
| 32: (tc) | |
| 33: (carg reg) | |
| 34: (load (addr reg $ofs) $size) | |
| 35: (carg reg) | |
| 36: (local) | |
| 37: (addr reg $ofs) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (branch :after) | |
| -> { 5 } | |
| Block{4} [42-45) | |
| 42: (label :fail) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (store (addr reg $ofs) reg $size) | |
| -> { 5 } | |
| Block{5} [45-47) | |
| 45: (branch :after) | |
| 46: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0018 [label="CONST_PTR(0)"]; | |
| n_0021 [label="TC"]; | |
| n_0023 [label="CARG(0)"]; | |
| n_0023 -> n_0021; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(40)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0027 [label="CARG(0)"]; | |
| n_0027 -> n_0014; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0031 [label="CARG(0)"]; | |
| n_0031 -> n_0004; | |
| n_0035 [label="ARGLIST"]; | |
| n_0035 -> n_0023; | |
| n_0035 -> n_0027; | |
| n_0035 -> n_0031; | |
| n_0040 [label="CALLV"]; | |
| n_0040 -> n_0018; | |
| n_0040 -> n_0035; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (tc) | |
| 1: (carg reg) | |
| 2: (local) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (carg reg) | |
| 5: (local) | |
| 6: (addr reg $ofs) | |
| 7: (carg reg) | |
| 8: (arglist c_arg) | |
| 9: (callv (const_ptr $ptr) c_args) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(136)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(24)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):str"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:str"]; | |
| n_0018 -> n_0014; | |
| n_0140 [label="STORE(8)"]; | |
| n_0140 -> n_0004; | |
| n_0140 -> n_0018; | |
| n_0027 [label="LOCAL"]; | |
| n_0029 [label="ADDR(8)"]; | |
| n_0029 -> n_0027; | |
| n_0033 [label="LOAD(8):obj"]; | |
| n_0033 -> n_0029; | |
| n_0037 [label="NZ:obj"]; | |
| n_0037 -> n_0033; | |
| n_0040 [label="ADDR(12)"]; | |
| n_0040 -> n_0033; | |
| n_0044 [label="LOAD(2)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="CONST(1, 2)"]; | |
| n_0052 [label="AND"]; | |
| n_0052 -> n_0044; | |
| n_0052 -> n_0048; | |
| n_0056 [label="ZR"]; | |
| n_0056 -> n_0052; | |
| n_0059 [label="ADDR(16)"]; | |
| n_0059 -> n_0033; | |
| n_0063 [label="LOAD(8)"]; | |
| n_0063 -> n_0059; | |
| n_0067 [label="ADDR(64)"]; | |
| n_0067 -> n_0063; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="NZ"]; | |
| n_0075 -> n_0071; | |
| n_0078 [label="ALL"]; | |
| n_0078 -> n_0037; | |
| n_0078 -> n_0056; | |
| n_0078 -> n_0075; | |
| n_0083 [label="ADDR(16)"]; | |
| n_0083 -> n_0033; | |
| n_0087 [label="LOAD(8)"]; | |
| n_0087 -> n_0083; | |
| n_0091 [label="ADDR(64)"]; | |
| n_0091 -> n_0087; | |
| n_0095 [label="LOAD(8)"]; | |
| n_0095 -> n_0091; | |
| n_0099 [label="ADDR(8)"]; | |
| n_0099 -> n_0095; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="TC"]; | |
| n_0109 [label="CARG(0)"]; | |
| n_0109 -> n_0107; | |
| n_0113 [label="CARG(0)"]; | |
| n_0113 -> n_0033; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(48)"]; | |
| n_0023 -> n_0021; | |
| n_0117 [label="CARG(0)"]; | |
| n_0117 -> n_0023; | |
| n_0121 [label="ARGLIST"]; | |
| n_0121 -> n_0109; | |
| n_0121 -> n_0113; | |
| n_0121 -> n_0117; | |
| n_0126 [label="CALLV"]; | |
| n_0126 -> n_0103; | |
| n_0126 -> n_0121; | |
| n_0130 [label="STORE(8)"]; | |
| n_0130 -> n_0023; | |
| n_0130 -> n_0033; | |
| n_0135 [label="IFV"]; | |
| n_0135 -> n_0078; | |
| n_0135 -> n_0126; | |
| n_0135 -> n_0130; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| 5: (local) | |
| 6: (nz (load (addr reg $ofs) $size)) | |
| 7: (conditional-branch :fail) | |
| -> { 1, 4 } | |
| Block{1} [8-11) | |
| 8: (load (addr reg $ofs) $size) | |
| 9: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 10: (conditional-branch :fail) | |
| -> { 2, 4 } | |
| Block{2} [11-15) | |
| 11: (load (addr reg $ofs) $size) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (nz (load (addr reg $ofs) $size)) | |
| 14: (conditional-branch :fail) | |
| -> { 3, 4 } | |
| Block{3} [15-29) | |
| 15: (all flag) | |
| 16: (load (addr reg $ofs) $size) | |
| 17: (load (addr reg $ofs) $size) | |
| 18: (load (addr reg $ofs) $size) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (carg reg) | |
| 23: (local) | |
| 24: (addr reg $ofs) | |
| 25: (carg reg) | |
| 26: (arglist c_arg) | |
| 27: (callv (load (addr reg $ofs) $sz) c_args) | |
| 28: (branch :after) | |
| -> { 5 } | |
| Block{4} [29-32) | |
| 29: (label :fail) | |
| 30: (load (addr reg $ofs) $size) | |
| 31: (store (addr reg $ofs) reg $size) | |
| -> { 5 } | |
| Block{5} [32-34) | |
| 32: (branch :after) | |
| 33: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(48)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(2, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(40)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(40)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="NZ:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="ADDR(12)"]; | |
| n_0021 -> n_0014; | |
| n_0025 [label="LOAD(2)"]; | |
| n_0025 -> n_0021; | |
| n_0029 [label="CONST(1, 2)"]; | |
| n_0033 [label="AND"]; | |
| n_0033 -> n_0025; | |
| n_0033 -> n_0029; | |
| n_0037 [label="ZR"]; | |
| n_0037 -> n_0033; | |
| n_0040 [label="ADDR(16)"]; | |
| n_0040 -> n_0014; | |
| n_0044 [label="LOAD(8)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="ADDR(64)"]; | |
| n_0048 -> n_0044; | |
| n_0052 [label="LOAD(8)"]; | |
| n_0052 -> n_0048; | |
| n_0056 [label="NZ"]; | |
| n_0056 -> n_0052; | |
| n_0059 [label="ALL"]; | |
| n_0059 -> n_0018; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0056; | |
| n_0064 [label="ADDR(16)"]; | |
| n_0064 -> n_0014; | |
| n_0068 [label="LOAD(8)"]; | |
| n_0068 -> n_0064; | |
| n_0072 [label="ADDR(64)"]; | |
| n_0072 -> n_0068; | |
| n_0076 [label="LOAD(8)"]; | |
| n_0076 -> n_0072; | |
| n_0080 [label="ADDR(8)"]; | |
| n_0080 -> n_0076; | |
| n_0084 [label="LOAD(8)"]; | |
| n_0084 -> n_0080; | |
| n_0088 [label="TC"]; | |
| n_0090 [label="CARG(0)"]; | |
| n_0090 -> n_0088; | |
| n_0094 [label="CARG(0)"]; | |
| n_0094 -> n_0014; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0098 [label="CARG(0)"]; | |
| n_0098 -> n_0004; | |
| n_0102 [label="ARGLIST"]; | |
| n_0102 -> n_0090; | |
| n_0102 -> n_0094; | |
| n_0102 -> n_0098; | |
| n_0107 [label="CALLV"]; | |
| n_0107 -> n_0084; | |
| n_0107 -> n_0102; | |
| n_0111 [label="STORE(8)"]; | |
| n_0111 -> n_0004; | |
| n_0111 -> n_0014; | |
| n_0116 [label="IFV"]; | |
| n_0116 -> n_0059; | |
| n_0116 -> n_0107; | |
| n_0116 -> n_0111; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-3) | |
| 0: (local) | |
| 1: (nz (load (addr reg $ofs) $size)) | |
| 2: (conditional-branch :fail) | |
| -> { 1, 4 } | |
| Block{1} [3-6) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 5: (conditional-branch :fail) | |
| -> { 2, 4 } | |
| Block{2} [6-10) | |
| 6: (load (addr reg $ofs) $size) | |
| 7: (load (addr reg $ofs) $size) | |
| 8: (nz (load (addr reg $ofs) $size)) | |
| 9: (conditional-branch :fail) | |
| -> { 3, 4 } | |
| Block{3} [10-24) | |
| 10: (all flag) | |
| 11: (load (addr reg $ofs) $size) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (tc) | |
| 15: (carg reg) | |
| 16: (load (addr reg $ofs) $size) | |
| 17: (carg reg) | |
| 18: (local) | |
| 19: (addr reg $ofs) | |
| 20: (carg reg) | |
| 21: (arglist c_arg) | |
| 22: (callv (load (addr reg $ofs) $sz) c_args) | |
| 23: (branch :after) | |
| -> { 5 } | |
| Block{4} [24-27) | |
| 24: (label :fail) | |
| 25: (load (addr reg $ofs) $size) | |
| 26: (store (addr reg $ofs) reg $size) | |
| -> { 5 } | |
| Block{5} [27-29) | |
| 27: (branch :after) | |
| 28: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0018 [label="CONST_PTR(0)"]; | |
| n_0021 [label="TC"]; | |
| n_0023 [label="CARG(0)"]; | |
| n_0023 -> n_0021; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(80)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0027 [label="CARG(0)"]; | |
| n_0027 -> n_0014; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(344)"]; | |
| n_0004 -> n_0002; | |
| n_0031 [label="CARG(0)"]; | |
| n_0031 -> n_0004; | |
| n_0035 [label="CONST(0, 8)"]; | |
| n_0039 [label="CARG(0)"]; | |
| n_0039 -> n_0035; | |
| n_0043 [label="CONST(0, 8)"]; | |
| n_0047 [label="CARG(0)"]; | |
| n_0047 -> n_0043; | |
| n_0051 [label="CONST(0, 8)"]; | |
| n_0055 [label="CARG(1)"]; | |
| n_0055 -> n_0051; | |
| n_0059 [label="ARGLIST"]; | |
| n_0059 -> n_0023; | |
| n_0059 -> n_0027; | |
| n_0059 -> n_0031; | |
| n_0059 -> n_0039; | |
| n_0059 -> n_0047; | |
| n_0059 -> n_0055; | |
| n_0067 [label="CALLV"]; | |
| n_0067 -> n_0018; | |
| n_0067 -> n_0059; | |
| n_0071 [label="LOCAL"]; | |
| n_0073 [label="ADDR(344)"]; | |
| n_0073 -> n_0071; | |
| n_0077 [label="LOAD(8):int64"]; | |
| n_0077 -> n_0073; | |
| n_0084 [label="NZ:int64"]; | |
| n_0084 -> n_0077; | |
| n_0081 [label="LABEL(97)"]; | |
| n_0087 [label="BRANCH"]; | |
| n_0087 -> n_0081; | |
| n_0090 [label="WHEN"]; | |
| n_0090 -> n_0084; | |
| n_0090 -> n_0087; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-19) | |
| 0: (tc) | |
| 1: (carg reg) | |
| 2: (local) | |
| 3: (load (addr reg $ofs) $size) | |
| 4: (carg reg) | |
| 5: (local) | |
| 6: (addr reg $ofs) | |
| 7: (carg reg) | |
| 8: (const $val $size) | |
| 9: (carg reg) | |
| 10: (const $val $size) | |
| 11: (carg reg) | |
| 12: (const $val $size) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (callv (const_ptr $ptr) c_args) | |
| 16: (local) | |
| 17: (nz (load (addr reg $ofs) $size)) | |
| 18: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [19-20) | |
| 19: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [20-22) | |
| 20: (label :fail) | |
| 21: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(0, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(160)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(35)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0192 [label="STORE(8)"]; | |
| n_0192 -> n_0004; | |
| n_0192 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(8)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0089 [label="NZ:obj"]; | |
| n_0089 -> n_0085; | |
| n_0092 [label="ADDR(12)"]; | |
| n_0092 -> n_0085; | |
| n_0096 [label="LOAD(2)"]; | |
| n_0096 -> n_0092; | |
| n_0100 [label="CONST(1, 2)"]; | |
| n_0104 [label="AND"]; | |
| n_0104 -> n_0096; | |
| n_0104 -> n_0100; | |
| n_0108 [label="ZR"]; | |
| n_0108 -> n_0104; | |
| n_0111 [label="ADDR(16)"]; | |
| n_0111 -> n_0085; | |
| n_0115 [label="LOAD(8)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="ADDR(64)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="LOAD(8)"]; | |
| n_0123 -> n_0119; | |
| n_0127 [label="NZ"]; | |
| n_0127 -> n_0123; | |
| n_0130 [label="ALL"]; | |
| n_0130 -> n_0089; | |
| n_0130 -> n_0108; | |
| n_0130 -> n_0127; | |
| n_0135 [label="ADDR(16)"]; | |
| n_0135 -> n_0085; | |
| n_0139 [label="LOAD(8)"]; | |
| n_0139 -> n_0135; | |
| n_0143 [label="ADDR(64)"]; | |
| n_0143 -> n_0139; | |
| n_0147 [label="LOAD(8)"]; | |
| n_0147 -> n_0143; | |
| n_0151 [label="ADDR(8)"]; | |
| n_0151 -> n_0147; | |
| n_0155 [label="LOAD(8)"]; | |
| n_0155 -> n_0151; | |
| n_0159 [label="TC"]; | |
| n_0161 [label="CARG(0)"]; | |
| n_0161 -> n_0159; | |
| n_0165 [label="CARG(0)"]; | |
| n_0165 -> n_0085; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(80)"]; | |
| n_0075 -> n_0073; | |
| n_0169 [label="CARG(0)"]; | |
| n_0169 -> n_0075; | |
| n_0173 [label="ARGLIST"]; | |
| n_0173 -> n_0161; | |
| n_0173 -> n_0165; | |
| n_0173 -> n_0169; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0155; | |
| n_0178 -> n_0173; | |
| n_0182 [label="STORE(8)"]; | |
| n_0182 -> n_0075; | |
| n_0182 -> n_0085; | |
| n_0187 [label="IFV"]; | |
| n_0187 -> n_0130; | |
| n_0187 -> n_0178; | |
| n_0187 -> n_0182; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-23) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (nz (load (addr reg $ofs) $size)) | |
| 22: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [23-26) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 25: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [26-30) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (load (addr reg $ofs) $size) | |
| 28: (nz (load (addr reg $ofs) $size)) | |
| 29: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [30-44) | |
| 30: (all flag) | |
| 31: (load (addr reg $ofs) $size) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (load (addr reg $ofs) $size) | |
| 34: (tc) | |
| 35: (carg reg) | |
| 36: (load (addr reg $ofs) $size) | |
| 37: (carg reg) | |
| 38: (local) | |
| 39: (addr reg $ofs) | |
| 40: (carg reg) | |
| 41: (arglist c_arg) | |
| 42: (callv (load (addr reg $ofs) $sz) c_args) | |
| 43: (branch :after) | |
| -> { 8 } | |
| Block{7} [44-47) | |
| 44: (label :fail) | |
| 45: (load (addr reg $ofs) $size) | |
| 46: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [47-49) | |
| 47: (branch :after) | |
| 48: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(80)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(4, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(48)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(1, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(168)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(41)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0338 [label="STORE(8)"]; | |
| n_0338 -> n_0004; | |
| n_0338 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(152)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(4, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(80)"]; | |
| n_0184 -> n_0182; | |
| n_0192 [label="TC"]; | |
| n_0194 [label="ADDR(432)"]; | |
| n_0194 -> n_0192; | |
| n_0198 [label="LOAD(8)"]; | |
| n_0198 -> n_0194; | |
| n_0202 [label="ADDR(120)"]; | |
| n_0202 -> n_0198; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0188 [label="CONST(6, 2)"]; | |
| n_0210 [label="IDX(8)"]; | |
| n_0210 -> n_0206; | |
| n_0210 -> n_0188; | |
| n_0215 [label="LOAD(8):obj"]; | |
| n_0215 -> n_0210; | |
| n_0343 [label="STORE(8)"]; | |
| n_0343 -> n_0184; | |
| n_0343 -> n_0215; | |
| n_0225 [label="LOCAL"]; | |
| n_0227 [label="ADDR(8)"]; | |
| n_0227 -> n_0225; | |
| n_0231 [label="LOAD(8):obj"]; | |
| n_0231 -> n_0227; | |
| n_0235 [label="NZ:obj"]; | |
| n_0235 -> n_0231; | |
| n_0238 [label="ADDR(12)"]; | |
| n_0238 -> n_0231; | |
| n_0242 [label="LOAD(2)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CONST(1, 2)"]; | |
| n_0250 [label="AND"]; | |
| n_0250 -> n_0242; | |
| n_0250 -> n_0246; | |
| n_0254 [label="ZR"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(16)"]; | |
| n_0257 -> n_0231; | |
| n_0261 [label="LOAD(8)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="ADDR(64)"]; | |
| n_0265 -> n_0261; | |
| n_0269 [label="LOAD(8)"]; | |
| n_0269 -> n_0265; | |
| n_0273 [label="NZ"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ALL"]; | |
| n_0276 -> n_0235; | |
| n_0276 -> n_0254; | |
| n_0276 -> n_0273; | |
| n_0281 [label="ADDR(16)"]; | |
| n_0281 -> n_0231; | |
| n_0285 [label="LOAD(8)"]; | |
| n_0285 -> n_0281; | |
| n_0289 [label="ADDR(64)"]; | |
| n_0289 -> n_0285; | |
| n_0293 [label="LOAD(8)"]; | |
| n_0293 -> n_0289; | |
| n_0297 [label="ADDR(8)"]; | |
| n_0297 -> n_0293; | |
| n_0301 [label="LOAD(8)"]; | |
| n_0301 -> n_0297; | |
| n_0305 [label="TC"]; | |
| n_0307 [label="CARG(0)"]; | |
| n_0307 -> n_0305; | |
| n_0311 [label="CARG(0)"]; | |
| n_0311 -> n_0231; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(64)"]; | |
| n_0221 -> n_0219; | |
| n_0315 [label="CARG(0)"]; | |
| n_0315 -> n_0221; | |
| n_0319 [label="ARGLIST"]; | |
| n_0319 -> n_0307; | |
| n_0319 -> n_0311; | |
| n_0319 -> n_0315; | |
| n_0324 [label="CALLV"]; | |
| n_0324 -> n_0301; | |
| n_0324 -> n_0319; | |
| n_0328 [label="STORE(8)"]; | |
| n_0328 -> n_0221; | |
| n_0328 -> n_0231; | |
| n_0333 [label="IFV"]; | |
| n_0333 -> n_0276; | |
| n_0333 -> n_0324; | |
| n_0333 -> n_0328; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-51) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (tc) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (load (addr reg $ofs) $size) | |
| 45: (const $val $size) | |
| 46: (load (idx reg reg $scale) $size) | |
| 47: (store (addr reg $ofs) reg $size) | |
| 48: (local) | |
| 49: (nz (load (addr reg $ofs) $size)) | |
| 50: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [51-54) | |
| 51: (load (addr reg $ofs) $size) | |
| 52: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 53: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [54-58) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (nz (load (addr reg $ofs) $size)) | |
| 57: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [58-72) | |
| 58: (all flag) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (load (addr reg $ofs) $size) | |
| 62: (tc) | |
| 63: (carg reg) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (carg reg) | |
| 66: (local) | |
| 67: (addr reg $ofs) | |
| 68: (carg reg) | |
| 69: (arglist c_arg) | |
| 70: (callv (load (addr reg $ofs) $sz) c_args) | |
| 71: (branch :after) | |
| -> { 8 } | |
| Block{7} [72-75) | |
| 72: (label :fail) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [75-77) | |
| 75: (branch :after) | |
| 76: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(64)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(7, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(72)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(2, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(176)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(47)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0338 [label="STORE(8)"]; | |
| n_0338 -> n_0004; | |
| n_0338 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(184)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(6, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(80)"]; | |
| n_0184 -> n_0182; | |
| n_0192 [label="TC"]; | |
| n_0194 [label="ADDR(432)"]; | |
| n_0194 -> n_0192; | |
| n_0198 [label="LOAD(8)"]; | |
| n_0198 -> n_0194; | |
| n_0202 [label="ADDR(120)"]; | |
| n_0202 -> n_0198; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0188 [label="CONST(9, 2)"]; | |
| n_0210 [label="IDX(8)"]; | |
| n_0210 -> n_0206; | |
| n_0210 -> n_0188; | |
| n_0215 [label="LOAD(8):obj"]; | |
| n_0215 -> n_0210; | |
| n_0343 [label="STORE(8)"]; | |
| n_0343 -> n_0184; | |
| n_0343 -> n_0215; | |
| n_0225 [label="LOCAL"]; | |
| n_0227 [label="ADDR(8)"]; | |
| n_0227 -> n_0225; | |
| n_0231 [label="LOAD(8):obj"]; | |
| n_0231 -> n_0227; | |
| n_0235 [label="NZ:obj"]; | |
| n_0235 -> n_0231; | |
| n_0238 [label="ADDR(12)"]; | |
| n_0238 -> n_0231; | |
| n_0242 [label="LOAD(2)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CONST(1, 2)"]; | |
| n_0250 [label="AND"]; | |
| n_0250 -> n_0242; | |
| n_0250 -> n_0246; | |
| n_0254 [label="ZR"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(16)"]; | |
| n_0257 -> n_0231; | |
| n_0261 [label="LOAD(8)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="ADDR(64)"]; | |
| n_0265 -> n_0261; | |
| n_0269 [label="LOAD(8)"]; | |
| n_0269 -> n_0265; | |
| n_0273 [label="NZ"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ALL"]; | |
| n_0276 -> n_0235; | |
| n_0276 -> n_0254; | |
| n_0276 -> n_0273; | |
| n_0281 [label="ADDR(16)"]; | |
| n_0281 -> n_0231; | |
| n_0285 [label="LOAD(8)"]; | |
| n_0285 -> n_0281; | |
| n_0289 [label="ADDR(64)"]; | |
| n_0289 -> n_0285; | |
| n_0293 [label="LOAD(8)"]; | |
| n_0293 -> n_0289; | |
| n_0297 [label="ADDR(8)"]; | |
| n_0297 -> n_0293; | |
| n_0301 [label="LOAD(8)"]; | |
| n_0301 -> n_0297; | |
| n_0305 [label="TC"]; | |
| n_0307 [label="CARG(0)"]; | |
| n_0307 -> n_0305; | |
| n_0311 [label="CARG(0)"]; | |
| n_0311 -> n_0231; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(192)"]; | |
| n_0221 -> n_0219; | |
| n_0315 [label="CARG(0)"]; | |
| n_0315 -> n_0221; | |
| n_0319 [label="ARGLIST"]; | |
| n_0319 -> n_0307; | |
| n_0319 -> n_0311; | |
| n_0319 -> n_0315; | |
| n_0324 [label="CALLV"]; | |
| n_0324 -> n_0301; | |
| n_0324 -> n_0319; | |
| n_0328 [label="STORE(8)"]; | |
| n_0328 -> n_0221; | |
| n_0328 -> n_0231; | |
| n_0333 [label="IFV"]; | |
| n_0333 -> n_0276; | |
| n_0333 -> n_0324; | |
| n_0333 -> n_0328; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-51) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (tc) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (load (addr reg $ofs) $size) | |
| 45: (const $val $size) | |
| 46: (load (idx reg reg $scale) $size) | |
| 47: (store (addr reg $ofs) reg $size) | |
| 48: (local) | |
| 49: (nz (load (addr reg $ofs) $size)) | |
| 50: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [51-54) | |
| 51: (load (addr reg $ofs) $size) | |
| 52: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 53: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [54-58) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (nz (load (addr reg $ofs) $size)) | |
| 57: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [58-72) | |
| 58: (all flag) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (load (addr reg $ofs) $size) | |
| 62: (tc) | |
| 63: (carg reg) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (carg reg) | |
| 66: (local) | |
| 67: (addr reg $ofs) | |
| 68: (carg reg) | |
| 69: (arglist c_arg) | |
| 70: (callv (load (addr reg $ofs) $sz) c_args) | |
| 71: (branch :after) | |
| -> { 8 } | |
| Block{7} [72-75) | |
| 72: (label :fail) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [75-77) | |
| 75: (branch :after) | |
| 76: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(192)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(10, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(64)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(3, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(200)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(53)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(24)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0338 [label="STORE(8)"]; | |
| n_0338 -> n_0004; | |
| n_0338 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(208)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(7, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(80)"]; | |
| n_0184 -> n_0182; | |
| n_0192 [label="TC"]; | |
| n_0194 [label="ADDR(432)"]; | |
| n_0194 -> n_0192; | |
| n_0198 [label="LOAD(8)"]; | |
| n_0198 -> n_0194; | |
| n_0202 [label="ADDR(120)"]; | |
| n_0202 -> n_0198; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0188 [label="CONST(12, 2)"]; | |
| n_0210 [label="IDX(8)"]; | |
| n_0210 -> n_0206; | |
| n_0210 -> n_0188; | |
| n_0215 [label="LOAD(8):obj"]; | |
| n_0215 -> n_0210; | |
| n_0343 [label="STORE(8)"]; | |
| n_0343 -> n_0184; | |
| n_0343 -> n_0215; | |
| n_0225 [label="LOCAL"]; | |
| n_0227 [label="ADDR(8)"]; | |
| n_0227 -> n_0225; | |
| n_0231 [label="LOAD(8):obj"]; | |
| n_0231 -> n_0227; | |
| n_0235 [label="NZ:obj"]; | |
| n_0235 -> n_0231; | |
| n_0238 [label="ADDR(12)"]; | |
| n_0238 -> n_0231; | |
| n_0242 [label="LOAD(2)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CONST(1, 2)"]; | |
| n_0250 [label="AND"]; | |
| n_0250 -> n_0242; | |
| n_0250 -> n_0246; | |
| n_0254 [label="ZR"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(16)"]; | |
| n_0257 -> n_0231; | |
| n_0261 [label="LOAD(8)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="ADDR(64)"]; | |
| n_0265 -> n_0261; | |
| n_0269 [label="LOAD(8)"]; | |
| n_0269 -> n_0265; | |
| n_0273 [label="NZ"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ALL"]; | |
| n_0276 -> n_0235; | |
| n_0276 -> n_0254; | |
| n_0276 -> n_0273; | |
| n_0281 [label="ADDR(16)"]; | |
| n_0281 -> n_0231; | |
| n_0285 [label="LOAD(8)"]; | |
| n_0285 -> n_0281; | |
| n_0289 [label="ADDR(64)"]; | |
| n_0289 -> n_0285; | |
| n_0293 [label="LOAD(8)"]; | |
| n_0293 -> n_0289; | |
| n_0297 [label="ADDR(8)"]; | |
| n_0297 -> n_0293; | |
| n_0301 [label="LOAD(8)"]; | |
| n_0301 -> n_0297; | |
| n_0305 [label="TC"]; | |
| n_0307 [label="CARG(0)"]; | |
| n_0307 -> n_0305; | |
| n_0311 [label="CARG(0)"]; | |
| n_0311 -> n_0231; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(216)"]; | |
| n_0221 -> n_0219; | |
| n_0315 [label="CARG(0)"]; | |
| n_0315 -> n_0221; | |
| n_0319 [label="ARGLIST"]; | |
| n_0319 -> n_0307; | |
| n_0319 -> n_0311; | |
| n_0319 -> n_0315; | |
| n_0324 [label="CALLV"]; | |
| n_0324 -> n_0301; | |
| n_0324 -> n_0319; | |
| n_0328 [label="STORE(8)"]; | |
| n_0328 -> n_0221; | |
| n_0328 -> n_0231; | |
| n_0333 [label="IFV"]; | |
| n_0333 -> n_0276; | |
| n_0333 -> n_0324; | |
| n_0333 -> n_0328; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-51) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (tc) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (load (addr reg $ofs) $size) | |
| 45: (const $val $size) | |
| 46: (load (idx reg reg $scale) $size) | |
| 47: (store (addr reg $ofs) reg $size) | |
| 48: (local) | |
| 49: (nz (load (addr reg $ofs) $size)) | |
| 50: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [51-54) | |
| 51: (load (addr reg $ofs) $size) | |
| 52: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 53: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [54-58) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (nz (load (addr reg $ofs) $size)) | |
| 57: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [58-72) | |
| 58: (all flag) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (load (addr reg $ofs) $size) | |
| 62: (tc) | |
| 63: (carg reg) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (carg reg) | |
| 66: (local) | |
| 67: (addr reg $ofs) | |
| 68: (carg reg) | |
| 69: (arglist c_arg) | |
| 70: (callv (load (addr reg $ofs) $sz) c_args) | |
| 71: (branch :after) | |
| -> { 8 } | |
| Block{7} [72-75) | |
| 72: (label :fail) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [75-77) | |
| 75: (branch :after) | |
| 76: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(216)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(13, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(192)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(4, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(224)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(59)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0343 [label="STORE(8)"]; | |
| n_0343 -> n_0004; | |
| n_0343 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(152)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(4, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(80)"]; | |
| n_0184 -> n_0182; | |
| n_0192 [label="TC"]; | |
| n_0194 [label="ADDR(432)"]; | |
| n_0194 -> n_0192; | |
| n_0198 [label="LOAD(8)"]; | |
| n_0198 -> n_0194; | |
| n_0202 [label="ADDR(120)"]; | |
| n_0202 -> n_0198; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0188 [label="CONST(15, 2)"]; | |
| n_0210 [label="IDX(8)"]; | |
| n_0210 -> n_0206; | |
| n_0210 -> n_0188; | |
| n_0215 [label="LOAD(8):obj"]; | |
| n_0215 -> n_0210; | |
| n_0338 [label="STORE(8)"]; | |
| n_0338 -> n_0184; | |
| n_0338 -> n_0215; | |
| n_0225 [label="LOCAL"]; | |
| n_0227 [label="ADDR(8)"]; | |
| n_0227 -> n_0225; | |
| n_0231 [label="LOAD(8):obj"]; | |
| n_0231 -> n_0227; | |
| n_0235 [label="NZ:obj"]; | |
| n_0235 -> n_0231; | |
| n_0238 [label="ADDR(12)"]; | |
| n_0238 -> n_0231; | |
| n_0242 [label="LOAD(2)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CONST(1, 2)"]; | |
| n_0250 [label="AND"]; | |
| n_0250 -> n_0242; | |
| n_0250 -> n_0246; | |
| n_0254 [label="ZR"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(16)"]; | |
| n_0257 -> n_0231; | |
| n_0261 [label="LOAD(8)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="ADDR(64)"]; | |
| n_0265 -> n_0261; | |
| n_0269 [label="LOAD(8)"]; | |
| n_0269 -> n_0265; | |
| n_0273 [label="NZ"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ALL"]; | |
| n_0276 -> n_0235; | |
| n_0276 -> n_0254; | |
| n_0276 -> n_0273; | |
| n_0281 [label="ADDR(16)"]; | |
| n_0281 -> n_0231; | |
| n_0285 [label="LOAD(8)"]; | |
| n_0285 -> n_0281; | |
| n_0289 [label="ADDR(64)"]; | |
| n_0289 -> n_0285; | |
| n_0293 [label="LOAD(8)"]; | |
| n_0293 -> n_0289; | |
| n_0297 [label="ADDR(8)"]; | |
| n_0297 -> n_0293; | |
| n_0301 [label="LOAD(8)"]; | |
| n_0301 -> n_0297; | |
| n_0305 [label="TC"]; | |
| n_0307 [label="CARG(0)"]; | |
| n_0307 -> n_0305; | |
| n_0311 [label="CARG(0)"]; | |
| n_0311 -> n_0231; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(232)"]; | |
| n_0221 -> n_0219; | |
| n_0315 [label="CARG(0)"]; | |
| n_0315 -> n_0221; | |
| n_0319 [label="ARGLIST"]; | |
| n_0319 -> n_0307; | |
| n_0319 -> n_0311; | |
| n_0319 -> n_0315; | |
| n_0324 [label="CALLV"]; | |
| n_0324 -> n_0301; | |
| n_0324 -> n_0319; | |
| n_0328 [label="STORE(8)"]; | |
| n_0328 -> n_0221; | |
| n_0328 -> n_0231; | |
| n_0333 [label="IFV"]; | |
| n_0333 -> n_0276; | |
| n_0333 -> n_0324; | |
| n_0333 -> n_0328; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-51) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (tc) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (load (addr reg $ofs) $size) | |
| 45: (const $val $size) | |
| 46: (load (idx reg reg $scale) $size) | |
| 47: (store (addr reg $ofs) reg $size) | |
| 48: (local) | |
| 49: (nz (load (addr reg $ofs) $size)) | |
| 50: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [51-54) | |
| 51: (load (addr reg $ofs) $size) | |
| 52: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 53: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [54-58) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (nz (load (addr reg $ofs) $size)) | |
| 57: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [58-72) | |
| 58: (all flag) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (load (addr reg $ofs) $size) | |
| 62: (tc) | |
| 63: (carg reg) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (carg reg) | |
| 66: (local) | |
| 67: (addr reg $ofs) | |
| 68: (carg reg) | |
| 69: (arglist c_arg) | |
| 70: (callv (load (addr reg $ofs) $sz) c_args) | |
| 71: (branch :after) | |
| -> { 8 } | |
| Block{7} [72-75) | |
| 72: (label :fail) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [75-77) | |
| 75: (branch :after) | |
| 76: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(232)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(16, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(216)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(5, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(240)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(65)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0343 [label="STORE(8)"]; | |
| n_0343 -> n_0004; | |
| n_0343 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(152)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(4, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(80)"]; | |
| n_0184 -> n_0182; | |
| n_0192 [label="TC"]; | |
| n_0194 [label="ADDR(432)"]; | |
| n_0194 -> n_0192; | |
| n_0198 [label="LOAD(8)"]; | |
| n_0198 -> n_0194; | |
| n_0202 [label="ADDR(120)"]; | |
| n_0202 -> n_0198; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0188 [label="CONST(18, 2)"]; | |
| n_0210 [label="IDX(8)"]; | |
| n_0210 -> n_0206; | |
| n_0210 -> n_0188; | |
| n_0215 [label="LOAD(8):obj"]; | |
| n_0215 -> n_0210; | |
| n_0338 [label="STORE(8)"]; | |
| n_0338 -> n_0184; | |
| n_0338 -> n_0215; | |
| n_0225 [label="LOCAL"]; | |
| n_0227 [label="ADDR(8)"]; | |
| n_0227 -> n_0225; | |
| n_0231 [label="LOAD(8):obj"]; | |
| n_0231 -> n_0227; | |
| n_0235 [label="NZ:obj"]; | |
| n_0235 -> n_0231; | |
| n_0238 [label="ADDR(12)"]; | |
| n_0238 -> n_0231; | |
| n_0242 [label="LOAD(2)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CONST(1, 2)"]; | |
| n_0250 [label="AND"]; | |
| n_0250 -> n_0242; | |
| n_0250 -> n_0246; | |
| n_0254 [label="ZR"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(16)"]; | |
| n_0257 -> n_0231; | |
| n_0261 [label="LOAD(8)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="ADDR(64)"]; | |
| n_0265 -> n_0261; | |
| n_0269 [label="LOAD(8)"]; | |
| n_0269 -> n_0265; | |
| n_0273 [label="NZ"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ALL"]; | |
| n_0276 -> n_0235; | |
| n_0276 -> n_0254; | |
| n_0276 -> n_0273; | |
| n_0281 [label="ADDR(16)"]; | |
| n_0281 -> n_0231; | |
| n_0285 [label="LOAD(8)"]; | |
| n_0285 -> n_0281; | |
| n_0289 [label="ADDR(64)"]; | |
| n_0289 -> n_0285; | |
| n_0293 [label="LOAD(8)"]; | |
| n_0293 -> n_0289; | |
| n_0297 [label="ADDR(8)"]; | |
| n_0297 -> n_0293; | |
| n_0301 [label="LOAD(8)"]; | |
| n_0301 -> n_0297; | |
| n_0305 [label="TC"]; | |
| n_0307 [label="CARG(0)"]; | |
| n_0307 -> n_0305; | |
| n_0311 [label="CARG(0)"]; | |
| n_0311 -> n_0231; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(248)"]; | |
| n_0221 -> n_0219; | |
| n_0315 [label="CARG(0)"]; | |
| n_0315 -> n_0221; | |
| n_0319 [label="ARGLIST"]; | |
| n_0319 -> n_0307; | |
| n_0319 -> n_0311; | |
| n_0319 -> n_0315; | |
| n_0324 [label="CALLV"]; | |
| n_0324 -> n_0301; | |
| n_0324 -> n_0319; | |
| n_0328 [label="STORE(8)"]; | |
| n_0328 -> n_0221; | |
| n_0328 -> n_0231; | |
| n_0333 [label="IFV"]; | |
| n_0333 -> n_0276; | |
| n_0333 -> n_0324; | |
| n_0333 -> n_0328; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-51) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (tc) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (load (addr reg $ofs) $size) | |
| 45: (const $val $size) | |
| 46: (load (idx reg reg $scale) $size) | |
| 47: (store (addr reg $ofs) reg $size) | |
| 48: (local) | |
| 49: (nz (load (addr reg $ofs) $size)) | |
| 50: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [51-54) | |
| 51: (load (addr reg $ofs) $size) | |
| 52: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 53: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [54-58) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (nz (load (addr reg $ofs) $size)) | |
| 57: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [58-72) | |
| 58: (all flag) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (load (addr reg $ofs) $size) | |
| 62: (tc) | |
| 63: (carg reg) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (carg reg) | |
| 66: (local) | |
| 67: (addr reg $ofs) | |
| 68: (carg reg) | |
| 69: (arglist c_arg) | |
| 70: (callv (load (addr reg $ofs) $sz) c_args) | |
| 71: (branch :after) | |
| -> { 8 } | |
| Block{7} [72-75) | |
| 72: (label :fail) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [75-77) | |
| 75: (branch :after) | |
| 76: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(248)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(19, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(232)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(6, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(256)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(71)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0343 [label="STORE(8)"]; | |
| n_0343 -> n_0004; | |
| n_0343 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(152)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(4, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(80)"]; | |
| n_0184 -> n_0182; | |
| n_0192 [label="TC"]; | |
| n_0194 [label="ADDR(432)"]; | |
| n_0194 -> n_0192; | |
| n_0198 [label="LOAD(8)"]; | |
| n_0198 -> n_0194; | |
| n_0202 [label="ADDR(120)"]; | |
| n_0202 -> n_0198; | |
| n_0206 [label="LOAD(8)"]; | |
| n_0206 -> n_0202; | |
| n_0188 [label="CONST(21, 2)"]; | |
| n_0210 [label="IDX(8)"]; | |
| n_0210 -> n_0206; | |
| n_0210 -> n_0188; | |
| n_0215 [label="LOAD(8):obj"]; | |
| n_0215 -> n_0210; | |
| n_0338 [label="STORE(8)"]; | |
| n_0338 -> n_0184; | |
| n_0338 -> n_0215; | |
| n_0225 [label="LOCAL"]; | |
| n_0227 [label="ADDR(8)"]; | |
| n_0227 -> n_0225; | |
| n_0231 [label="LOAD(8):obj"]; | |
| n_0231 -> n_0227; | |
| n_0235 [label="NZ:obj"]; | |
| n_0235 -> n_0231; | |
| n_0238 [label="ADDR(12)"]; | |
| n_0238 -> n_0231; | |
| n_0242 [label="LOAD(2)"]; | |
| n_0242 -> n_0238; | |
| n_0246 [label="CONST(1, 2)"]; | |
| n_0250 [label="AND"]; | |
| n_0250 -> n_0242; | |
| n_0250 -> n_0246; | |
| n_0254 [label="ZR"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(16)"]; | |
| n_0257 -> n_0231; | |
| n_0261 [label="LOAD(8)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="ADDR(64)"]; | |
| n_0265 -> n_0261; | |
| n_0269 [label="LOAD(8)"]; | |
| n_0269 -> n_0265; | |
| n_0273 [label="NZ"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ALL"]; | |
| n_0276 -> n_0235; | |
| n_0276 -> n_0254; | |
| n_0276 -> n_0273; | |
| n_0281 [label="ADDR(16)"]; | |
| n_0281 -> n_0231; | |
| n_0285 [label="LOAD(8)"]; | |
| n_0285 -> n_0281; | |
| n_0289 [label="ADDR(64)"]; | |
| n_0289 -> n_0285; | |
| n_0293 [label="LOAD(8)"]; | |
| n_0293 -> n_0289; | |
| n_0297 [label="ADDR(8)"]; | |
| n_0297 -> n_0293; | |
| n_0301 [label="LOAD(8)"]; | |
| n_0301 -> n_0297; | |
| n_0305 [label="TC"]; | |
| n_0307 [label="CARG(0)"]; | |
| n_0307 -> n_0305; | |
| n_0311 [label="CARG(0)"]; | |
| n_0311 -> n_0231; | |
| n_0219 [label="LOCAL"]; | |
| n_0221 [label="ADDR(264)"]; | |
| n_0221 -> n_0219; | |
| n_0315 [label="CARG(0)"]; | |
| n_0315 -> n_0221; | |
| n_0319 [label="ARGLIST"]; | |
| n_0319 -> n_0307; | |
| n_0319 -> n_0311; | |
| n_0319 -> n_0315; | |
| n_0324 [label="CALLV"]; | |
| n_0324 -> n_0301; | |
| n_0324 -> n_0319; | |
| n_0328 [label="STORE(8)"]; | |
| n_0328 -> n_0221; | |
| n_0328 -> n_0231; | |
| n_0333 [label="IFV"]; | |
| n_0333 -> n_0276; | |
| n_0333 -> n_0324; | |
| n_0333 -> n_0328; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-51) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (tc) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (load (addr reg $ofs) $size) | |
| 45: (const $val $size) | |
| 46: (load (idx reg reg $scale) $size) | |
| 47: (store (addr reg $ofs) reg $size) | |
| 48: (local) | |
| 49: (nz (load (addr reg $ofs) $size)) | |
| 50: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [51-54) | |
| 51: (load (addr reg $ofs) $size) | |
| 52: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 53: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [54-58) | |
| 54: (load (addr reg $ofs) $size) | |
| 55: (load (addr reg $ofs) $size) | |
| 56: (nz (load (addr reg $ofs) $size)) | |
| 57: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [58-72) | |
| 58: (all flag) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (load (addr reg $ofs) $size) | |
| 62: (tc) | |
| 63: (carg reg) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (carg reg) | |
| 66: (local) | |
| 67: (addr reg $ofs) | |
| 68: (carg reg) | |
| 69: (arglist c_arg) | |
| 70: (callv (load (addr reg $ofs) $sz) c_args) | |
| 71: (branch :after) | |
| -> { 8 } | |
| Block{7} [72-75) | |
| 72: (label :fail) | |
| 73: (load (addr reg $ofs) $size) | |
| 74: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [75-77) | |
| 75: (branch :after) | |
| 76: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(264)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(22, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(248)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(7, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(272)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(77)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0367 [label="STORE(8)"]; | |
| n_0367 -> n_0004; | |
| n_0367 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(280)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(20, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(152)"]; | |
| n_0184 -> n_0182; | |
| n_0188 [label="LOCAL"]; | |
| n_0190 [label="ADDR(280)"]; | |
| n_0190 -> n_0188; | |
| n_0194 [label="LOAD(8):uint64"]; | |
| n_0194 -> n_0190; | |
| n_0198 [label="COPY:int64"]; | |
| n_0198 -> n_0194; | |
| n_0362 [label="STORE(8)"]; | |
| n_0362 -> n_0184; | |
| n_0362 -> n_0198; | |
| n_0201 [label="LOCAL"]; | |
| n_0203 [label="ADDR(80)"]; | |
| n_0203 -> n_0201; | |
| n_0211 [label="TC"]; | |
| n_0213 [label="ADDR(432)"]; | |
| n_0213 -> n_0211; | |
| n_0217 [label="LOAD(8)"]; | |
| n_0217 -> n_0213; | |
| n_0221 [label="ADDR(120)"]; | |
| n_0221 -> n_0217; | |
| n_0225 [label="LOAD(8)"]; | |
| n_0225 -> n_0221; | |
| n_0207 [label="CONST(24, 2)"]; | |
| n_0229 [label="IDX(8)"]; | |
| n_0229 -> n_0225; | |
| n_0229 -> n_0207; | |
| n_0234 [label="LOAD(8):obj"]; | |
| n_0234 -> n_0229; | |
| n_0357 [label="STORE(8)"]; | |
| n_0357 -> n_0203; | |
| n_0357 -> n_0234; | |
| n_0244 [label="LOCAL"]; | |
| n_0246 [label="ADDR(8)"]; | |
| n_0246 -> n_0244; | |
| n_0250 [label="LOAD(8):obj"]; | |
| n_0250 -> n_0246; | |
| n_0254 [label="NZ:obj"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(12)"]; | |
| n_0257 -> n_0250; | |
| n_0261 [label="LOAD(2)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="CONST(1, 2)"]; | |
| n_0269 [label="AND"]; | |
| n_0269 -> n_0261; | |
| n_0269 -> n_0265; | |
| n_0273 [label="ZR"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ADDR(16)"]; | |
| n_0276 -> n_0250; | |
| n_0280 [label="LOAD(8)"]; | |
| n_0280 -> n_0276; | |
| n_0284 [label="ADDR(64)"]; | |
| n_0284 -> n_0280; | |
| n_0288 [label="LOAD(8)"]; | |
| n_0288 -> n_0284; | |
| n_0292 [label="NZ"]; | |
| n_0292 -> n_0288; | |
| n_0295 [label="ALL"]; | |
| n_0295 -> n_0254; | |
| n_0295 -> n_0273; | |
| n_0295 -> n_0292; | |
| n_0300 [label="ADDR(16)"]; | |
| n_0300 -> n_0250; | |
| n_0304 [label="LOAD(8)"]; | |
| n_0304 -> n_0300; | |
| n_0308 [label="ADDR(64)"]; | |
| n_0308 -> n_0304; | |
| n_0312 [label="LOAD(8)"]; | |
| n_0312 -> n_0308; | |
| n_0316 [label="ADDR(8)"]; | |
| n_0316 -> n_0312; | |
| n_0320 [label="LOAD(8)"]; | |
| n_0320 -> n_0316; | |
| n_0324 [label="TC"]; | |
| n_0326 [label="CARG(0)"]; | |
| n_0326 -> n_0324; | |
| n_0330 [label="CARG(0)"]; | |
| n_0330 -> n_0250; | |
| n_0238 [label="LOCAL"]; | |
| n_0240 [label="ADDR(288)"]; | |
| n_0240 -> n_0238; | |
| n_0334 [label="CARG(0)"]; | |
| n_0334 -> n_0240; | |
| n_0338 [label="ARGLIST"]; | |
| n_0338 -> n_0326; | |
| n_0338 -> n_0330; | |
| n_0338 -> n_0334; | |
| n_0343 [label="CALLV"]; | |
| n_0343 -> n_0320; | |
| n_0343 -> n_0338; | |
| n_0347 [label="STORE(8)"]; | |
| n_0347 -> n_0240; | |
| n_0347 -> n_0250; | |
| n_0352 [label="IFV"]; | |
| n_0352 -> n_0295; | |
| n_0352 -> n_0343; | |
| n_0352 -> n_0347; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-56) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (local) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (copy reg) | |
| 45: (store (addr reg $ofs) reg $size) | |
| 46: (local) | |
| 47: (tc) | |
| 48: (load (addr reg $ofs) $size) | |
| 49: (load (addr reg $ofs) $size) | |
| 50: (const $val $size) | |
| 51: (load (idx reg reg $scale) $size) | |
| 52: (store (addr reg $ofs) reg $size) | |
| 53: (local) | |
| 54: (nz (load (addr reg $ofs) $size)) | |
| 55: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [56-59) | |
| 56: (load (addr reg $ofs) $size) | |
| 57: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 58: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [59-63) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (nz (load (addr reg $ofs) $size)) | |
| 62: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [63-77) | |
| 63: (all flag) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (load (addr reg $ofs) $size) | |
| 66: (load (addr reg $ofs) $size) | |
| 67: (tc) | |
| 68: (carg reg) | |
| 69: (load (addr reg $ofs) $size) | |
| 70: (carg reg) | |
| 71: (local) | |
| 72: (addr reg $ofs) | |
| 73: (carg reg) | |
| 74: (arglist c_arg) | |
| 75: (callv (load (addr reg $ofs) $sz) c_args) | |
| 76: (branch :after) | |
| -> { 8 } | |
| Block{7} [77-80) | |
| 77: (label :fail) | |
| 78: (load (addr reg $ofs) $size) | |
| 79: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [80-82) | |
| 80: (branch :after) | |
| 81: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(288)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(25, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(264)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(8, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(296)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(83)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0367 [label="STORE(8)"]; | |
| n_0367 -> n_0004; | |
| n_0367 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(280)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(20, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(152)"]; | |
| n_0184 -> n_0182; | |
| n_0188 [label="LOCAL"]; | |
| n_0190 [label="ADDR(280)"]; | |
| n_0190 -> n_0188; | |
| n_0194 [label="LOAD(8):uint64"]; | |
| n_0194 -> n_0190; | |
| n_0198 [label="COPY:int64"]; | |
| n_0198 -> n_0194; | |
| n_0362 [label="STORE(8)"]; | |
| n_0362 -> n_0184; | |
| n_0362 -> n_0198; | |
| n_0201 [label="LOCAL"]; | |
| n_0203 [label="ADDR(80)"]; | |
| n_0203 -> n_0201; | |
| n_0211 [label="TC"]; | |
| n_0213 [label="ADDR(432)"]; | |
| n_0213 -> n_0211; | |
| n_0217 [label="LOAD(8)"]; | |
| n_0217 -> n_0213; | |
| n_0221 [label="ADDR(120)"]; | |
| n_0221 -> n_0217; | |
| n_0225 [label="LOAD(8)"]; | |
| n_0225 -> n_0221; | |
| n_0207 [label="CONST(27, 2)"]; | |
| n_0229 [label="IDX(8)"]; | |
| n_0229 -> n_0225; | |
| n_0229 -> n_0207; | |
| n_0234 [label="LOAD(8):obj"]; | |
| n_0234 -> n_0229; | |
| n_0357 [label="STORE(8)"]; | |
| n_0357 -> n_0203; | |
| n_0357 -> n_0234; | |
| n_0244 [label="LOCAL"]; | |
| n_0246 [label="ADDR(8)"]; | |
| n_0246 -> n_0244; | |
| n_0250 [label="LOAD(8):obj"]; | |
| n_0250 -> n_0246; | |
| n_0254 [label="NZ:obj"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(12)"]; | |
| n_0257 -> n_0250; | |
| n_0261 [label="LOAD(2)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="CONST(1, 2)"]; | |
| n_0269 [label="AND"]; | |
| n_0269 -> n_0261; | |
| n_0269 -> n_0265; | |
| n_0273 [label="ZR"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ADDR(16)"]; | |
| n_0276 -> n_0250; | |
| n_0280 [label="LOAD(8)"]; | |
| n_0280 -> n_0276; | |
| n_0284 [label="ADDR(64)"]; | |
| n_0284 -> n_0280; | |
| n_0288 [label="LOAD(8)"]; | |
| n_0288 -> n_0284; | |
| n_0292 [label="NZ"]; | |
| n_0292 -> n_0288; | |
| n_0295 [label="ALL"]; | |
| n_0295 -> n_0254; | |
| n_0295 -> n_0273; | |
| n_0295 -> n_0292; | |
| n_0300 [label="ADDR(16)"]; | |
| n_0300 -> n_0250; | |
| n_0304 [label="LOAD(8)"]; | |
| n_0304 -> n_0300; | |
| n_0308 [label="ADDR(64)"]; | |
| n_0308 -> n_0304; | |
| n_0312 [label="LOAD(8)"]; | |
| n_0312 -> n_0308; | |
| n_0316 [label="ADDR(8)"]; | |
| n_0316 -> n_0312; | |
| n_0320 [label="LOAD(8)"]; | |
| n_0320 -> n_0316; | |
| n_0324 [label="TC"]; | |
| n_0326 [label="CARG(0)"]; | |
| n_0326 -> n_0324; | |
| n_0330 [label="CARG(0)"]; | |
| n_0330 -> n_0250; | |
| n_0238 [label="LOCAL"]; | |
| n_0240 [label="ADDR(304)"]; | |
| n_0240 -> n_0238; | |
| n_0334 [label="CARG(0)"]; | |
| n_0334 -> n_0240; | |
| n_0338 [label="ARGLIST"]; | |
| n_0338 -> n_0326; | |
| n_0338 -> n_0330; | |
| n_0338 -> n_0334; | |
| n_0343 [label="CALLV"]; | |
| n_0343 -> n_0320; | |
| n_0343 -> n_0338; | |
| n_0347 [label="STORE(8)"]; | |
| n_0347 -> n_0240; | |
| n_0347 -> n_0250; | |
| n_0352 [label="IFV"]; | |
| n_0352 -> n_0295; | |
| n_0352 -> n_0343; | |
| n_0352 -> n_0347; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-56) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (local) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (copy reg) | |
| 45: (store (addr reg $ofs) reg $size) | |
| 46: (local) | |
| 47: (tc) | |
| 48: (load (addr reg $ofs) $size) | |
| 49: (load (addr reg $ofs) $size) | |
| 50: (const $val $size) | |
| 51: (load (idx reg reg $scale) $size) | |
| 52: (store (addr reg $ofs) reg $size) | |
| 53: (local) | |
| 54: (nz (load (addr reg $ofs) $size)) | |
| 55: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [56-59) | |
| 56: (load (addr reg $ofs) $size) | |
| 57: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 58: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [59-63) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (nz (load (addr reg $ofs) $size)) | |
| 62: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [63-77) | |
| 63: (all flag) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (load (addr reg $ofs) $size) | |
| 66: (load (addr reg $ofs) $size) | |
| 67: (tc) | |
| 68: (carg reg) | |
| 69: (load (addr reg $ofs) $size) | |
| 70: (carg reg) | |
| 71: (local) | |
| 72: (addr reg $ofs) | |
| 73: (carg reg) | |
| 74: (arglist c_arg) | |
| 75: (callv (load (addr reg $ofs) $sz) c_args) | |
| 76: (branch :after) | |
| -> { 8 } | |
| Block{7} [77-80) | |
| 77: (label :fail) | |
| 78: (load (addr reg $ofs) $size) | |
| 79: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [80-82) | |
| 80: (branch :after) | |
| 81: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(304)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(28, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(288)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(9, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(312)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(89)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0367 [label="STORE(8)"]; | |
| n_0367 -> n_0004; | |
| n_0367 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(280)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(20, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(152)"]; | |
| n_0184 -> n_0182; | |
| n_0188 [label="LOCAL"]; | |
| n_0190 [label="ADDR(280)"]; | |
| n_0190 -> n_0188; | |
| n_0194 [label="LOAD(8):uint64"]; | |
| n_0194 -> n_0190; | |
| n_0198 [label="COPY:int64"]; | |
| n_0198 -> n_0194; | |
| n_0362 [label="STORE(8)"]; | |
| n_0362 -> n_0184; | |
| n_0362 -> n_0198; | |
| n_0201 [label="LOCAL"]; | |
| n_0203 [label="ADDR(80)"]; | |
| n_0203 -> n_0201; | |
| n_0211 [label="TC"]; | |
| n_0213 [label="ADDR(432)"]; | |
| n_0213 -> n_0211; | |
| n_0217 [label="LOAD(8)"]; | |
| n_0217 -> n_0213; | |
| n_0221 [label="ADDR(120)"]; | |
| n_0221 -> n_0217; | |
| n_0225 [label="LOAD(8)"]; | |
| n_0225 -> n_0221; | |
| n_0207 [label="CONST(30, 2)"]; | |
| n_0229 [label="IDX(8)"]; | |
| n_0229 -> n_0225; | |
| n_0229 -> n_0207; | |
| n_0234 [label="LOAD(8):obj"]; | |
| n_0234 -> n_0229; | |
| n_0357 [label="STORE(8)"]; | |
| n_0357 -> n_0203; | |
| n_0357 -> n_0234; | |
| n_0244 [label="LOCAL"]; | |
| n_0246 [label="ADDR(8)"]; | |
| n_0246 -> n_0244; | |
| n_0250 [label="LOAD(8):obj"]; | |
| n_0250 -> n_0246; | |
| n_0254 [label="NZ:obj"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(12)"]; | |
| n_0257 -> n_0250; | |
| n_0261 [label="LOAD(2)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="CONST(1, 2)"]; | |
| n_0269 [label="AND"]; | |
| n_0269 -> n_0261; | |
| n_0269 -> n_0265; | |
| n_0273 [label="ZR"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ADDR(16)"]; | |
| n_0276 -> n_0250; | |
| n_0280 [label="LOAD(8)"]; | |
| n_0280 -> n_0276; | |
| n_0284 [label="ADDR(64)"]; | |
| n_0284 -> n_0280; | |
| n_0288 [label="LOAD(8)"]; | |
| n_0288 -> n_0284; | |
| n_0292 [label="NZ"]; | |
| n_0292 -> n_0288; | |
| n_0295 [label="ALL"]; | |
| n_0295 -> n_0254; | |
| n_0295 -> n_0273; | |
| n_0295 -> n_0292; | |
| n_0300 [label="ADDR(16)"]; | |
| n_0300 -> n_0250; | |
| n_0304 [label="LOAD(8)"]; | |
| n_0304 -> n_0300; | |
| n_0308 [label="ADDR(64)"]; | |
| n_0308 -> n_0304; | |
| n_0312 [label="LOAD(8)"]; | |
| n_0312 -> n_0308; | |
| n_0316 [label="ADDR(8)"]; | |
| n_0316 -> n_0312; | |
| n_0320 [label="LOAD(8)"]; | |
| n_0320 -> n_0316; | |
| n_0324 [label="TC"]; | |
| n_0326 [label="CARG(0)"]; | |
| n_0326 -> n_0324; | |
| n_0330 [label="CARG(0)"]; | |
| n_0330 -> n_0250; | |
| n_0238 [label="LOCAL"]; | |
| n_0240 [label="ADDR(320)"]; | |
| n_0240 -> n_0238; | |
| n_0334 [label="CARG(0)"]; | |
| n_0334 -> n_0240; | |
| n_0338 [label="ARGLIST"]; | |
| n_0338 -> n_0326; | |
| n_0338 -> n_0330; | |
| n_0338 -> n_0334; | |
| n_0343 [label="CALLV"]; | |
| n_0343 -> n_0320; | |
| n_0343 -> n_0338; | |
| n_0347 [label="STORE(8)"]; | |
| n_0347 -> n_0240; | |
| n_0347 -> n_0250; | |
| n_0352 [label="IFV"]; | |
| n_0352 -> n_0295; | |
| n_0352 -> n_0343; | |
| n_0352 -> n_0347; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-56) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (local) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (copy reg) | |
| 45: (store (addr reg $ofs) reg $size) | |
| 46: (local) | |
| 47: (tc) | |
| 48: (load (addr reg $ofs) $size) | |
| 49: (load (addr reg $ofs) $size) | |
| 50: (const $val $size) | |
| 51: (load (idx reg reg $scale) $size) | |
| 52: (store (addr reg $ofs) reg $size) | |
| 53: (local) | |
| 54: (nz (load (addr reg $ofs) $size)) | |
| 55: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [56-59) | |
| 56: (load (addr reg $ofs) $size) | |
| 57: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 58: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [59-63) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (nz (load (addr reg $ofs) $size)) | |
| 62: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [63-77) | |
| 63: (all flag) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (load (addr reg $ofs) $size) | |
| 66: (load (addr reg $ofs) $size) | |
| 67: (tc) | |
| 68: (carg reg) | |
| 69: (load (addr reg $ofs) $size) | |
| 70: (carg reg) | |
| 71: (local) | |
| 72: (addr reg $ofs) | |
| 73: (carg reg) | |
| 74: (arglist c_arg) | |
| 75: (callv (load (addr reg $ofs) $sz) c_args) | |
| 76: (branch :after) | |
| -> { 8 } | |
| Block{7} [77-80) | |
| 77: (label :fail) | |
| 78: (load (addr reg $ofs) $size) | |
| 79: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [80-82) | |
| 80: (branch :after) | |
| 81: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(320)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0026 [label="ADDR(16)"]; | |
| n_0026 -> n_0014; | |
| n_0030 [label="LOAD(8)"]; | |
| n_0030 -> n_0026; | |
| n_0034 [label="TC"]; | |
| n_0036 [label="ADDR(432)"]; | |
| n_0036 -> n_0034; | |
| n_0040 [label="LOAD(8)"]; | |
| n_0040 -> n_0036; | |
| n_0044 [label="ADDR(120)"]; | |
| n_0044 -> n_0040; | |
| n_0048 [label="LOAD(8)"]; | |
| n_0048 -> n_0044; | |
| n_0022 [label="CONST(31, 2)"]; | |
| n_0052 [label="IDX(8)"]; | |
| n_0052 -> n_0048; | |
| n_0052 -> n_0022; | |
| n_0057 [label="LOAD(8)"]; | |
| n_0057 -> n_0052; | |
| n_0061 [label="EQ"]; | |
| n_0061 -> n_0030; | |
| n_0061 -> n_0057; | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(304)"]; | |
| n_0004 -> n_0002; | |
| n_0065 [label="TC"]; | |
| n_0067 [label="ADDR(432)"]; | |
| n_0067 -> n_0065; | |
| n_0071 [label="LOAD(8)"]; | |
| n_0071 -> n_0067; | |
| n_0075 [label="ADDR(120)"]; | |
| n_0075 -> n_0071; | |
| n_0079 [label="LOAD(8)"]; | |
| n_0079 -> n_0075; | |
| n_0083 [label="CONST(1, 8)"]; | |
| n_0087 [label="ADD"]; | |
| n_0087 -> n_0022; | |
| n_0087 -> n_0083; | |
| n_0091 [label="IDX(8)"]; | |
| n_0091 -> n_0079; | |
| n_0091 -> n_0087; | |
| n_0096 [label="LOAD(8)"]; | |
| n_0096 -> n_0091; | |
| n_0100 [label="STORE(8)"]; | |
| n_0100 -> n_0004; | |
| n_0100 -> n_0096; | |
| n_0105 [label="CONST_PTR(0)"]; | |
| n_0108 [label="TC"]; | |
| n_0110 [label="CARG(0)"]; | |
| n_0110 -> n_0108; | |
| n_0114 [label="CARG(0)"]; | |
| n_0114 -> n_0014; | |
| n_0118 [label="CU"]; | |
| n_0120 [label="ADDR(104)"]; | |
| n_0120 -> n_0118; | |
| n_0124 [label="LOAD(8)"]; | |
| n_0124 -> n_0120; | |
| n_0018 [label="CONST(629, 4)"]; | |
| n_0128 [label="IDX(8)"]; | |
| n_0128 -> n_0124; | |
| n_0128 -> n_0018; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0128; | |
| n_0137 [label="DISCARD"]; | |
| n_0137 -> n_0133; | |
| n_0140 [label="NZ"]; | |
| n_0140 -> n_0133; | |
| n_0143 [label="CONST_PTR(1)"]; | |
| n_0146 [label="TC"]; | |
| n_0148 [label="CARG(0)"]; | |
| n_0148 -> n_0146; | |
| n_0152 [label="CARG(0)"]; | |
| n_0152 -> n_0118; | |
| n_0156 [label="CARG(1)"]; | |
| n_0156 -> n_0018; | |
| n_0160 [label="ARGLIST"]; | |
| n_0160 -> n_0148; | |
| n_0160 -> n_0152; | |
| n_0160 -> n_0156; | |
| n_0165 [label="CALL(8)"]; | |
| n_0165 -> n_0143; | |
| n_0165 -> n_0160; | |
| n_0170 [label="IF"]; | |
| n_0170 -> n_0140; | |
| n_0170 -> n_0133; | |
| n_0170 -> n_0165; | |
| n_0175 [label="DO"]; | |
| n_0175 -> n_0137; | |
| n_0175 -> n_0170; | |
| n_0179 [label="CARG(0)"]; | |
| n_0179 -> n_0175; | |
| n_0183 [label="CARG(1)"]; | |
| n_0183 -> n_0022; | |
| n_0187 [label="CARG(0)"]; | |
| n_0187 -> n_0004; | |
| n_0191 [label="ARGLIST"]; | |
| n_0191 -> n_0110; | |
| n_0191 -> n_0114; | |
| n_0191 -> n_0179; | |
| n_0191 -> n_0183; | |
| n_0191 -> n_0187; | |
| n_0198 [label="CALLV"]; | |
| n_0198 -> n_0105; | |
| n_0198 -> n_0191; | |
| n_0202 [label="IFV"]; | |
| n_0202 -> n_0061; | |
| n_0202 -> n_0100; | |
| n_0202 -> n_0198; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-10) | |
| 0: (local) | |
| 1: (load (addr reg $ofs) $size) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (tc) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (load (addr reg $ofs) $size) | |
| 6: (const $val $size) | |
| 7: (load (idx reg reg $scale) $size) | |
| 8: (eq reg reg) | |
| 9: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [10-18) | |
| 10: (local) | |
| 11: (tc) | |
| 12: (load (addr reg $ofs) $size) | |
| 13: (load (addr reg $ofs) $size) | |
| 14: (add reg (const $val $size)) | |
| 15: (load (idx reg reg $scale) $size) | |
| 16: (store (addr reg $ofs) reg $size) | |
| 17: (branch :after) | |
| -> { 6 } | |
| Block{2} [18-29) | |
| 18: (label :fail) | |
| 19: (tc) | |
| 20: (carg reg) | |
| 21: (carg reg) | |
| 22: (cu) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (const $val $size) | |
| 25: (load (idx reg reg $scale) $size) | |
| 26: (discard reg) | |
| 27: (nz (load (idx reg reg $scl) $size)) | |
| 28: (conditional-branch: fail) | |
| -> { 3, 4 } | |
| Block{3} [29-30) | |
| 29: (branch :after) | |
| -> { 5 } | |
| Block{4} [30-37) | |
| 30: (label :fail) | |
| 31: (tc) | |
| 32: (carg reg) | |
| 33: (carg reg) | |
| 34: (carg reg) | |
| 35: (arglist c_arg) | |
| 36: (call (const_ptr $ptr) c_args $size) | |
| -> { 5 } | |
| Block{5} [37-46) | |
| 37: (branch :after) | |
| 38: (if flag reg) | |
| 39: (do void reg) | |
| 40: (carg reg) | |
| 41: (carg reg) | |
| 42: (addr reg $ofs) | |
| 43: (carg reg) | |
| 44: (arglist c_arg) | |
| 45: (callv (const_ptr $ptr) c_args) | |
| -> { 6 } | |
| Block{6} [46-48) | |
| 46: (branch :after) | |
| 47: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LABEL(97)"]; | |
| n_0005 [label="BRANCH"]; | |
| n_0005 -> n_0002; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-1) | |
| 0: (branch (label $name)) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(80)"]; | |
| n_0004 -> n_0002; | |
| n_0008 [label="LOCAL"]; | |
| n_0010 [label="ADDR(144)"]; | |
| n_0010 -> n_0008; | |
| n_0014 [label="LOAD(8):obj"]; | |
| n_0014 -> n_0010; | |
| n_0018 [label="COPY:obj"]; | |
| n_0018 -> n_0014; | |
| n_0021 [label="STORE(8)"]; | |
| n_0021 -> n_0004; | |
| n_0021 -> n_0018; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-5) | |
| 0: (local) | |
| 1: (local) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (copy reg) | |
| 4: (store (addr reg $ofs) reg $size) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0008 [label="CONST(10, 2)"]; | |
| n_0012 [label="COPY:int64"]; | |
| n_0012 -> n_0008; | |
| n_0015 [label="LOCAL"]; | |
| n_0017 [label="ADDR(328)"]; | |
| n_0017 -> n_0015; | |
| n_0021 [label="LOCAL"]; | |
| n_0023 [label="ADDR(152)"]; | |
| n_0023 -> n_0021; | |
| n_0027 [label="LOAD(8):int64"]; | |
| n_0027 -> n_0023; | |
| n_0056 [label="SCAST(8, 2)"]; | |
| n_0056 -> n_0012; | |
| n_0031 [label="EQ:int64"]; | |
| n_0031 -> n_0027; | |
| n_0031 -> n_0056; | |
| n_0035 [label="FLAGVAL:int64"]; | |
| n_0035 -> n_0031; | |
| n_0051 [label="STORE(8)"]; | |
| n_0051 -> n_0017; | |
| n_0051 -> n_0035; | |
| n_0041 [label="ZR:int64"]; | |
| n_0041 -> n_0035; | |
| n_0038 [label="LABEL(95)"]; | |
| n_0044 [label="BRANCH"]; | |
| n_0044 -> n_0038; | |
| n_0047 [label="WHEN"]; | |
| n_0047 -> n_0041; | |
| n_0047 -> n_0044; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-11) | |
| 0: (const $val $size) | |
| 1: (copy reg) | |
| 2: (local) | |
| 3: (local) | |
| 4: (load (addr reg $ofs) $size) | |
| 5: (scast reg $to_size $from_size) | |
| 6: (eq reg reg) | |
| 7: (flagval flag) | |
| 8: (store (addr reg $ofs) reg $size) | |
| 9: (zr reg) | |
| 10: (branch :fail) | |
| -> { 1, 2 } | |
| Block{1} [11-12) | |
| 11: (branch (label $name)) | |
| -> { 2 } | |
| Block{2} [12-14) | |
| 12: (label :fail) | |
| 13: (when flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT: Starting dump of JIT expression tree | |
| ========================================= | |
| digraph { | |
| n_0002 [label="LOCAL"]; | |
| n_0004 [label="ADDR(208)"]; | |
| n_0004 -> n_0002; | |
| n_0012 [label="CU"]; | |
| n_0014 [label="ADDR(104)"]; | |
| n_0014 -> n_0012; | |
| n_0018 [label="LOAD(8)"]; | |
| n_0018 -> n_0014; | |
| n_0008 [label="CONST(630, 4)"]; | |
| n_0022 [label="IDX(8)"]; | |
| n_0022 -> n_0018; | |
| n_0022 -> n_0008; | |
| n_0027 [label="LOAD(8)"]; | |
| n_0027 -> n_0022; | |
| n_0031 [label="DISCARD"]; | |
| n_0031 -> n_0027; | |
| n_0034 [label="NZ"]; | |
| n_0034 -> n_0027; | |
| n_0037 [label="CONST_PTR(0)"]; | |
| n_0040 [label="TC"]; | |
| n_0042 [label="CARG(0)"]; | |
| n_0042 -> n_0040; | |
| n_0046 [label="CARG(0)"]; | |
| n_0046 -> n_0012; | |
| n_0050 [label="CARG(1)"]; | |
| n_0050 -> n_0008; | |
| n_0054 [label="ARGLIST"]; | |
| n_0054 -> n_0042; | |
| n_0054 -> n_0046; | |
| n_0054 -> n_0050; | |
| n_0059 [label="CALL(8)"]; | |
| n_0059 -> n_0037; | |
| n_0059 -> n_0054; | |
| n_0064 [label="IF"]; | |
| n_0064 -> n_0034; | |
| n_0064 -> n_0027; | |
| n_0064 -> n_0059; | |
| n_0069 [label="DO:str"]; | |
| n_0069 -> n_0031; | |
| n_0069 -> n_0064; | |
| n_0367 [label="STORE(8)"]; | |
| n_0367 -> n_0004; | |
| n_0367 -> n_0069; | |
| n_0079 [label="LOCAL"]; | |
| n_0081 [label="ADDR(104)"]; | |
| n_0081 -> n_0079; | |
| n_0085 [label="LOAD(8):obj"]; | |
| n_0085 -> n_0081; | |
| n_0099 [label="ADDR(16)"]; | |
| n_0099 -> n_0085; | |
| n_0103 [label="LOAD(8)"]; | |
| n_0103 -> n_0099; | |
| n_0107 [label="ADDR(16)"]; | |
| n_0107 -> n_0103; | |
| n_0111 [label="LOAD(8)"]; | |
| n_0111 -> n_0107; | |
| n_0115 [label="ADDR(288)"]; | |
| n_0115 -> n_0111; | |
| n_0119 [label="LOAD(8)"]; | |
| n_0119 -> n_0115; | |
| n_0123 [label="TC"]; | |
| n_0125 [label="CARG(0)"]; | |
| n_0125 -> n_0123; | |
| n_0129 [label="ADDR(16)"]; | |
| n_0129 -> n_0085; | |
| n_0133 [label="LOAD(8)"]; | |
| n_0133 -> n_0129; | |
| n_0137 [label="CARG(0)"]; | |
| n_0137 -> n_0133; | |
| n_0141 [label="CARG(0)"]; | |
| n_0141 -> n_0085; | |
| n_0145 [label="ADDR(24)"]; | |
| n_0145 -> n_0085; | |
| n_0149 [label="CARG(0)"]; | |
| n_0149 -> n_0145; | |
| n_0089 [label="LOCAL"]; | |
| n_0091 [label="ADDR(136)"]; | |
| n_0091 -> n_0089; | |
| n_0095 [label="LOAD(8):str"]; | |
| n_0095 -> n_0091; | |
| n_0153 [label="CARG(0)"]; | |
| n_0153 -> n_0095; | |
| n_0073 [label="LOCAL"]; | |
| n_0075 [label="ADDR(280)"]; | |
| n_0075 -> n_0073; | |
| n_0157 [label="CARG(0)"]; | |
| n_0157 -> n_0075; | |
| n_0161 [label="CONST(20, 8)"]; | |
| n_0165 [label="CARG(1)"]; | |
| n_0165 -> n_0161; | |
| n_0169 [label="ARGLIST"]; | |
| n_0169 -> n_0125; | |
| n_0169 -> n_0137; | |
| n_0169 -> n_0141; | |
| n_0169 -> n_0149; | |
| n_0169 -> n_0153; | |
| n_0169 -> n_0157; | |
| n_0169 -> n_0165; | |
| n_0178 [label="CALLV"]; | |
| n_0178 -> n_0119; | |
| n_0178 -> n_0169; | |
| n_0182 [label="LOCAL"]; | |
| n_0184 [label="ADDR(152)"]; | |
| n_0184 -> n_0182; | |
| n_0188 [label="LOCAL"]; | |
| n_0190 [label="ADDR(280)"]; | |
| n_0190 -> n_0188; | |
| n_0194 [label="LOAD(8):uint64"]; | |
| n_0194 -> n_0190; | |
| n_0198 [label="COPY:int64"]; | |
| n_0198 -> n_0194; | |
| n_0362 [label="STORE(8)"]; | |
| n_0362 -> n_0184; | |
| n_0362 -> n_0198; | |
| n_0201 [label="LOCAL"]; | |
| n_0203 [label="ADDR(80)"]; | |
| n_0203 -> n_0201; | |
| n_0211 [label="TC"]; | |
| n_0213 [label="ADDR(432)"]; | |
| n_0213 -> n_0211; | |
| n_0217 [label="LOAD(8)"]; | |
| n_0217 -> n_0213; | |
| n_0221 [label="ADDR(120)"]; | |
| n_0221 -> n_0217; | |
| n_0225 [label="LOAD(8)"]; | |
| n_0225 -> n_0221; | |
| n_0207 [label="CONST(33, 2)"]; | |
| n_0229 [label="IDX(8)"]; | |
| n_0229 -> n_0225; | |
| n_0229 -> n_0207; | |
| n_0234 [label="LOAD(8):obj"]; | |
| n_0234 -> n_0229; | |
| n_0357 [label="STORE(8)"]; | |
| n_0357 -> n_0203; | |
| n_0357 -> n_0234; | |
| n_0244 [label="LOCAL"]; | |
| n_0246 [label="ADDR(8)"]; | |
| n_0246 -> n_0244; | |
| n_0250 [label="LOAD(8):obj"]; | |
| n_0250 -> n_0246; | |
| n_0254 [label="NZ:obj"]; | |
| n_0254 -> n_0250; | |
| n_0257 [label="ADDR(12)"]; | |
| n_0257 -> n_0250; | |
| n_0261 [label="LOAD(2)"]; | |
| n_0261 -> n_0257; | |
| n_0265 [label="CONST(1, 2)"]; | |
| n_0269 [label="AND"]; | |
| n_0269 -> n_0261; | |
| n_0269 -> n_0265; | |
| n_0273 [label="ZR"]; | |
| n_0273 -> n_0269; | |
| n_0276 [label="ADDR(16)"]; | |
| n_0276 -> n_0250; | |
| n_0280 [label="LOAD(8)"]; | |
| n_0280 -> n_0276; | |
| n_0284 [label="ADDR(64)"]; | |
| n_0284 -> n_0280; | |
| n_0288 [label="LOAD(8)"]; | |
| n_0288 -> n_0284; | |
| n_0292 [label="NZ"]; | |
| n_0292 -> n_0288; | |
| n_0295 [label="ALL"]; | |
| n_0295 -> n_0254; | |
| n_0295 -> n_0273; | |
| n_0295 -> n_0292; | |
| n_0300 [label="ADDR(16)"]; | |
| n_0300 -> n_0250; | |
| n_0304 [label="LOAD(8)"]; | |
| n_0304 -> n_0300; | |
| n_0308 [label="ADDR(64)"]; | |
| n_0308 -> n_0304; | |
| n_0312 [label="LOAD(8)"]; | |
| n_0312 -> n_0308; | |
| n_0316 [label="ADDR(8)"]; | |
| n_0316 -> n_0312; | |
| n_0320 [label="LOAD(8)"]; | |
| n_0320 -> n_0316; | |
| n_0324 [label="TC"]; | |
| n_0326 [label="CARG(0)"]; | |
| n_0326 -> n_0324; | |
| n_0330 [label="CARG(0)"]; | |
| n_0330 -> n_0250; | |
| n_0238 [label="LOCAL"]; | |
| n_0240 [label="ADDR(336)"]; | |
| n_0240 -> n_0238; | |
| n_0334 [label="CARG(0)"]; | |
| n_0334 -> n_0240; | |
| n_0338 [label="ARGLIST"]; | |
| n_0338 -> n_0326; | |
| n_0338 -> n_0330; | |
| n_0338 -> n_0334; | |
| n_0343 [label="CALLV"]; | |
| n_0343 -> n_0320; | |
| n_0343 -> n_0338; | |
| n_0347 [label="STORE(8)"]; | |
| n_0347 -> n_0240; | |
| n_0347 -> n_0250; | |
| n_0352 [label="IFV"]; | |
| n_0352 -> n_0295; | |
| n_0352 -> n_0343; | |
| n_0352 -> n_0347; | |
| } | |
| End dump of JIT expression tree | |
| =============================== | |
| JIT: Starting tile list log | |
| =========================== | |
| Block{0} [0-8) | |
| 0: (local) | |
| 1: (cu) | |
| 2: (load (addr reg $ofs) $size) | |
| 3: (const $val $size) | |
| 4: (load (idx reg reg $scale) $size) | |
| 5: (discard reg) | |
| 6: (nz (load (idx reg reg $scl) $size)) | |
| 7: (conditional-branch: fail) | |
| -> { 1, 2 } | |
| Block{1} [8-9) | |
| 8: (branch :after) | |
| -> { 3 } | |
| Block{2} [9-16) | |
| 9: (label :fail) | |
| 10: (tc) | |
| 11: (carg reg) | |
| 12: (carg reg) | |
| 13: (carg reg) | |
| 14: (arglist c_arg) | |
| 15: (call (const_ptr $ptr) c_args $size) | |
| -> { 3 } | |
| Block{3} [16-56) | |
| 16: (branch :after) | |
| 17: (if flag reg) | |
| 18: (do void reg) | |
| 19: (store (addr reg $ofs) reg $size) | |
| 20: (local) | |
| 21: (load (addr reg $ofs) $size) | |
| 22: (load (addr reg $ofs) $size) | |
| 23: (load (addr reg $ofs) $size) | |
| 24: (tc) | |
| 25: (carg reg) | |
| 26: (load (addr reg $ofs) $size) | |
| 27: (carg reg) | |
| 28: (carg reg) | |
| 29: (addr reg $ofs) | |
| 30: (carg reg) | |
| 31: (local) | |
| 32: (load (addr reg $ofs) $size) | |
| 33: (carg reg) | |
| 34: (local) | |
| 35: (addr reg $ofs) | |
| 36: (carg reg) | |
| 37: (const $val $size) | |
| 38: (carg reg) | |
| 39: (arglist c_arg) | |
| 40: (callv (load (addr reg $ofs) $sz) c_args) | |
| 41: (local) | |
| 42: (local) | |
| 43: (load (addr reg $ofs) $size) | |
| 44: (copy reg) | |
| 45: (store (addr reg $ofs) reg $size) | |
| 46: (local) | |
| 47: (tc) | |
| 48: (load (addr reg $ofs) $size) | |
| 49: (load (addr reg $ofs) $size) | |
| 50: (const $val $size) | |
| 51: (load (idx reg reg $scale) $size) | |
| 52: (store (addr reg $ofs) reg $size) | |
| 53: (local) | |
| 54: (nz (load (addr reg $ofs) $size)) | |
| 55: (conditional-branch :fail) | |
| -> { 4, 7 } | |
| Block{4} [56-59) | |
| 56: (load (addr reg $ofs) $size) | |
| 57: (zr (and (load (addr reg $ofs) $size) (const $val $size))) | |
| 58: (conditional-branch :fail) | |
| -> { 5, 7 } | |
| Block{5} [59-63) | |
| 59: (load (addr reg $ofs) $size) | |
| 60: (load (addr reg $ofs) $size) | |
| 61: (nz (load (addr reg $ofs) $size)) | |
| 62: (conditional-branch :fail) | |
| -> { 6, 7 } | |
| Block{6} [63-77) | |
| 63: (all flag) | |
| 64: (load (addr reg $ofs) $size) | |
| 65: (load (addr reg $ofs) $size) | |
| 66: (load (addr reg $ofs) $size) | |
| 67: (tc) | |
| 68: (carg reg) | |
| 69: (load (addr reg $ofs) $size) | |
| 70: (carg reg) | |
| 71: (local) | |
| 72: (addr reg $ofs) | |
| 73: (carg reg) | |
| 74: (arglist c_arg) | |
| 75: (callv (load (addr reg $ofs) $sz) c_args) | |
| 76: (branch :after) | |
| -> { 8 } | |
| Block{7} [77-80) | |
| 77: (label :fail) | |
| 78: (load (addr reg $ofs) $size) | |
| 79: (store (addr reg $ofs) reg $size) | |
| -> { 8 } | |
| Block{8} [80-82) | |
| 80: (branch :after) | |
| 81: (ifv flag void) | |
| -> {} | |
| End of tile list log | |
| ==================== | |
| JIT Spilled: 5 offset 160 | |
| r0 [160] = obj | |
| r1 [168] = unknown | |
| r2 [170] = unknown | |
| r3 [178] = str | |
| r4 [180] = obj | |
| After: | |
| Spesh of 'SET_BLOCK_OUTER_CTX' (cuid: 103, file: gen/moar/stage2/NQPHLL.nqp:1499) | |
| Callsite 0x7f844c1156c0 (2 args, 2 pos) | |
| Positional flags: obj, obj | |
| BB 0 (0x7f84440399a8): | |
| line: 1499 (pc 0) | |
| Instructions: | |
| no_op | |
| Successors: 1, 18, 22 | |
| Predecessors: | |
| Dominance children: 1, 17, 18, 20, 22, 98, 100 | |
| BB 1 (0x7f8444039a30): | |
| line: 1499 (pc 0) | |
| Instructions: | |
| null r7(1) # [024] start of exprjit tree | |
| null r8(1) | |
| null r9(1) | |
| null r15(1) | |
| null r16(1) | |
| null r18(1) | |
| null r24(1) | |
| null r27(1) | |
| null r29(1) | |
| null r31(1) | |
| null r33(1) | |
| null r36(1) | |
| null r38(1) | |
| null r40(1) | |
| sp_getarg_o r0(2), liti16(0) | |
| sp_getarg_o r1(2), liti16(1) | |
| [Annotation: Line Number: gen/moar/stage2/NQPHLL.nqp:1499] | |
| const_s r3(1), lits(%*COMPILING) | |
| getdynlex r4(2), r3(1) | |
| ifnonnull r4(2), BB(8) | |
| Successors: 8, 2 | |
| Predecessors: 0 | |
| Dominance children: 2, 8, 9 | |
| BB 2 (0x7f8444039a90): | |
| line: 1499 (pc 42) | |
| Instructions: | |
| wval r8(2), liti16(0), liti16(0) (not deserialized) # [025] start of exprjit tree | |
| getwho r7(2), r8(2) | |
| const_s r3(2), lits(%COMPILING) | |
| atkey_o r8(4), r7(2), r3(2) | |
| ifnonnull r8(4), BB(4) | |
| Successors: 4, 3 | |
| Predecessors: 1 | |
| Dominance children: 3, 4, 5 | |
| BB 3 (0x7f8444039af0): | |
| line: 1499 (pc 86) | |
| Instructions: | |
| const_s r3(3), lits(%COMPILING) # [026] start of exprjit tree | |
| sp_fastcreate r10(3), liti16(32), sslot(0) | |
| bindkey_o r7(2), r3(3), r10(3) | |
| set r9(2), r10(3) | |
| goto BB(5) | |
| Successors: 5 | |
| Predecessors: 2 | |
| Dominance children: | |
| BB 4 (0x7f8444039b50): | |
| line: 1499 (pc 124) | |
| Instructions: | |
| set r9(3), r8(4) # [027] start of exprjit tree | |
| Successors: 5 | |
| Predecessors: 2 | |
| Dominance children: | |
| BB 5 (0x7f8444039bb0): | |
| line: 1499 (pc 130) | |
| Instructions: | |
| PHI r9(4), r9(2), r9(3) | |
| set r6(2), r9(4) # [028] start of exprjit tree | |
| ifnonnull r9(4), BB(7) | |
| Successors: 7, 6 | |
| Predecessors: 3, 4 | |
| Dominance children: 6, 7 | |
| BB 6 (0x7f8444039c10): | |
| line: 1499 (pc 144) | |
| Instructions: | |
| const_s r3(5), lits(Contextual %*COMPILING not found) # [029] start of exprjit tree | |
| die r6(3), r3(5) | |
| Successors: 7 | |
| Predecessors: 5 | |
| Dominance children: 7 | |
| BB 7 (0x7f8444039cd0): | |
| line: 1499 (pc 164) | |
| Instructions: | |
| PHI r6(4), r6(2), r6(3) | |
| set r5(2), r6(4) # [030] start of exprjit tree | |
| goto BB(9) | |
| Successors: 9 | |
| Predecessors: 5, 6 | |
| Dominance children: | |
| BB 8 (0x7f8444039d30): | |
| line: 1499 (pc 176) | |
| Instructions: | |
| set r5(3), r4(2) # [031] start of exprjit tree | |
| Successors: 9 | |
| Predecessors: 1 | |
| Dominance children: | |
| BB 9 (0x7f8444039d90): | |
| line: 1499 (pc 182) | |
| Instructions: | |
| PHI r9(5), r9(4), r9(1) | |
| PHI r8(5), r8(4), r8(1) | |
| PHI r7(3), r7(2), r7(1) | |
| PHI r5(4), r5(2), r5(3) | |
| const_s r3(8), lits(%?OPTIONS) # [032] start of exprjit tree | |
| atkey_o r5(5), r5(4), r3(8) | |
| ifnonnull r5(5), BB(11) | |
| Successors: 11, 10 | |
| Predecessors: 7, 8 | |
| Dominance children: 10, 11, 12 | |
| BB 10 (0x7f8444039df0): | |
| line: 1499 (pc 206) | |
| Instructions: | |
| sp_getspeshslot r6(6), sslot(1) # [033] start of exprjit tree | |
| goto BB(12) | |
| Successors: 12 | |
| Predecessors: 9 | |
| Dominance children: | |
| BB 11 (0x7f8444039e50): | |
| line: 1499 (pc 226) | |
| Instructions: | |
| set r6(7), r5(5) # [034] start of exprjit tree | |
| Successors: 12 | |
| Predecessors: 9 | |
| Dominance children: | |
| BB 12 (0x7f8444039eb0): | |
| line: 1499 (pc 232) | |
| Instructions: | |
| PHI r6(8), r6(6), r6(7) | |
| const_s r3(9), lits(outer_ctx) # [035] start of exprjit tree | |
| atkey_o r6(9), r6(8), r3(9) | |
| ifnonnull r6(9), BB(14) | |
| Successors: 14, 13 | |
| Predecessors: 10, 11 | |
| Dominance children: 13, 14, 15 | |
| BB 13 (0x7f8444039f10): | |
| line: 1499 (pc 256) | |
| Instructions: | |
| sp_getspeshslot r4(5), sslot(1) # [036] start of exprjit tree | |
| goto BB(15) | |
| Successors: 15 | |
| Predecessors: 12 | |
| Dominance children: | |
| BB 14 (0x7f8444039f70): | |
| line: 1499 (pc 276) | |
| Instructions: | |
| set r4(6), r6(9) # [037] start of exprjit tree | |
| Successors: 15 | |
| Predecessors: 12 | |
| Dominance children: | |
| BB 15 (0x7f8444039fd0): | |
| line: 1499 (pc 282) | |
| Instructions: | |
| PHI r4(7), r4(5), r4(6) | |
| set r2(2), r4(7) # [038] start of exprjit tree | |
| [Annotation: INS Deopt One (idx 0 -> pc 294; line 1499)] | |
| [Annotation: Logged (bytecode offset 288)] | |
| sp_decont r4(8), r2(2) | |
| isconcrete r11(1), r4(8) | |
| # [039] expr bail: Cannot get template for: sp_fastbox_i_ic | |
| # [022] box_i into a BOOTInt | |
| sp_fastbox_i_ic r42(3), liti16(32), sslot(36), liti16(24), r11(1), liti16(0) | |
| set r10(8), r42(3) | |
| unless_i r11(1), BB(100) | |
| Successors: 100, 16 | |
| Predecessors: 13, 14 | |
| Dominance children: 17 | |
| BB 16 (0x7f844403a090): | |
| line: 1501 (pc 326) | |
| Instructions: | |
| [Annotation: Line Number: gen/moar/stage2/NQPHLL.nqp:1501] | |
| null r4(9) # [040] start of exprjit tree | |
| Successors: 17 | |
| Predecessors: 15 | |
| Dominance children: | |
| BB 17 (0x7f844403a0f0): | |
| line: 1501 (pc 330) | |
| Instructions: | |
| PHI r42(4), r42(3), r42(10) | |
| PHI r41(1), r41(0), r41(8) | |
| PHI r40(2), r40(1), r40(10) | |
| PHI r39(1), r39(0), r39(8) | |
| PHI r38(2), r38(1), r38(10) | |
| PHI r37(1), r37(0), r37(8) | |
| PHI r36(2), r36(1), r36(10) | |
| PHI r35(1), r35(0), r35(10) | |
| PHI r34(1), r34(0), r34(8) | |
| PHI r33(2), r33(1), r33(10) | |
| PHI r32(1), r32(0), r32(8) | |
| PHI r31(2), r31(1), r31(10) | |
| PHI r30(1), r30(0), r30(8) | |
| PHI r29(2), r29(1), r29(10) | |
| PHI r28(1), r28(0), r28(8) | |
| PHI r27(2), r27(1), r27(10) | |
| PHI r26(1), r26(0), r26(15) | |
| PHI r25(1), r25(0), r25(8) | |
| PHI r24(2), r24(1), r24(10) | |
| PHI r23(1), r23(0), r23(7) | |
| PHI r22(1), r22(0), r22(8) | |
| PHI r21(1), r21(0), r21(8) | |
| PHI r20(1), r20(0), r20(8) | |
| PHI r19(1), r19(0), r19(26) | |
| PHI r18(2), r18(1), r18(8) | |
| PHI r17(1), r17(0), r17(6) | |
| PHI r16(2), r16(1), r16(7) | |
| PHI r15(2), r15(1), r15(7) | |
| PHI r11(2), r11(1), r11(6) | |
| PHI r10(9), r10(8), r10(39) | |
| PHI r9(6), r9(5), r9(13) | |
| PHI r8(6), r8(5), r8(14) | |
| PHI r7(4), r7(3), r7(8) | |
| PHI r6(10), r6(9), r6(21) | |
| PHI r4(10), r4(9), r4(14) | |
| PHI r3(10), r3(9), r3(20) | |
| PHI r2(3), r2(2), r2(8) | |
| PHI r1(3), r1(2), r1(7) | |
| PHI r0(3), r0(2), r0(7) | |
| isnull r12(2), r2(3) # [041] start of exprjit tree | |
| if_i r12(2), BB(99) | |
| Successors: 99, 18 | |
| Predecessors: 16, 98 | |
| Dominance children: 99 | |
| BB 18 (0x7f844403a150): | |
| line: 1501 (pc 344) | |
| Instructions: | |
| PHI r42(5), r42(0), r42(4) | |
| PHI r41(2), r41(0), r41(1) | |
| PHI r40(3), r40(0), r40(2) | |
| PHI r39(2), r39(0), r39(1) | |
| PHI r38(3), r38(0), r38(2) | |
| PHI r37(2), r37(0), r37(1) | |
| PHI r36(3), r36(0), r36(2) | |
| PHI r35(2), r35(0), r35(1) | |
| PHI r34(2), r34(0), r34(1) | |
| PHI r33(3), r33(0), r33(2) | |
| PHI r32(2), r32(0), r32(1) | |
| PHI r31(3), r31(0), r31(2) | |
| PHI r30(2), r30(0), r30(1) | |
| PHI r29(3), r29(0), r29(2) | |
| PHI r28(2), r28(0), r28(1) | |
| PHI r27(3), r27(0), r27(2) | |
| PHI r26(2), r26(0), r26(1) | |
| PHI r25(2), r25(0), r25(1) | |
| PHI r24(3), r24(0), r24(2) | |
| PHI r23(2), r23(0), r23(1) | |
| PHI r22(2), r22(0), r22(1) | |
| PHI r21(2), r21(0), r21(1) | |
| PHI r20(2), r20(0), r20(1) | |
| PHI r19(2), r19(0), r19(1) | |
| PHI r18(3), r18(0), r18(2) | |
| PHI r17(2), r17(0), r17(1) | |
| PHI r16(3), r16(0), r16(2) | |
| PHI r15(3), r15(0), r15(2) | |
| PHI r12(3), r12(0), r12(2) | |
| PHI r11(3), r11(0), r11(2) | |
| PHI r10(11), r10(0), r10(9) | |
| PHI r9(7), r9(0), r9(6) | |
| PHI r8(7), r8(0), r8(6) | |
| PHI r7(5), r7(0), r7(4) | |
| PHI r6(11), r6(0), r6(10) | |
| PHI r4(11), r4(0), r4(10) | |
| PHI r3(11), r3(0), r3(10) | |
| PHI r2(4), r2(0), r2(3) | |
| PHI r1(4), r1(0), r1(3) | |
| PHI r0(4), r0(0), r0(3) | |
| [Annotation: INS Deopt OSR (idx 1 -> pc 346); line 1502] | |
| ctxlexpad r13(4), r2(4) # [042] expr bail: Cannot get template for: ctxlexpad | |
| isnull r14(3), r13(4) | |
| if_i r14(3), BB(98) | |
| Successors: 98, 19 | |
| Predecessors: 0, 17 | |
| Dominance children: 19 | |
| BB 19 (0x7f844403a1b0): | |
| line: 1504 (pc 372) | |
| Instructions: | |
| iter r15(4), r13(4) # [043] start of exprjit tree | |
| Successors: 20 | |
| Predecessors: 18 | |
| Dominance children: | |
| BB 20 (0x7f844403a210): | |
| line: 1504 (pc 384) | |
| Instructions: | |
| PHI r42(6), r42(5), r42(6), r42(6), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(8), r42(8), r42(7), r42(7), r42(9) | |
| PHI r41(3), r41(2), r41(3), r41(3), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6), r41(6), r41(6), r41(6), r41(7) | |
| PHI r40(4), r40(3), r40(4), r40(4), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(6), r40(6), r40(5), r40(5), r40(5), r40(7), r40(8), r40(5), r40(5), r40(9) | |
| PHI r39(3), r39(2), r39(3), r39(3), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(7) | |
| PHI r38(4), r38(3), r38(4), r38(4), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(6), r38(6), r38(5), r38(5), r38(5), r38(7), r38(8), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(9) | |
| PHI r37(3), r37(2), r37(3), r37(3), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(7) | |
| PHI r36(4), r36(3), r36(4), r36(4), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(6), r36(6), r36(5), r36(5), r36(5), r36(7), r36(8), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(9) | |
| PHI r35(3), r35(2), r35(3), r35(3), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(5), r35(5), r35(4), r35(4), r35(6), r35(6), r35(6), r35(4), r35(4), r35(7), r35(7), r35(7), r35(4), r35(4), r35(8), r35(8), r35(8), r35(4), r35(4), r35(9) | |
| PHI r34(3), r34(2), r34(3), r34(3), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(7) | |
| PHI r33(4), r33(3), r33(4), r33(4), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(6), r33(6), r33(5), r33(5), r33(5), r33(7), r33(8), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(9) | |
| PHI r32(3), r32(2), r32(3), r32(3), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(7) | |
| PHI r31(4), r31(3), r31(4), r31(4), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(6), r31(6), r31(5), r31(5), r31(5), r31(7), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(9) | |
| PHI r30(3), r30(2), r30(3), r30(3), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(7) | |
| PHI r29(4), r29(3), r29(4), r29(4), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(6), r29(6), r29(5), r29(5), r29(5), r29(7), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(9) | |
| PHI r28(3), r28(2), r28(3), r28(3), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(7) | |
| PHI r27(4), r27(3), r27(4), r27(4), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(6), r27(6), r27(6), r27(5), r27(5), r27(5), r27(7), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(9) | |
| PHI r26(3), r26(2), r26(3), r26(3), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(5), r26(5), r26(5), r26(4), r26(4), r26(6), r26(6), r26(6), r26(4), r26(4), r26(7), r26(7), r26(7), r26(4), r26(4), r26(8), r26(8), r26(8), r26(4), r26(4), r26(9), r26(9), r26(9), r26(4), r26(4), r26(10), r26(10), r26(10), r26(4), r26(4), r26(11), r26(11), r26(11), r26(4), r26(4), r26(12), r26(12), r26(12), r26(4), r26(13), r26(14) | |
| PHI r25(3), r25(2), r25(3), r25(3), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(7) | |
| PHI r24(4), r24(3), r24(4), r24(4), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(6), r24(6), r24(6), r24(5), r24(5), r24(5), r24(7), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(9) | |
| PHI r23(3), r23(2), r23(3), r23(3), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(5), r23(5), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(6) | |
| PHI r22(3), r22(2), r22(3), r22(3), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(7) | |
| PHI r21(3), r21(2), r21(3), r21(3), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(7) | |
| PHI r20(3), r20(2), r20(3), r20(3), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(7) | |
| PHI r19(3), r19(2), r19(3), r19(3), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(5), r19(6), r19(6), r19(6), r19(6), r19(6), r19(7), r19(8), r19(8), r19(8), r19(7), r19(9), r19(9), r19(9), r19(9), r19(9), r19(10), r19(10), r19(10), r19(10), r19(10), r19(11), r19(12), r19(12), r19(12), r19(11), r19(13), r19(14), r19(14), r19(14), r19(13), r19(15), r19(16), r19(16), r19(16), r19(15), r19(17), r19(18), r19(18), r19(18), r19(17), r19(19), r19(20), r19(20), r19(20), r19(19), r19(21), r19(22), r19(22), r19(22), r19(21), r19(23), r19(24), r19(24), r19(24), r19(23), r19(23), r19(25) | |
| PHI r18(4), r18(3), r18(4), r18(4), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(7) | |
| PHI r17(3), r17(2), r17(3), r17(3), r17(4), r17(4), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5) | |
| PHI r16(4), r16(3), r16(4), r16(4), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6) | |
| PHI r15(5), r15(4), r15(5), r15(5), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6) | |
| PHI r14(4), r14(3), r14(4), r14(4), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5) | |
| PHI r13(5), r13(4), r13(5), r13(5), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6) | |
| PHI r12(4), r12(3), r12(4), r12(4), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5) | |
| PHI r11(4), r11(3), r11(4), r11(4), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5) | |
| PHI r10(12), r10(11), r10(12), r10(12), r10(13), r10(13), r10(13), r10(13), r10(13), r10(14), r10(14), r10(14), r10(14), r10(15), r10(15), r10(15), r10(16), r10(16), r10(17), r10(17), r10(17), r10(18), r10(18), r10(19), r10(19), r10(19), r10(20), r10(20), r10(21), r10(21), r10(21), r10(22), r10(22), r10(23), r10(23), r10(23), r10(24), r10(24), r10(25), r10(25), r10(25), r10(26), r10(26), r10(27), r10(27), r10(27), r10(28), r10(28), r10(29), r10(29), r10(29), r10(30), r10(30), r10(31), r10(31), r10(31), r10(32), r10(32), r10(33), r10(33), r10(33), r10(34), r10(34), r10(35), r10(35), r10(35), r10(37), r10(37), r10(38) | |
| PHI r9(8), r9(7), r9(8), r9(8), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(10), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(12) | |
| PHI r8(8), r8(7), r8(8), r8(8), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(10), r8(10), r8(10), r8(9), r8(9), r8(9), r8(11), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(13) | |
| PHI r7(6), r7(5), r7(6), r7(6), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7) | |
| PHI r6(12), r6(11), r6(12), r6(12), r6(13), r6(13), r6(14), r6(14), r6(14), r6(14), r6(14), r6(17), r6(17), r6(17), r6(18), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(20) | |
| PHI r4(12), r4(11), r4(12), r4(12), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13) | |
| PHI r3(12), r3(11), r3(12), r3(12), r3(13), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(15), r3(15), r3(15), r3(14), r3(14), r3(16), r3(16), r3(16), r3(14), r3(14), r3(17), r3(17), r3(17), r3(14), r3(14), r3(18), r3(18), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(19) | |
| PHI r2(5), r2(4), r2(5), r2(5), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6) | |
| PHI r1(5), r1(4), r1(5), r1(5), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6) | |
| PHI r0(5), r0(4), r0(5), r0(5), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6) | |
| [Annotation: FH Start (2)] | |
| [Annotation: FH Goto (1)] | |
| [Annotation: FH Start (1)] | |
| [Annotation: FH Start (0)] | |
| [Annotation: INS Deopt One (idx 2 -> pc 390; line 1504)] | |
| [Annotation: Logged (bytecode offset 384)] | |
| sp_decont r5(13), r15(5) # [044] start of exprjit tree | |
| Successors: 21, 22, 20, 98 | |
| Predecessors: 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33, 35, 37, 38, 39, 41, 43, 44, 45, 47, 49, 50, 51, 53, 55, 56, 57, 59, 61, 62, 63, 65, 67, 68, 69, 71, 73, 74, 75, 77, 79, 80, 81, 83, 85, 86, 87, 89, 91, 92, 93, 95, 96, 97 | |
| Dominance children: 21 | |
| BB 21 (0x7f844403a270): | |
| line: 1504 (pc 390) | |
| Instructions: | |
| istrue r43(0), r5(13) # [045] start of exprjit tree | |
| unless_i r43(0), BB(98) | |
| Successors: 98, 22, 20 | |
| Predecessors: 20 | |
| Dominance children: | |
| BB 22 (0x7f844403a2d0): | |
| line: 1504 (pc 398) | |
| Instructions: | |
| PHI r42(7), r42(0), r42(6), r42(6), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(8), r42(8), r42(7), r42(7) | |
| PHI r41(4), r41(0), r41(3), r41(3), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6), r41(6), r41(6), r41(6) | |
| PHI r40(5), r40(0), r40(4), r40(4), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(6), r40(6), r40(5), r40(5), r40(5), r40(7), r40(8), r40(5), r40(5) | |
| PHI r39(4), r39(0), r39(3), r39(3), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6) | |
| PHI r38(5), r38(0), r38(4), r38(4), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(6), r38(6), r38(5), r38(5), r38(5), r38(7), r38(8), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5) | |
| PHI r37(4), r37(0), r37(3), r37(3), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6) | |
| PHI r36(5), r36(0), r36(4), r36(4), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(6), r36(6), r36(5), r36(5), r36(5), r36(7), r36(8), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5) | |
| PHI r35(4), r35(0), r35(3), r35(3), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(5), r35(5), r35(4), r35(4), r35(6), r35(6), r35(6), r35(4), r35(4), r35(7), r35(7), r35(7), r35(4), r35(4), r35(8), r35(8), r35(8), r35(4), r35(4) | |
| PHI r34(4), r34(0), r34(3), r34(3), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6) | |
| PHI r33(5), r33(0), r33(4), r33(4), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(6), r33(6), r33(5), r33(5), r33(5), r33(7), r33(8), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5) | |
| PHI r32(4), r32(0), r32(3), r32(3), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6) | |
| PHI r31(5), r31(0), r31(4), r31(4), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(6), r31(6), r31(5), r31(5), r31(5), r31(7), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5) | |
| PHI r30(4), r30(0), r30(3), r30(3), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6) | |
| PHI r29(5), r29(0), r29(4), r29(4), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(6), r29(6), r29(5), r29(5), r29(5), r29(7), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5) | |
| PHI r28(4), r28(0), r28(3), r28(3), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6) | |
| PHI r27(5), r27(0), r27(4), r27(4), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(6), r27(6), r27(6), r27(5), r27(5), r27(5), r27(7), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5) | |
| PHI r26(4), r26(0), r26(3), r26(3), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(5), r26(5), r26(5), r26(4), r26(4), r26(6), r26(6), r26(6), r26(4), r26(4), r26(7), r26(7), r26(7), r26(4), r26(4), r26(8), r26(8), r26(8), r26(4), r26(4), r26(9), r26(9), r26(9), r26(4), r26(4), r26(10), r26(10), r26(10), r26(4), r26(4), r26(11), r26(11), r26(11), r26(4), r26(4), r26(12), r26(12), r26(12), r26(4), r26(13) | |
| PHI r25(4), r25(0), r25(3), r25(3), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6) | |
| PHI r24(5), r24(0), r24(4), r24(4), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(6), r24(6), r24(6), r24(5), r24(5), r24(5), r24(7), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5) | |
| PHI r23(4), r23(0), r23(3), r23(3), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(5), r23(5), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4) | |
| PHI r22(4), r22(0), r22(3), r22(3), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6) | |
| PHI r21(4), r21(0), r21(3), r21(3), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6) | |
| PHI r20(4), r20(0), r20(3), r20(3), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6) | |
| PHI r19(4), r19(0), r19(3), r19(3), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(5), r19(6), r19(6), r19(6), r19(6), r19(6), r19(7), r19(8), r19(8), r19(8), r19(7), r19(9), r19(9), r19(9), r19(9), r19(9), r19(10), r19(10), r19(10), r19(10), r19(10), r19(11), r19(12), r19(12), r19(12), r19(11), r19(13), r19(14), r19(14), r19(14), r19(13), r19(15), r19(16), r19(16), r19(16), r19(15), r19(17), r19(18), r19(18), r19(18), r19(17), r19(19), r19(20), r19(20), r19(20), r19(19), r19(21), r19(22), r19(22), r19(22), r19(21), r19(23), r19(24), r19(24), r19(24), r19(23), r19(23) | |
| PHI r18(5), r18(0), r18(4), r18(4), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6) | |
| PHI r17(4), r17(0), r17(3), r17(3), r17(4), r17(4), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5) | |
| PHI r15(6), r15(0), r15(5), r15(5), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6) | |
| PHI r14(5), r14(0), r14(4), r14(4), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5), r14(5) | |
| PHI r13(6), r13(0), r13(5), r13(5), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6), r13(6) | |
| PHI r12(5), r12(0), r12(4), r12(4), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5), r12(5) | |
| PHI r11(5), r11(0), r11(4), r11(4), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5) | |
| PHI r10(13), r10(0), r10(12), r10(12), r10(13), r10(13), r10(13), r10(13), r10(13), r10(14), r10(14), r10(14), r10(14), r10(15), r10(15), r10(15), r10(16), r10(16), r10(17), r10(17), r10(17), r10(18), r10(18), r10(19), r10(19), r10(19), r10(20), r10(20), r10(21), r10(21), r10(21), r10(22), r10(22), r10(23), r10(23), r10(23), r10(24), r10(24), r10(25), r10(25), r10(25), r10(26), r10(26), r10(27), r10(27), r10(27), r10(28), r10(28), r10(29), r10(29), r10(29), r10(30), r10(30), r10(31), r10(31), r10(31), r10(32), r10(32), r10(33), r10(33), r10(33), r10(34), r10(34), r10(35), r10(35), r10(35), r10(37), r10(37) | |
| PHI r9(9), r9(0), r9(8), r9(8), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(10), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9) | |
| PHI r8(9), r8(0), r8(8), r8(8), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(10), r8(10), r8(10), r8(9), r8(9), r8(9), r8(11), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9) | |
| PHI r7(7), r7(0), r7(6), r7(6), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7) | |
| PHI r6(13), r6(0), r6(12), r6(12), r6(13), r6(13), r6(14), r6(14), r6(14), r6(14), r6(14), r6(17), r6(17), r6(17), r6(18), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17) | |
| PHI r4(13), r4(0), r4(12), r4(12), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13) | |
| PHI r3(13), r3(0), r3(12), r3(12), r3(13), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(15), r3(15), r3(15), r3(14), r3(14), r3(16), r3(16), r3(16), r3(14), r3(14), r3(17), r3(17), r3(17), r3(14), r3(14), r3(18), r3(18), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14) | |
| PHI r2(6), r2(0), r2(5), r2(5), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6) | |
| PHI r1(6), r1(0), r1(5), r1(5), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6) | |
| PHI r0(6), r0(0), r0(5), r0(5), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6) | |
| [Annotation: INS Deopt OSR (idx 3 -> pc 400); line 1504] | |
| [Annotation: FH Goto (0)] | |
| shift_o r16(6), r15(6) # [046] start of exprjit tree | |
| [Annotation: INS Deopt One (idx 4 -> pc 418; line 1505)] | |
| [Annotation: Logged (bytecode offset 412)] | |
| sp_decont r5(16), r16(6) | |
| Successors: 23, 22, 20, 98 | |
| Predecessors: 0, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33, 35, 37, 38, 39, 41, 43, 44, 45, 47, 49, 50, 51, 53, 55, 56, 57, 59, 61, 62, 63, 65, 67, 68, 69, 71, 73, 74, 75, 77, 79, 80, 81, 83, 85, 86, 87, 89, 91, 92, 93, 95, 96 | |
| Dominance children: 23 | |
| BB 23 (0x7f844403a330): | |
| line: 1505 (pc 418) | |
| Instructions: | |
| smrt_strify r3(14), r5(16) # [047] start of exprjit tree | |
| Successors: 24, 22, 20, 98 | |
| Predecessors: 22 | |
| Dominance children: 24 | |
| BB 24 (0x7f844403a390): | |
| line: 1505 (pc 424) | |
| Instructions: | |
| set r17(5), r3(14) # [048] start of exprjit tree | |
| [Annotation: INS Deopt One (idx 5 -> pc 436; line 1505)] | |
| [Annotation: Logged (bytecode offset 430)] | |
| sp_decont r6(14), r1(6) | |
| Successors: 25, 22, 20, 98 | |
| Predecessors: 23 | |
| Dominance children: 25 | |
| BB 25 (0x7f844403a3f0): | |
| line: 1505 (pc 436) | |
| Instructions: | |
| sp_findmeth r5(17), r6(14), lits(symbol), sslot(2) # [049] start of exprjit tree | |
| Successors: 26, 22, 20, 98 | |
| Predecessors: 24 | |
| Dominance children: 26 | |
| BB 26 (0x7f844403a450): | |
| line: 1505 (pc 446) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 6 -> pc 446; line 1505)] | |
| prepargs callsite(0x7f844c1156a0, 2 arg, 2 pos, nonflattening, interned) # [050] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| [Annotation: INS Deopt All (idx 8 -> pc 468; line 1505)] | |
| [Annotation: INS Deopt One (idx 7 -> pc 468; line 1505)] | |
| [Annotation: Logged (bytecode offset 462)] | |
| invoke_o r5(18), r5(17) | |
| Successors: 27, 22, 20, 98 | |
| Predecessors: 25 | |
| Dominance children: 27 | |
| BB 27 (0x7f844403a4b0): | |
| line: 1505 (pc 468) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 9 -> pc 474; line 1505)] | |
| [Annotation: Logged (bytecode offset 468)] | |
| sp_decont r10(14), r5(18) # [051] start of exprjit tree | |
| Successors: 28, 22, 20, 98 | |
| Predecessors: 26 | |
| Dominance children: 28 | |
| BB 28 (0x7f844403a510): | |
| line: 1505 (pc 474) | |
| Instructions: | |
| istrue r43(1), r10(14) # [052] start of exprjit tree | |
| if_i r43(1), BB(97) | |
| Successors: 97, 29, 22, 20, 98 | |
| Predecessors: 27 | |
| Dominance children: 29, 97 | |
| BB 29 (0x7f844403a570): | |
| line: 1507 (pc 482) | |
| Instructions: | |
| lexprimspec r19(5), r13(6), r17(5) # [053] expr bail: Cannot get template for: lexprimspec | |
| sp_fastbox_i_ic r18(6), liti16(32), sslot(37), liti16(24), r19(5), liti16(0) # [023] box_i into a BOOTInt | |
| [Annotation: INS Deopt One (idx 10 -> pc 514; line 1507)] | |
| [Annotation: Logged (bytecode offset 508)] | |
| set r6(17), r18(6) | |
| # [001] unbox_i from a BOOTInt | |
| # [000] specialized from smrt_intify | |
| sp_get_i64 r19(6), r6(17), liti16(24) | |
| Successors: 30, 22, 20, 98 | |
| Predecessors: 28 | |
| Dominance children: 32 | |
| BB 30 (0x7f844403a630): | |
| line: 1507 (pc 520) | |
| Instructions: | |
| const_i64_16 r20(5), liti16(0) # [054] start of exprjit tree | |
| eq_i r20(6), r19(6), r20(5) | |
| unless_i r20(6), BB(35) | |
| Successors: 35, 31 | |
| Predecessors: 29 | |
| Dominance children: 31, 35 | |
| BB 31 (0x7f844403a690): | |
| line: 1510 (pc 542) | |
| Instructions: | |
| const_s r3(15), lits(lexical) # [055] start of exprjit tree | |
| [Annotation: INS Deopt One (idx 11 -> pc 556; line 1510)] | |
| [Annotation: Logged (bytecode offset 550)] | |
| sp_decont r10(15), r1(6) | |
| Successors: 32, 22, 20, 98 | |
| Predecessors: 30 | |
| Dominance children: 32 | |
| BB 32 (0x7f844403a6f0): | |
| line: 1510 (pc 556) | |
| Instructions: | |
| sp_findmeth r6(18), r10(15), lits(symbol), sslot(4) # [056] start of exprjit tree | |
| Successors: 33, 22, 20, 98 | |
| Predecessors: 31 | |
| Dominance children: 33 | |
| BB 33 (0x7f844403a750): | |
| line: 1510 (pc 566) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 12 -> pc 566; line 1510)] | |
| prepargs callsite(0x560f5bb9f6d0, 6 arg, 2 pos, nonflattening, interned) # [057] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(15) | |
| argconst_s liti16(4), lits(lazy_value_from) | |
| arg_o liti16(5), r13(6) | |
| [Annotation: INS Deopt All (idx 14 -> pc 616; line 1510)] | |
| [Annotation: INS Deopt One (idx 13 -> pc 616; line 1510)] | |
| [Annotation: Logged (bytecode offset 610)] | |
| invoke_o r6(19), r6(18) | |
| Successors: 34, 22, 20, 98 | |
| Predecessors: 32 | |
| Dominance children: 34 | |
| BB 34 (0x7f844403a7b0): | |
| line: 1510 (pc 616) | |
| Instructions: | |
| goto BB(97) # [058] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 33 | |
| Dominance children: | |
| BB 35 (0x7f844403a810): | |
| line: 1510 (pc 622) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 15 -> pc 628; line 1510)] | |
| [Annotation: Logged (bytecode offset 622)] | |
| set r10(16), r18(6) # [059] start of exprjit tree | |
| # [060] expr bail: Cannot get template for: sp_get_i64 | |
| # [003] unbox_i from a BOOTInt | |
| # [002] specialized from smrt_intify | |
| sp_get_i64 r19(7), r10(16), liti16(24) | |
| Successors: 36, 22, 20, 98 | |
| Predecessors: 30 | |
| Dominance children: 39 | |
| BB 36 (0x7f844403a8d0): | |
| line: 1510 (pc 634) | |
| Instructions: | |
| const_i64_16 r21(5), liti16(1) # [061] start of exprjit tree | |
| eq_i r21(6), r19(7), r21(5) | |
| unless_i r21(6), BB(41) | |
| Successors: 41, 37 | |
| Predecessors: 35 | |
| Dominance children: 37, 41 | |
| BB 37 (0x7f844403a930): | |
| line: 1514 (pc 656) | |
| Instructions: | |
| const_s r3(16), lits(lexical) # [062] start of exprjit tree | |
| atkey_i r19(8), r13(6), r17(5) | |
| sp_getspeshslot r10(17), sslot(6) | |
| [Annotation: INS Deopt One (idx 16 -> pc 686; line 1514)] | |
| [Annotation: Logged (bytecode offset 680)] | |
| sp_decont r8(10), r1(6) | |
| Successors: 38, 22, 20, 98 | |
| Predecessors: 36 | |
| Dominance children: 38 | |
| BB 38 (0x7f844403a990): | |
| line: 1514 (pc 686) | |
| Instructions: | |
| sp_findmeth r9(10), r8(10), lits(symbol), sslot(7) # [063] start of exprjit tree | |
| Successors: 39, 22, 20, 98 | |
| Predecessors: 37 | |
| Dominance children: 39 | |
| BB 39 (0x7f844403a9f0): | |
| line: 1514 (pc 696) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 17 -> pc 696; line 1514)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [064] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(16) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(8) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(17) | |
| [Annotation: INS Deopt All (idx 19 -> pc 760; line 1514)] | |
| [Annotation: INS Deopt One (idx 18 -> pc 760; line 1514)] | |
| [Annotation: Logged (bytecode offset 754)] | |
| invoke_o r9(11), r9(10) | |
| Successors: 40, 22, 20, 98 | |
| Predecessors: 38 | |
| Dominance children: 40 | |
| BB 40 (0x7f844403aa50): | |
| line: 1514 (pc 760) | |
| Instructions: | |
| goto BB(97) # [065] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 39 | |
| Dominance children: | |
| BB 41 (0x7f844403aab0): | |
| line: 1514 (pc 766) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 20 -> pc 772; line 1514)] | |
| [Annotation: Logged (bytecode offset 766)] | |
| set r10(18), r18(6) # [066] start of exprjit tree | |
| # [067] expr bail: Cannot get template for: sp_get_i64 | |
| # [005] unbox_i from a BOOTInt | |
| # [004] specialized from smrt_intify | |
| sp_get_i64 r19(9), r10(18), liti16(24) | |
| Successors: 42, 22, 20, 98 | |
| Predecessors: 36 | |
| Dominance children: 46 | |
| BB 42 (0x7f844403ab70): | |
| line: 1514 (pc 778) | |
| Instructions: | |
| const_i64_16 r22(5), liti16(2) # [068] start of exprjit tree | |
| eq_i r22(6), r19(9), r22(5) | |
| unless_i r22(6), BB(47) | |
| Successors: 47, 43 | |
| Predecessors: 41 | |
| Dominance children: 43, 47 | |
| BB 43 (0x7f844403abd0): | |
| line: 1518 (pc 800) | |
| Instructions: | |
| const_s r3(17), lits(lexical) # [069] start of exprjit tree | |
| atkey_n r23(5), r13(6), r17(5) | |
| sp_getspeshslot r10(19), sslot(9) | |
| [Annotation: INS Deopt One (idx 21 -> pc 830; line 1518)] | |
| [Annotation: Logged (bytecode offset 824)] | |
| sp_decont r24(6), r1(6) | |
| Successors: 44, 22, 20, 98 | |
| Predecessors: 42 | |
| Dominance children: 44 | |
| BB 44 (0x7f844403ac30): | |
| line: 1518 (pc 830) | |
| Instructions: | |
| sp_findmeth r8(11), r24(6), lits(symbol), sslot(10) # [070] start of exprjit tree | |
| Successors: 45, 22, 20, 98 | |
| Predecessors: 43 | |
| Dominance children: 45 | |
| BB 45 (0x7f844403ac90): | |
| line: 1518 (pc 840) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 22 -> pc 840; line 1518)] | |
| prepargs callsite(0x560f5bb9f7f0, 8 arg, 2 pos, nonflattening, interned) # [071] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(17) | |
| argconst_s liti16(4), lits(value) | |
| arg_n liti16(5), r23(5) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(19) | |
| [Annotation: INS Deopt All (idx 24 -> pc 904; line 1518)] | |
| [Annotation: INS Deopt One (idx 23 -> pc 904; line 1518)] | |
| [Annotation: Logged (bytecode offset 898)] | |
| invoke_o r8(12), r8(11) | |
| Successors: 46, 22, 20, 98 | |
| Predecessors: 44 | |
| Dominance children: 46 | |
| BB 46 (0x7f844403acf0): | |
| line: 1518 (pc 904) | |
| Instructions: | |
| goto BB(97) # [072] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 45 | |
| Dominance children: | |
| BB 47 (0x7f844403ad50): | |
| line: 1518 (pc 910) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 25 -> pc 916; line 1518)] | |
| [Annotation: Logged (bytecode offset 910)] | |
| set r10(20), r18(6) # [073] start of exprjit tree | |
| # [074] expr bail: Cannot get template for: sp_get_i64 | |
| # [007] unbox_i from a BOOTInt | |
| # [006] specialized from smrt_intify | |
| sp_get_i64 r19(10), r10(20), liti16(24) | |
| Successors: 48, 22, 20, 98 | |
| Predecessors: 42 | |
| Dominance children: 53 | |
| BB 48 (0x7f844403ae10): | |
| line: 1518 (pc 922) | |
| Instructions: | |
| const_i64_16 r25(5), liti16(3) # [075] start of exprjit tree | |
| eq_i r25(6), r19(10), r25(5) | |
| unless_i r25(6), BB(53) | |
| Successors: 53, 49 | |
| Predecessors: 47 | |
| Dominance children: 49, 53 | |
| BB 49 (0x7f844403ae70): | |
| line: 1522 (pc 944) | |
| Instructions: | |
| const_s r3(18), lits(lexical) # [076] start of exprjit tree | |
| atkey_s r26(5), r13(6), r17(5) | |
| sp_getspeshslot r10(21), sslot(12) | |
| [Annotation: INS Deopt One (idx 26 -> pc 974; line 1522)] | |
| [Annotation: Logged (bytecode offset 968)] | |
| sp_decont r27(6), r1(6) | |
| Successors: 50, 22, 20, 98 | |
| Predecessors: 48 | |
| Dominance children: 50 | |
| BB 50 (0x7f844403aed0): | |
| line: 1522 (pc 974) | |
| Instructions: | |
| sp_findmeth r24(7), r27(6), lits(symbol), sslot(13) # [077] start of exprjit tree | |
| Successors: 51, 22, 20, 98 | |
| Predecessors: 49 | |
| Dominance children: 51 | |
| BB 51 (0x7f844403af30): | |
| line: 1522 (pc 984) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 27 -> pc 984; line 1522)] | |
| prepargs callsite(0x560f5bb9f860, 8 arg, 2 pos, nonflattening, interned) # [078] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r3(18) | |
| argconst_s liti16(4), lits(value) | |
| arg_s liti16(5), r26(5) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(21) | |
| [Annotation: INS Deopt All (idx 29 -> pc 1048; line 1522)] | |
| [Annotation: INS Deopt One (idx 28 -> pc 1048; line 1522)] | |
| [Annotation: Logged (bytecode offset 1042)] | |
| invoke_o r24(8), r24(7) | |
| Successors: 52, 22, 20, 98 | |
| Predecessors: 50 | |
| Dominance children: 52 | |
| BB 52 (0x7f844403af90): | |
| line: 1522 (pc 1048) | |
| Instructions: | |
| goto BB(97) # [079] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 51 | |
| Dominance children: | |
| BB 53 (0x7f844403aff0): | |
| line: 1522 (pc 1054) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 30 -> pc 1060; line 1522)] | |
| [Annotation: Logged (bytecode offset 1054)] | |
| set r10(22), r18(6) # [080] start of exprjit tree | |
| # [081] expr bail: Cannot get template for: sp_get_i64 | |
| # [009] unbox_i from a BOOTInt | |
| # [008] specialized from smrt_intify | |
| sp_get_i64 r19(11), r10(22), liti16(24) | |
| Successors: 54, 22, 20, 98 | |
| Predecessors: 48 | |
| Dominance children: 60 | |
| BB 54 (0x7f844403b0b0): | |
| line: 1522 (pc 1066) | |
| Instructions: | |
| const_i64_16 r28(5), liti16(4) # [082] start of exprjit tree | |
| eq_i r28(6), r19(11), r28(5) | |
| unless_i r28(6), BB(59) | |
| Successors: 59, 55 | |
| Predecessors: 53 | |
| Dominance children: 55, 59 | |
| BB 55 (0x7f844403b110): | |
| line: 1526 (pc 1088) | |
| Instructions: | |
| const_s r26(6), lits(lexical) # [083] start of exprjit tree | |
| atkey_i r19(12), r13(6), r17(5) | |
| sp_getspeshslot r10(23), sslot(15) | |
| [Annotation: INS Deopt One (idx 31 -> pc 1118; line 1526)] | |
| [Annotation: Logged (bytecode offset 1112)] | |
| sp_decont r29(6), r1(6) | |
| Successors: 56, 22, 20, 98 | |
| Predecessors: 54 | |
| Dominance children: 56 | |
| BB 56 (0x7f844403b170): | |
| line: 1526 (pc 1118) | |
| Instructions: | |
| sp_findmeth r27(7), r29(6), lits(symbol), sslot(16) # [084] start of exprjit tree | |
| Successors: 57, 22, 20, 98 | |
| Predecessors: 55 | |
| Dominance children: 57 | |
| BB 57 (0x7f844403b1d0): | |
| line: 1526 (pc 1128) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 32 -> pc 1128; line 1526)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [085] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(6) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(12) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(23) | |
| [Annotation: INS Deopt All (idx 34 -> pc 1192; line 1526)] | |
| [Annotation: INS Deopt One (idx 33 -> pc 1192; line 1526)] | |
| [Annotation: Logged (bytecode offset 1186)] | |
| invoke_o r27(8), r27(7) | |
| Successors: 58, 22, 20, 98 | |
| Predecessors: 56 | |
| Dominance children: 58 | |
| BB 58 (0x7f844403b230): | |
| line: 1526 (pc 1192) | |
| Instructions: | |
| goto BB(97) # [086] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 57 | |
| Dominance children: | |
| BB 59 (0x7f844403b290): | |
| line: 1526 (pc 1198) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 35 -> pc 1204; line 1526)] | |
| [Annotation: Logged (bytecode offset 1198)] | |
| set r10(24), r18(6) # [087] start of exprjit tree | |
| # [088] expr bail: Cannot get template for: sp_get_i64 | |
| # [011] unbox_i from a BOOTInt | |
| # [010] specialized from smrt_intify | |
| sp_get_i64 r19(13), r10(24), liti16(24) | |
| Successors: 60, 22, 20, 98 | |
| Predecessors: 54 | |
| Dominance children: 67 | |
| BB 60 (0x7f844403b350): | |
| line: 1526 (pc 1210) | |
| Instructions: | |
| const_i64_16 r30(5), liti16(5) # [089] start of exprjit tree | |
| eq_i r30(6), r19(13), r30(5) | |
| unless_i r30(6), BB(65) | |
| Successors: 65, 61 | |
| Predecessors: 59 | |
| Dominance children: 61, 65 | |
| BB 61 (0x7f844403b3b0): | |
| line: 1530 (pc 1232) | |
| Instructions: | |
| const_s r26(7), lits(lexical) # [090] start of exprjit tree | |
| atkey_i r19(14), r13(6), r17(5) | |
| sp_getspeshslot r10(25), sslot(18) | |
| [Annotation: INS Deopt One (idx 36 -> pc 1262; line 1530)] | |
| [Annotation: Logged (bytecode offset 1256)] | |
| sp_decont r31(6), r1(6) | |
| Successors: 62, 22, 20, 98 | |
| Predecessors: 60 | |
| Dominance children: 62 | |
| BB 62 (0x7f844403b410): | |
| line: 1530 (pc 1262) | |
| Instructions: | |
| sp_findmeth r29(7), r31(6), lits(symbol), sslot(19) # [091] start of exprjit tree | |
| Successors: 63, 22, 20, 98 | |
| Predecessors: 61 | |
| Dominance children: 63 | |
| BB 63 (0x7f844403b470): | |
| line: 1530 (pc 1272) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 37 -> pc 1272; line 1530)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [092] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(7) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(14) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(25) | |
| [Annotation: INS Deopt All (idx 39 -> pc 1336; line 1530)] | |
| [Annotation: INS Deopt One (idx 38 -> pc 1336; line 1530)] | |
| [Annotation: Logged (bytecode offset 1330)] | |
| invoke_o r29(8), r29(7) | |
| Successors: 64, 22, 20, 98 | |
| Predecessors: 62 | |
| Dominance children: 64 | |
| BB 64 (0x7f844403b4d0): | |
| line: 1530 (pc 1336) | |
| Instructions: | |
| goto BB(97) # [093] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 63 | |
| Dominance children: | |
| BB 65 (0x7f844403b530): | |
| line: 1530 (pc 1342) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 40 -> pc 1348; line 1530)] | |
| [Annotation: Logged (bytecode offset 1342)] | |
| set r10(26), r18(6) # [094] start of exprjit tree | |
| # [095] expr bail: Cannot get template for: sp_get_i64 | |
| # [013] unbox_i from a BOOTInt | |
| # [012] specialized from smrt_intify | |
| sp_get_i64 r19(15), r10(26), liti16(24) | |
| Successors: 66, 22, 20, 98 | |
| Predecessors: 60 | |
| Dominance children: 74 | |
| BB 66 (0x7f844403b5f0): | |
| line: 1530 (pc 1354) | |
| Instructions: | |
| const_i64_16 r32(5), liti16(6) # [096] start of exprjit tree | |
| eq_i r32(6), r19(15), r32(5) | |
| unless_i r32(6), BB(71) | |
| Successors: 71, 67 | |
| Predecessors: 65 | |
| Dominance children: 67, 71 | |
| BB 67 (0x7f844403b650): | |
| line: 1534 (pc 1376) | |
| Instructions: | |
| const_s r26(8), lits(lexical) # [097] start of exprjit tree | |
| atkey_i r19(16), r13(6), r17(5) | |
| sp_getspeshslot r10(27), sslot(21) | |
| [Annotation: INS Deopt One (idx 41 -> pc 1406; line 1534)] | |
| [Annotation: Logged (bytecode offset 1400)] | |
| sp_decont r33(6), r1(6) | |
| Successors: 68, 22, 20, 98 | |
| Predecessors: 66 | |
| Dominance children: 68 | |
| BB 68 (0x7f844403b6b0): | |
| line: 1534 (pc 1406) | |
| Instructions: | |
| sp_findmeth r31(7), r33(6), lits(symbol), sslot(22) # [098] start of exprjit tree | |
| Successors: 69, 22, 20, 98 | |
| Predecessors: 67 | |
| Dominance children: 69 | |
| BB 69 (0x7f844403b710): | |
| line: 1534 (pc 1416) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 42 -> pc 1416; line 1534)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [099] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(8) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(16) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(27) | |
| [Annotation: INS Deopt All (idx 44 -> pc 1480; line 1534)] | |
| [Annotation: INS Deopt One (idx 43 -> pc 1480; line 1534)] | |
| [Annotation: Logged (bytecode offset 1474)] | |
| invoke_o r31(8), r31(7) | |
| Successors: 70, 22, 20, 98 | |
| Predecessors: 68 | |
| Dominance children: 70 | |
| BB 70 (0x7f844403b770): | |
| line: 1534 (pc 1480) | |
| Instructions: | |
| goto BB(97) # [100] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 69 | |
| Dominance children: | |
| BB 71 (0x7f844403b7d0): | |
| line: 1534 (pc 1486) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 45 -> pc 1492; line 1534)] | |
| [Annotation: Logged (bytecode offset 1486)] | |
| set r10(28), r18(6) # [101] start of exprjit tree | |
| # [102] expr bail: Cannot get template for: sp_get_i64 | |
| # [015] unbox_i from a BOOTInt | |
| # [014] specialized from smrt_intify | |
| sp_get_i64 r19(17), r10(28), liti16(24) | |
| Successors: 72, 22, 20, 98 | |
| Predecessors: 66 | |
| Dominance children: 81 | |
| BB 72 (0x7f844403b890): | |
| line: 1534 (pc 1498) | |
| Instructions: | |
| const_i64_16 r34(5), liti16(7) # [103] start of exprjit tree | |
| eq_i r34(6), r19(17), r34(5) | |
| unless_i r34(6), BB(77) | |
| Successors: 77, 73 | |
| Predecessors: 71 | |
| Dominance children: 73, 77 | |
| BB 73 (0x7f844403b8f0): | |
| line: 1538 (pc 1520) | |
| Instructions: | |
| const_s r26(9), lits(lexical) # [104] start of exprjit tree | |
| atkey_u r35(5), r13(6), r17(5) | |
| coerce_ui r19(18), r35(5) | |
| sp_getspeshslot r10(29), sslot(24) | |
| [Annotation: INS Deopt One (idx 46 -> pc 1556; line 1538)] | |
| [Annotation: Logged (bytecode offset 1550)] | |
| sp_decont r36(6), r1(6) | |
| Successors: 74, 22, 20, 98 | |
| Predecessors: 72 | |
| Dominance children: 74 | |
| BB 74 (0x7f844403b950): | |
| line: 1538 (pc 1556) | |
| Instructions: | |
| sp_findmeth r33(7), r36(6), lits(symbol), sslot(25) # [105] start of exprjit tree | |
| Successors: 75, 22, 20, 98 | |
| Predecessors: 73 | |
| Dominance children: 75 | |
| BB 75 (0x7f844403b9b0): | |
| line: 1538 (pc 1566) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 47 -> pc 1566; line 1538)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [106] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(9) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(18) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(29) | |
| [Annotation: INS Deopt All (idx 49 -> pc 1630; line 1538)] | |
| [Annotation: INS Deopt One (idx 48 -> pc 1630; line 1538)] | |
| [Annotation: Logged (bytecode offset 1624)] | |
| invoke_o r33(8), r33(7) | |
| Successors: 76, 22, 20, 98 | |
| Predecessors: 74 | |
| Dominance children: 76 | |
| BB 76 (0x7f844403ba10): | |
| line: 1538 (pc 1630) | |
| Instructions: | |
| goto BB(97) # [107] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 75 | |
| Dominance children: | |
| BB 77 (0x7f844403ba70): | |
| line: 1538 (pc 1636) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 50 -> pc 1642; line 1538)] | |
| [Annotation: Logged (bytecode offset 1636)] | |
| set r10(30), r18(6) # [108] start of exprjit tree | |
| # [109] expr bail: Cannot get template for: sp_get_i64 | |
| # [017] unbox_i from a BOOTInt | |
| # [016] specialized from smrt_intify | |
| sp_get_i64 r19(19), r10(30), liti16(24) | |
| Successors: 78, 22, 20, 98 | |
| Predecessors: 72 | |
| Dominance children: 88 | |
| BB 78 (0x7f844403bb30): | |
| line: 1538 (pc 1648) | |
| Instructions: | |
| const_i64_16 r37(5), liti16(8) # [110] start of exprjit tree | |
| eq_i r37(6), r19(19), r37(5) | |
| unless_i r37(6), BB(83) | |
| Successors: 83, 79 | |
| Predecessors: 77 | |
| Dominance children: 79, 83 | |
| BB 79 (0x7f844403bb90): | |
| line: 1542 (pc 1670) | |
| Instructions: | |
| const_s r26(10), lits(lexical) # [111] start of exprjit tree | |
| atkey_u r35(6), r13(6), r17(5) | |
| coerce_ui r19(20), r35(6) | |
| sp_getspeshslot r10(31), sslot(27) | |
| [Annotation: INS Deopt One (idx 51 -> pc 1706; line 1542)] | |
| [Annotation: Logged (bytecode offset 1700)] | |
| sp_decont r38(6), r1(6) | |
| Successors: 80, 22, 20, 98 | |
| Predecessors: 78 | |
| Dominance children: 80 | |
| BB 80 (0x7f844403bbf0): | |
| line: 1542 (pc 1706) | |
| Instructions: | |
| sp_findmeth r36(7), r38(6), lits(symbol), sslot(28) # [112] start of exprjit tree | |
| Successors: 81, 22, 20, 98 | |
| Predecessors: 79 | |
| Dominance children: 81 | |
| BB 81 (0x7f844403bc50): | |
| line: 1542 (pc 1716) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 52 -> pc 1716; line 1542)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [113] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(10) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(20) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(31) | |
| [Annotation: INS Deopt All (idx 54 -> pc 1780; line 1542)] | |
| [Annotation: INS Deopt One (idx 53 -> pc 1780; line 1542)] | |
| [Annotation: Logged (bytecode offset 1774)] | |
| invoke_o r36(8), r36(7) | |
| Successors: 82, 22, 20, 98 | |
| Predecessors: 80 | |
| Dominance children: 82 | |
| BB 82 (0x7f844403bcb0): | |
| line: 1542 (pc 1780) | |
| Instructions: | |
| goto BB(97) # [114] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 81 | |
| Dominance children: | |
| BB 83 (0x7f844403bd10): | |
| line: 1542 (pc 1786) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 55 -> pc 1792; line 1542)] | |
| [Annotation: Logged (bytecode offset 1786)] | |
| set r10(32), r18(6) # [115] start of exprjit tree | |
| # [116] expr bail: Cannot get template for: sp_get_i64 | |
| # [019] unbox_i from a BOOTInt | |
| # [018] specialized from smrt_intify | |
| sp_get_i64 r19(21), r10(32), liti16(24) | |
| Successors: 84, 22, 20, 98 | |
| Predecessors: 78 | |
| Dominance children: 95 | |
| BB 84 (0x7f844403bdd0): | |
| line: 1542 (pc 1798) | |
| Instructions: | |
| const_i64_16 r39(5), liti16(9) # [117] start of exprjit tree | |
| eq_i r39(6), r19(21), r39(5) | |
| unless_i r39(6), BB(89) | |
| Successors: 89, 85 | |
| Predecessors: 83 | |
| Dominance children: 85, 89 | |
| BB 85 (0x7f844403be30): | |
| line: 1546 (pc 1820) | |
| Instructions: | |
| const_s r26(11), lits(lexical) # [118] start of exprjit tree | |
| atkey_u r35(7), r13(6), r17(5) | |
| coerce_ui r19(22), r35(7) | |
| sp_getspeshslot r10(33), sslot(30) | |
| [Annotation: INS Deopt One (idx 56 -> pc 1856; line 1546)] | |
| [Annotation: Logged (bytecode offset 1850)] | |
| sp_decont r40(6), r1(6) | |
| Successors: 86, 22, 20, 98 | |
| Predecessors: 84 | |
| Dominance children: 86 | |
| BB 86 (0x7f844403be90): | |
| line: 1546 (pc 1856) | |
| Instructions: | |
| sp_findmeth r38(7), r40(6), lits(symbol), sslot(31) # [119] start of exprjit tree | |
| Successors: 87, 22, 20, 98 | |
| Predecessors: 85 | |
| Dominance children: 87 | |
| BB 87 (0x7f844403bef0): | |
| line: 1546 (pc 1866) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 57 -> pc 1866; line 1546)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) # [120] expr bail: Cannot get template for: prepargs | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(11) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(22) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(33) | |
| [Annotation: INS Deopt All (idx 59 -> pc 1930; line 1546)] | |
| [Annotation: INS Deopt One (idx 58 -> pc 1930; line 1546)] | |
| [Annotation: Logged (bytecode offset 1924)] | |
| invoke_o r38(8), r38(7) | |
| Successors: 88, 22, 20, 98 | |
| Predecessors: 86 | |
| Dominance children: 88 | |
| BB 88 (0x7f844403bf50): | |
| line: 1546 (pc 1930) | |
| Instructions: | |
| goto BB(97) # [121] start of exprjit tree | |
| Successors: 97 | |
| Predecessors: 87 | |
| Dominance children: | |
| BB 89 (0x7f844403bfb0): | |
| line: 1546 (pc 1936) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 60 -> pc 1942; line 1546)] | |
| [Annotation: Logged (bytecode offset 1936)] | |
| set r10(34), r18(6) # [122] start of exprjit tree | |
| # [123] expr bail: Cannot get template for: sp_get_i64 | |
| # [021] unbox_i from a BOOTInt | |
| # [020] specialized from smrt_intify | |
| sp_get_i64 r19(23), r10(34), liti16(24) | |
| Successors: 90, 22, 20, 98 | |
| Predecessors: 84 | |
| Dominance children: 102 | |
| BB 90 (0x7f844403c070): | |
| line: 1546 (pc 1948) | |
| Instructions: | |
| const_i64_16 r41(5), liti16(10) # [124] start of exprjit tree | |
| eq_i r41(6), r19(23), r41(5) | |
| unless_i r41(6), BB(95) | |
| Successors: 95, 91 | |
| Predecessors: 89 | |
| Dominance children: 91, 95 | |
| BB 91 (0x7f844403c0d0): | |
| line: 1550 (pc 1970) | |
| Instructions: | |
| const_s r26(12), lits(lexical) # [125] start of exprjit tree | |
| atkey_u r35(8), r13(6), r17(5) | |
| coerce_ui r19(24), r35(8) | |
| sp_getspeshslot r10(35), sslot(33) | |
| [Annotation: INS Deopt One (idx 61 -> pc 2006; line 1550)] | |
| [Annotation: Logged (bytecode offset 2000)] | |
| sp_decont r42(8), r1(6) | |
| Successors: 92, 22, 20, 98 | |
| Predecessors: 90 | |
| Dominance children: 92 | |
| BB 92 (0x7f8444041160): | |
| line: 1550 (pc 2006) | |
| Instructions: | |
| sp_findmeth r40(7), r42(8), lits(symbol), sslot(34) | |
| Successors: 93, 22, 20, 98 | |
| Predecessors: 91 | |
| Dominance children: 93 | |
| BB 93 (0x7f84440411c0): | |
| line: 1550 (pc 2016) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 62 -> pc 2016; line 1550)] | |
| prepargs callsite(0x560f5bb9f760, 8 arg, 2 pos, nonflattening, interned) | |
| arg_o liti16(0), r1(6) | |
| arg_s liti16(1), r17(5) | |
| argconst_s liti16(2), lits(scope) | |
| arg_s liti16(3), r26(12) | |
| argconst_s liti16(4), lits(value) | |
| arg_i liti16(5), r19(24) | |
| argconst_s liti16(6), lits(type) | |
| arg_o liti16(7), r10(35) | |
| [Annotation: INS Deopt All (idx 64 -> pc 2080; line 1550)] | |
| [Annotation: INS Deopt One (idx 63 -> pc 2080; line 1550)] | |
| [Annotation: Logged (bytecode offset 2074)] | |
| invoke_o r40(8), r40(7) | |
| Successors: 94, 22, 20, 98 | |
| Predecessors: 92 | |
| Dominance children: 94 | |
| BB 94 (0x7f8444041220): | |
| line: 1550 (pc 2080) | |
| Instructions: | |
| goto BB(97) | |
| Successors: 97 | |
| Predecessors: 93 | |
| Dominance children: | |
| BB 95 (0x7f8444041280): | |
| line: 1553 (pc 2086) | |
| Instructions: | |
| [Annotation: INS Deopt One (idx 65 -> pc 2094; line 1553)] | |
| [Annotation: Logged (bytecode offset 2086)] | |
| sp_getlex_no r10(36), lits(&die) | |
| [Annotation: INS Deopt One (idx 66 -> pc 2100; line 1553)] | |
| [Annotation: Logged (bytecode offset 2094)] | |
| sp_decont r10(37), r10(36) | |
| Successors: 96, 22, 20, 98 | |
| Predecessors: 90 | |
| Dominance children: 96 | |
| BB 96 (0x7f84440412e0): | |
| line: 1553 (pc 2100) | |
| Instructions: | |
| const_s r26(13), lits(Unhandled lexical type) | |
| [Annotation: INS Deopt One (idx 67 -> pc 2108; line 1553)] | |
| prepargs callsite(0x560f5b9ee530, 1 arg, 1 pos, nonflattening, interned) | |
| arg_s liti16(0), r26(13) | |
| [Annotation: INS Deopt All (idx 68 -> pc 2122; line 1553)] | |
| [Annotation: Logged (bytecode offset 2118)] | |
| invoke_v r10(37) | |
| Successors: 97, 22, 20, 98 | |
| Predecessors: 95 | |
| Dominance children: | |
| BB 97 (0x7f8444041340): | |
| line: 1553 (pc 2122) | |
| Instructions: | |
| PHI r42(9), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(7) | |
| PHI r41(7), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6) | |
| PHI r40(9), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(8), r40(5) | |
| PHI r39(7), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6) | |
| PHI r38(9), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(8), r38(5), r38(5) | |
| PHI r37(7), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6) | |
| PHI r36(9), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(8), r36(5), r36(5), r36(5) | |
| PHI r35(9), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(6), r35(7), r35(8), r35(4) | |
| PHI r34(7), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6) | |
| PHI r33(9), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(8), r33(5), r33(5), r33(5), r33(5) | |
| PHI r32(7), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6) | |
| PHI r31(9), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5) | |
| PHI r30(7), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6) | |
| PHI r29(9), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5) | |
| PHI r28(7), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6) | |
| PHI r27(9), r27(5), r27(5), r27(5), r27(5), r27(6), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5) | |
| PHI r26(14), r26(4), r26(4), r26(4), r26(4), r26(5), r26(6), r26(7), r26(8), r26(9), r26(10), r26(11), r26(12), r26(13) | |
| PHI r25(7), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6) | |
| PHI r24(9), r24(5), r24(5), r24(5), r24(6), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5) | |
| PHI r23(6), r23(4), r23(4), r23(4), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4) | |
| PHI r22(7), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6) | |
| PHI r21(7), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6) | |
| PHI r20(7), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6) | |
| PHI r19(25), r19(4), r19(6), r19(8), r19(9), r19(10), r19(12), r19(14), r19(16), r19(18), r19(20), r19(22), r19(24), r19(23) | |
| PHI r18(7), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6) | |
| PHI r10(38), r10(14), r10(15), r10(17), r10(19), r10(21), r10(23), r10(25), r10(27), r10(29), r10(31), r10(33), r10(35), r10(37) | |
| PHI r9(12), r9(9), r9(9), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9) | |
| PHI r8(13), r8(9), r8(9), r8(10), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9) | |
| PHI r6(20), r6(14), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17) | |
| PHI r3(19), r3(14), r3(15), r3(16), r3(17), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14) | |
| goto BB(20) | |
| Successors: 20 | |
| Predecessors: 28, 34, 40, 46, 52, 58, 64, 70, 76, 82, 88, 94, 96 | |
| Dominance children: | |
| BB 98 (0x7f84440413a0): | |
| line: 1553 (pc 2128) | |
| Instructions: | |
| PHI r42(10), r42(5), r42(6), r42(6), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(7), r42(8), r42(8), r42(8), r42(7), r42(7) | |
| PHI r41(8), r41(2), r41(3), r41(3), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(4), r41(6), r41(6), r41(6), r41(6), r41(6) | |
| PHI r40(10), r40(3), r40(4), r40(4), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(5), r40(6), r40(6), r40(6), r40(5), r40(5), r40(5), r40(7), r40(8), r40(5), r40(5) | |
| PHI r39(8), r39(2), r39(3), r39(3), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(4), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6), r39(6) | |
| PHI r38(10), r38(3), r38(4), r38(4), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(6), r38(6), r38(6), r38(5), r38(5), r38(5), r38(7), r38(8), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5), r38(5) | |
| PHI r37(8), r37(2), r37(3), r37(3), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(4), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6), r37(6) | |
| PHI r36(10), r36(3), r36(4), r36(4), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(6), r36(6), r36(6), r36(5), r36(5), r36(5), r36(7), r36(8), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5), r36(5) | |
| PHI r35(10), r35(2), r35(3), r35(3), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(4), r35(5), r35(5), r35(5), r35(4), r35(4), r35(6), r35(6), r35(6), r35(4), r35(4), r35(7), r35(7), r35(7), r35(4), r35(4), r35(8), r35(8), r35(8), r35(4), r35(4) | |
| PHI r34(8), r34(2), r34(3), r34(3), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(4), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6), r34(6) | |
| PHI r33(10), r33(3), r33(4), r33(4), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(6), r33(6), r33(6), r33(5), r33(5), r33(5), r33(7), r33(8), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5), r33(5) | |
| PHI r32(8), r32(2), r32(3), r32(3), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(4), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6), r32(6) | |
| PHI r31(10), r31(3), r31(4), r31(4), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(6), r31(6), r31(6), r31(5), r31(5), r31(5), r31(7), r31(8), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5), r31(5) | |
| PHI r30(8), r30(2), r30(3), r30(3), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(4), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6), r30(6) | |
| PHI r29(10), r29(3), r29(4), r29(4), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(6), r29(6), r29(6), r29(5), r29(5), r29(5), r29(7), r29(8), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5), r29(5) | |
| PHI r28(8), r28(2), r28(3), r28(3), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(4), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6), r28(6) | |
| PHI r27(10), r27(3), r27(4), r27(4), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(6), r27(6), r27(6), r27(5), r27(5), r27(5), r27(7), r27(8), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5), r27(5) | |
| PHI r26(15), r26(2), r26(3), r26(3), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(4), r26(5), r26(5), r26(5), r26(4), r26(4), r26(6), r26(6), r26(6), r26(4), r26(4), r26(7), r26(7), r26(7), r26(4), r26(4), r26(8), r26(8), r26(8), r26(4), r26(4), r26(9), r26(9), r26(9), r26(4), r26(4), r26(10), r26(10), r26(10), r26(4), r26(4), r26(11), r26(11), r26(11), r26(4), r26(4), r26(12), r26(12), r26(12), r26(4), r26(13) | |
| PHI r25(8), r25(2), r25(3), r25(3), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(4), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6), r25(6) | |
| PHI r24(10), r24(3), r24(4), r24(4), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(6), r24(6), r24(6), r24(5), r24(5), r24(5), r24(7), r24(8), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5), r24(5) | |
| PHI r23(7), r23(2), r23(3), r23(3), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(5), r23(5), r23(5), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4), r23(4) | |
| PHI r22(8), r22(2), r22(3), r22(3), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(4), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6), r22(6) | |
| PHI r21(8), r21(2), r21(3), r21(3), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(4), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6), r21(6) | |
| PHI r20(8), r20(2), r20(3), r20(3), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(4), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6), r20(6) | |
| PHI r19(26), r19(2), r19(3), r19(3), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(4), r19(5), r19(6), r19(6), r19(6), r19(6), r19(6), r19(7), r19(8), r19(8), r19(8), r19(7), r19(9), r19(9), r19(9), r19(9), r19(9), r19(10), r19(10), r19(10), r19(10), r19(10), r19(11), r19(12), r19(12), r19(12), r19(11), r19(13), r19(14), r19(14), r19(14), r19(13), r19(15), r19(16), r19(16), r19(16), r19(15), r19(17), r19(18), r19(18), r19(18), r19(17), r19(19), r19(20), r19(20), r19(20), r19(19), r19(21), r19(22), r19(22), r19(22), r19(21), r19(23), r19(24), r19(24), r19(24), r19(23), r19(23) | |
| PHI r18(8), r18(3), r18(4), r18(4), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(5), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6), r18(6) | |
| PHI r17(6), r17(2), r17(3), r17(3), r17(4), r17(4), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5), r17(5) | |
| PHI r16(7), r16(3), r16(4), r16(4), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6), r16(6) | |
| PHI r15(7), r15(3), r15(5), r15(5), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6), r15(6) | |
| PHI r11(6), r11(3), r11(4), r11(4), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5), r11(5) | |
| PHI r10(39), r10(11), r10(12), r10(12), r10(13), r10(13), r10(13), r10(13), r10(13), r10(14), r10(14), r10(14), r10(14), r10(15), r10(15), r10(15), r10(16), r10(16), r10(17), r10(17), r10(17), r10(18), r10(18), r10(19), r10(19), r10(19), r10(20), r10(20), r10(21), r10(21), r10(21), r10(22), r10(22), r10(23), r10(23), r10(23), r10(24), r10(24), r10(25), r10(25), r10(25), r10(26), r10(26), r10(27), r10(27), r10(27), r10(28), r10(28), r10(29), r10(29), r10(29), r10(30), r10(30), r10(31), r10(31), r10(31), r10(32), r10(32), r10(33), r10(33), r10(33), r10(34), r10(34), r10(35), r10(35), r10(35), r10(37), r10(37) | |
| PHI r9(13), r9(7), r9(8), r9(8), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(10), r9(11), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9), r9(9) | |
| PHI r8(14), r8(7), r8(8), r8(8), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(10), r8(10), r8(10), r8(9), r8(9), r8(9), r8(11), r8(12), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9), r8(9) | |
| PHI r7(8), r7(5), r7(6), r7(6), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7), r7(7) | |
| PHI r6(21), r6(11), r6(12), r6(12), r6(13), r6(13), r6(14), r6(14), r6(14), r6(14), r6(14), r6(17), r6(17), r6(17), r6(18), r6(19), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17), r6(17) | |
| PHI r4(14), r4(11), r4(12), r4(12), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13), r4(13) | |
| PHI r3(20), r3(11), r3(12), r3(12), r3(13), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(15), r3(15), r3(15), r3(14), r3(14), r3(16), r3(16), r3(16), r3(14), r3(14), r3(17), r3(17), r3(17), r3(14), r3(14), r3(18), r3(18), r3(18), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14), r3(14) | |
| PHI r2(7), r2(4), r2(5), r2(5), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6), r2(6) | |
| PHI r1(7), r1(4), r1(5), r1(5), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6), r1(6) | |
| PHI r0(7), r0(4), r0(5), r0(5), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6), r0(6) | |
| [Annotation: FH Goto (2)] | |
| [Annotation: FH End (2)] | |
| [Annotation: FH End (1)] | |
| [Annotation: FH End (0)] | |
| ctxouter r2(8), r2(7) | |
| goto BB(17) | |
| Successors: 17 | |
| Predecessors: 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33, 35, 37, 38, 39, 41, 43, 44, 45, 47, 49, 50, 51, 53, 55, 56, 57, 59, 61, 62, 63, 65, 67, 68, 69, 71, 73, 74, 75, 77, 79, 80, 81, 83, 85, 86, 87, 89, 91, 92, 93, 95, 96 | |
| Dominance children: | |
| BB 99 (0x7f8444041400): | |
| line: 1553 (pc 2150) | |
| Instructions: | |
| set r10(10), r4(10) | |
| Successors: 100 | |
| Predecessors: 17 | |
| Dominance children: | |
| BB 100 (0x7f8444041460): | |
| line: 1553 (pc 2156) | |
| Instructions: | |
| PHI r10(40), r10(8), r10(10) | |
| return_o r10(40) | |
| Successors: | |
| Predecessors: 15, 99 | |
| Dominance children: | |
| Facts: | |
| r0(0): usages=2, flags=0 | |
| r0(1): usages=0, flags=0 DeadWriter | |
| r0(2): usages=1, deopt=0, flags=17 KnTyp TyObj (type: Perl6::Actions) | |
| r0(3): usages=1, flags=0 (merged from 2 regs) | |
| r0(4): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r0(5): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r0(6): usages=193, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r0(7): usages=1, flags=0 (merged from 67 regs) | |
| r0(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r1(0): usages=2, flags=0 | |
| r1(1): usages=0, flags=0 DeadWriter | |
| r1(2): usages=1, deopt=0, flags=9 KnTyp Concr (type: QAST::Block) | |
| r1(3): usages=1, flags=0 (merged from 2 regs) | |
| r1(4): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r1(5): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r1(6): usages=217, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r1(7): usages=1, flags=0 (merged from 67 regs) | |
| r1(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r2(0): usages=2, flags=0 | |
| r2(1): usages=0, flags=0 DeadWriter | |
| r2(2): usages=2, deopt=0, flags=0 | |
| r2(3): usages=2, flags=0 (merged from 2 regs) | |
| r2(4): usages=3, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r2(5): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r2(6): usages=193, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r2(7): usages=1, flags=0 (merged from 67 regs) | |
| r2(8): usages=1, flags=0 | |
| r2(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r3(0): usages=2, flags=0 | |
| r3(1): usages=1, flags=2 KnVal | |
| r3(2): usages=1, flags=2 KnVal | |
| r3(3): usages=1, flags=2 KnVal | |
| r3(4): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r3(5): usages=1, flags=2 KnVal | |
| r3(6): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r3(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r3(8): usages=1, flags=2 KnVal | |
| r3(9): usages=2, deopt=0, flags=2 KnVal | |
| r3(10): usages=1, flags=0 (merged from 2 regs) | |
| r3(11): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r3(12): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r3(13): usages=3, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r3(14): usages=163, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5, flags=0 | |
| r3(15): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=2 KnVal | |
| r3(16): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=2 KnVal | |
| r3(17): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=2 KnVal | |
| r3(18): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=2 KnVal | |
| r3(19): usages=1, flags=0 (merged from 13 regs) | |
| r3(20): usages=1, flags=0 (merged from 67 regs) | |
| r3(21): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r4(0): usages=2, flags=0 | |
| r4(1): usages=0, flags=0 DeadWriter | |
| r4(2): usages=2, flags=0 | |
| r4(3): usages=0, flags=19 KnTyp KnVal TyObj (type: NQPMu) | |
| r4(4): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r4(5): usages=1, flags=19 KnTyp KnVal TyObj (type: NQPMu) | |
| r4(6): usages=1, flags=0 | |
| r4(7): usages=1, flags=0 (merged from 2 regs) | |
| r4(8): usages=1, deopt=0, flags=0 | |
| r4(9): usages=1, flags=3 KnTyp KnVal (type: VMNull) | |
| r4(10): usages=2, flags=0 (merged from 2 regs) | |
| r4(11): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r4(12): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r4(13): usages=193, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r4(14): usages=1, flags=0 (merged from 67 regs) | |
| r4(15): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r5(0): usages=0, flags=0 | |
| r5(1): usages=0, flags=0 DeadWriter | |
| r5(2): usages=1, flags=0 | |
| r5(3): usages=1, flags=0 | |
| r5(4): usages=1, flags=0 (merged from 2 regs) | |
| r5(5): usages=2, flags=0 | |
| r5(6): usages=0, flags=19 KnTyp KnVal TyObj (type: NQPMu) | |
| r5(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r5(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r5(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r5(10): usages=0, flags=0 | |
| r5(11): usages=0, flags=0 | |
| r5(12): usages=0, flags=0 DeadWriter (merged from 68 regs) | |
| r5(13): usages=1, deopt=2, flags=0 | |
| r5(14): usages=0, flags=0 DeadWriter (merged from 67 regs) | |
| r5(15): usages=0, flags=0 | |
| r5(16): usages=1, deopt=4, flags=0 | |
| r5(17): usages=1, flags=0 | |
| r5(18): usages=1, deopt=7,8, flags=0 | |
| r5(19): usages=0, flags=0 DeadWriter (merged from 67 regs) | |
| r5(20): usages=0, flags=0 | |
| r5(21): usages=0, flags=0 DeadWriter | |
| r5(22): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r6(0): usages=2, flags=0 | |
| r6(1): usages=0, flags=0 DeadWriter | |
| r6(2): usages=1, flags=0 | |
| r6(3): usages=1, flags=0 | |
| r6(4): usages=1, flags=0 (merged from 2 regs) | |
| r6(5): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r6(6): usages=1, flags=19 KnTyp KnVal TyObj (type: NQPMu) | |
| r6(7): usages=1, flags=0 | |
| r6(8): usages=1, flags=0 (merged from 2 regs) | |
| r6(9): usages=3, deopt=0, flags=0 | |
| r6(10): usages=1, flags=0 (merged from 2 regs) | |
| r6(11): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r6(12): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r6(13): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r6(14): usages=17, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5, flags=0 | |
| r6(15): usages=0, flags=19 KnTyp KnVal TyObj DeadWriter (type: BOOTInt) | |
| r6(16): usages=0, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r6(17): usages=177, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r6(18): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14, flags=0 | |
| r6(19): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14, flags=0 | |
| r6(20): usages=1, flags=0 (merged from 13 regs) | |
| r6(21): usages=1, flags=0 (merged from 67 regs) | |
| r6(22): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r7(0): usages=2, flags=0 | |
| r7(1): usages=1, flags=3 KnTyp KnVal (type: VMNull) | |
| r7(2): usages=3, flags=0 | |
| r7(3): usages=1, deopt=0, flags=0 (merged from 2 regs) | |
| r7(4): usages=1, flags=0 (merged from 2 regs) | |
| r7(5): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r7(6): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r7(7): usages=193, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r7(8): usages=1, flags=0 (merged from 67 regs) | |
| r7(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r8(0): usages=2, flags=0 | |
| r8(1): usages=1, flags=3 KnTyp KnVal (type: VMNull) | |
| r8(2): usages=1, flags=0 | |
| r8(3): usages=0, flags=0 | |
| r8(4): usages=3, flags=0 | |
| r8(5): usages=1, deopt=0, flags=0 (merged from 2 regs) | |
| r8(6): usages=1, flags=0 (merged from 2 regs) | |
| r8(7): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r8(8): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r8(9): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r8(10): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=0 | |
| r8(11): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24, flags=0 | |
| r8(12): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24, flags=0 | |
| r8(13): usages=1, flags=0 (merged from 13 regs) | |
| r8(14): usages=1, flags=0 (merged from 67 regs) | |
| r8(15): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r9(0): usages=2, flags=0 | |
| r9(1): usages=1, flags=3 KnTyp KnVal (type: VMNull) | |
| r9(2): usages=1, flags=9 KnTyp Concr (type: BOOTHash) | |
| r9(3): usages=1, flags=0 | |
| r9(4): usages=3, flags=0 (merged from 2 regs) | |
| r9(5): usages=1, deopt=0, flags=0 (merged from 2 regs) | |
| r9(6): usages=1, flags=0 (merged from 2 regs) | |
| r9(7): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r9(8): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r9(9): usages=198, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r9(10): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19, flags=0 | |
| r9(11): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19, flags=0 | |
| r9(12): usages=1, flags=0 (merged from 13 regs) | |
| r9(13): usages=1, flags=0 (merged from 67 regs) | |
| r9(14): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r10(0): usages=2, flags=0 | |
| r10(1): usages=0, flags=0 DeadWriter | |
| r10(2): usages=0, flags=19 KnTyp KnVal TyObj DeadWriter (type: BOOTHash) | |
| r10(3): usages=2, flags=9 KnTyp Concr (type: BOOTHash) | |
| r10(4): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r10(5): usages=0, flags=0 | |
| r10(6): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r10(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r10(8): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(9): usages=1, flags=0 (merged from 2 regs) | |
| r10(10): usages=1, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 | |
| r10(11): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r10(12): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r10(13): usages=15, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r10(14): usages=14, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9, flags=0 | |
| r10(15): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=0 | |
| r10(16): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(17): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=19 KnTyp KnVal TyObj (type: int) | |
| r10(18): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(19): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=19 KnTyp KnVal TyObj (type: num) | |
| r10(20): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(21): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=19 KnTyp KnVal TyObj (type: str) | |
| r10(22): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(23): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=19 KnTyp KnVal TyObj (type: int8) | |
| r10(24): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(25): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=19 KnTyp KnVal TyObj (type: int16) | |
| r10(26): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(27): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=19 KnTyp KnVal TyObj (type: int32) | |
| r10(28): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(29): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=19 KnTyp KnVal TyObj (type: uint8) | |
| r10(30): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(31): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=19 KnTyp KnVal TyObj (type: uint16) | |
| r10(32): usages=7, deopt=68,66,63,64,61,58,59,56, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(33): usages=11, deopt=68,66,63,64,61,58,59,56, flags=19 KnTyp KnVal TyObj (type: uint32) | |
| r10(34): usages=7, deopt=68,66,63,64,61, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r10(35): usages=11, deopt=68,66,63,64,61, flags=19 KnTyp KnVal TyObj (type: uint64) | |
| r10(36): usages=1, flags=0 | |
| r10(37): usages=8, deopt=68,66, flags=0 | |
| r10(38): usages=1, flags=0 (merged from 13 regs) | |
| r10(39): usages=1, flags=0 (merged from 67 regs) | |
| r10(40): usages=1, flags=0 (merged from 2 regs) | |
| r11(0): usages=2, flags=0 | |
| r11(1): usages=3, flags=0 | |
| r11(2): usages=1, flags=0 (merged from 2 regs) | |
| r11(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r11(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r11(5): usages=193, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r11(6): usages=1, flags=0 (merged from 67 regs) | |
| r11(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r12(0): usages=2, flags=0 | |
| r12(1): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r12(2): usages=2, flags=0 | |
| r12(3): usages=1, flags=0 (merged from 2 regs) | |
| r12(4): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r12(5): usages=129, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r12(6): usages=0, flags=0 DeadWriter (merged from 67 regs) | |
| r12(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r13(0): usages=1, flags=0 | |
| r13(1): usages=0, flags=0 DeadWriter | |
| r13(2): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r13(3): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r13(4): usages=3, flags=0 | |
| r13(5): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r13(6): usages=141, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r13(7): usages=0, flags=0 DeadWriter (merged from 67 regs) | |
| r13(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r14(0): usages=1, flags=0 | |
| r14(1): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r14(2): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r14(3): usages=2, flags=0 | |
| r14(4): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r14(5): usages=129, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r14(6): usages=0, flags=0 DeadWriter (merged from 67 regs) | |
| r14(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r15(0): usages=2, flags=0 | |
| r15(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r15(2): usages=1, flags=0 (merged from 2 regs) | |
| r15(3): usages=1, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r15(4): usages=1, flags=0 | |
| r15(5): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r15(6): usages=194, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r15(7): usages=1, flags=0 (merged from 67 regs) | |
| r15(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r16(0): usages=1, flags=0 | |
| r16(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r16(2): usages=1, flags=0 (merged from 2 regs) | |
| r16(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r16(4): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r16(5): usages=0, flags=0 DeadWriter (merged from 67 regs) | |
| r16(6): usages=130, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 | |
| r16(7): usages=1, flags=0 (merged from 67 regs) | |
| r16(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r17(0): usages=3, flags=0 | |
| r17(1): usages=1, flags=0 (merged from 2 regs) | |
| r17(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r17(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r17(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r17(5): usages=210, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5, flags=0 | |
| r17(6): usages=1, flags=0 (merged from 67 regs) | |
| r17(7): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r18(0): usages=2, flags=0 | |
| r18(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r18(2): usages=1, flags=0 (merged from 2 regs) | |
| r18(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r18(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r18(5): usages=22, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r18(6): usages=194, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r18(7): usages=1, flags=0 (merged from 13 regs) | |
| r18(8): usages=1, flags=0 (merged from 67 regs) | |
| r18(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r19(0): usages=3, flags=0 | |
| r19(1): usages=1, flags=0 (merged from 2 regs) | |
| r19(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r19(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r19(4): usages=22, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r19(5): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=0 | |
| r19(6): usages=17, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=0 | |
| r19(7): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=0 | |
| r19(8): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=0 | |
| r19(9): usages=17, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=0 | |
| r19(10): usages=17, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=0 | |
| r19(11): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=0 | |
| r19(12): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=0 | |
| r19(13): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=0 | |
| r19(14): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=0 | |
| r19(15): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=0 | |
| r19(16): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=0 | |
| r19(17): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=0 | |
| r19(18): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=0 | |
| r19(19): usages=7, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=0 | |
| r19(20): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=0 | |
| r19(21): usages=7, deopt=68,66,63,64,61,58,59,56, flags=0 | |
| r19(22): usages=11, deopt=68,66,63,64,61,58,59,56, flags=0 | |
| r19(23): usages=11, deopt=68,66,63,64,61, flags=0 | |
| r19(24): usages=11, deopt=68,66,63,64,61, flags=0 | |
| r19(25): usages=1, flags=0 (merged from 13 regs) | |
| r19(26): usages=1, flags=0 (merged from 67 regs) | |
| r19(27): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r20(0): usages=3, flags=0 | |
| r20(1): usages=1, flags=0 (merged from 2 regs) | |
| r20(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r20(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r20(4): usages=28, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r20(5): usages=1, flags=2 KnVal | |
| r20(6): usages=178, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11, flags=0 | |
| r20(7): usages=1, flags=0 (merged from 13 regs) | |
| r20(8): usages=1, flags=0 (merged from 67 regs) | |
| r20(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r21(0): usages=3, flags=0 | |
| r21(1): usages=1, flags=0 (merged from 2 regs) | |
| r21(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r21(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r21(4): usages=44, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r21(5): usages=1, flags=2 KnVal | |
| r21(6): usages=162, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16, flags=0 | |
| r21(7): usages=1, flags=0 (merged from 13 regs) | |
| r21(8): usages=1, flags=0 (merged from 67 regs) | |
| r21(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r22(0): usages=3, flags=0 | |
| r22(1): usages=1, flags=0 (merged from 2 regs) | |
| r22(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r22(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r22(4): usages=60, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r22(5): usages=1, flags=2 KnVal | |
| r22(6): usages=146, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=0 | |
| r22(7): usages=1, flags=0 (merged from 13 regs) | |
| r22(8): usages=1, flags=0 (merged from 67 regs) | |
| r22(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r23(0): usages=3, flags=0 | |
| r23(1): usages=1, flags=0 (merged from 2 regs) | |
| r23(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r23(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r23(4): usages=195, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r23(5): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=0 | |
| r23(6): usages=1, flags=0 (merged from 13 regs) | |
| r23(7): usages=1, flags=0 (merged from 67 regs) | |
| r23(8): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r24(0): usages=2, flags=0 | |
| r24(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r24(2): usages=1, flags=0 (merged from 2 regs) | |
| r24(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r24(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r24(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r24(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21, flags=0 | |
| r24(7): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29, flags=0 | |
| r24(8): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29, flags=0 | |
| r24(9): usages=1, flags=0 (merged from 13 regs) | |
| r24(10): usages=1, flags=0 (merged from 67 regs) | |
| r24(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r25(0): usages=3, flags=0 | |
| r25(1): usages=1, flags=0 (merged from 2 regs) | |
| r25(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r25(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r25(4): usages=76, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r25(5): usages=1, flags=2 KnVal | |
| r25(6): usages=130, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=0 | |
| r25(7): usages=1, flags=0 (merged from 13 regs) | |
| r25(8): usages=1, flags=0 (merged from 67 regs) | |
| r25(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r26(0): usages=3, flags=0 | |
| r26(1): usages=1, flags=0 (merged from 2 regs) | |
| r26(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r26(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r26(4): usages=121, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r26(5): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=0 | |
| r26(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=2 KnVal | |
| r26(7): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=2 KnVal | |
| r26(8): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=2 KnVal | |
| r26(9): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=2 KnVal | |
| r26(10): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=2 KnVal | |
| r26(11): usages=11, deopt=68,66,63,64,61,58,59,56, flags=2 KnVal | |
| r26(12): usages=11, deopt=68,66,63,64,61, flags=2 KnVal | |
| r26(13): usages=5, deopt=68, flags=2 KnVal | |
| r26(14): usages=1, flags=0 (merged from 13 regs) | |
| r26(15): usages=1, flags=0 (merged from 67 regs) | |
| r26(16): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r27(0): usages=2, flags=0 | |
| r27(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r27(2): usages=1, flags=0 (merged from 2 regs) | |
| r27(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r27(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r27(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r27(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26, flags=0 | |
| r27(7): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34, flags=0 | |
| r27(8): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34, flags=0 | |
| r27(9): usages=1, flags=0 (merged from 13 regs) | |
| r27(10): usages=1, flags=0 (merged from 67 regs) | |
| r27(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r28(0): usages=3, flags=0 | |
| r28(1): usages=1, flags=0 (merged from 2 regs) | |
| r28(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r28(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r28(4): usages=92, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r28(5): usages=1, flags=2 KnVal | |
| r28(6): usages=114, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=0 | |
| r28(7): usages=1, flags=0 (merged from 13 regs) | |
| r28(8): usages=1, flags=0 (merged from 67 regs) | |
| r28(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r29(0): usages=2, flags=0 | |
| r29(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r29(2): usages=1, flags=0 (merged from 2 regs) | |
| r29(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r29(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r29(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r29(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31, flags=0 | |
| r29(7): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39, flags=0 | |
| r29(8): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39, flags=0 | |
| r29(9): usages=1, flags=0 (merged from 13 regs) | |
| r29(10): usages=1, flags=0 (merged from 67 regs) | |
| r29(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r30(0): usages=3, flags=0 | |
| r30(1): usages=1, flags=0 (merged from 2 regs) | |
| r30(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r30(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r30(4): usages=108, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r30(5): usages=1, flags=2 KnVal | |
| r30(6): usages=98, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=0 | |
| r30(7): usages=1, flags=0 (merged from 13 regs) | |
| r30(8): usages=1, flags=0 (merged from 67 regs) | |
| r30(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r31(0): usages=2, flags=0 | |
| r31(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r31(2): usages=1, flags=0 (merged from 2 regs) | |
| r31(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r31(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r31(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r31(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36, flags=0 | |
| r31(7): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44, flags=0 | |
| r31(8): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44, flags=0 | |
| r31(9): usages=1, flags=0 (merged from 13 regs) | |
| r31(10): usages=1, flags=0 (merged from 67 regs) | |
| r31(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r32(0): usages=3, flags=0 | |
| r32(1): usages=1, flags=0 (merged from 2 regs) | |
| r32(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r32(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r32(4): usages=124, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r32(5): usages=1, flags=2 KnVal | |
| r32(6): usages=82, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=0 | |
| r32(7): usages=1, flags=0 (merged from 13 regs) | |
| r32(8): usages=1, flags=0 (merged from 67 regs) | |
| r32(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r33(0): usages=2, flags=0 | |
| r33(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r33(2): usages=1, flags=0 (merged from 2 regs) | |
| r33(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r33(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r33(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r33(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41, flags=0 | |
| r33(7): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49, flags=0 | |
| r33(8): usages=4, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49, flags=0 | |
| r33(9): usages=1, flags=0 (merged from 13 regs) | |
| r33(10): usages=1, flags=0 (merged from 67 regs) | |
| r33(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r34(0): usages=3, flags=0 | |
| r34(1): usages=1, flags=0 (merged from 2 regs) | |
| r34(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r34(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r34(4): usages=140, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r34(5): usages=1, flags=2 KnVal | |
| r34(6): usages=66, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=0 | |
| r34(7): usages=1, flags=0 (merged from 13 regs) | |
| r34(8): usages=1, flags=0 (merged from 67 regs) | |
| r34(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r35(0): usages=3, flags=0 | |
| r35(1): usages=1, flags=0 (merged from 2 regs) | |
| r35(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r35(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r35(4): usages=165, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r35(5): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=0 | |
| r35(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=0 | |
| r35(7): usages=11, deopt=68,66,63,64,61,58,59,56, flags=0 | |
| r35(8): usages=11, deopt=68,66,63,64,61, flags=0 | |
| r35(9): usages=1, flags=0 (merged from 13 regs) | |
| r35(10): usages=1, flags=0 (merged from 67 regs) | |
| r35(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r36(0): usages=2, flags=0 | |
| r36(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r36(2): usages=1, flags=0 (merged from 2 regs) | |
| r36(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r36(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r36(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r36(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46, flags=0 | |
| r36(7): usages=4, deopt=68,66,63,64,61,58,59,56,53,54, flags=0 | |
| r36(8): usages=4, deopt=68,66,63,64,61,58,59,56,53,54, flags=0 | |
| r36(9): usages=1, flags=0 (merged from 13 regs) | |
| r36(10): usages=1, flags=0 (merged from 67 regs) | |
| r36(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r37(0): usages=3, flags=0 | |
| r37(1): usages=1, flags=0 (merged from 2 regs) | |
| r37(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r37(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r37(4): usages=156, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r37(5): usages=1, flags=2 KnVal | |
| r37(6): usages=50, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=0 | |
| r37(7): usages=1, flags=0 (merged from 13 regs) | |
| r37(8): usages=1, flags=0 (merged from 67 regs) | |
| r37(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r38(0): usages=2, flags=0 | |
| r38(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r38(2): usages=1, flags=0 (merged from 2 regs) | |
| r38(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r38(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r38(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r38(6): usages=11, deopt=68,66,63,64,61,58,59,56,53,54,51, flags=0 | |
| r38(7): usages=4, deopt=68,66,63,64,61,58,59, flags=0 | |
| r38(8): usages=4, deopt=68,66,63,64,61,58,59, flags=0 | |
| r38(9): usages=1, flags=0 (merged from 13 regs) | |
| r38(10): usages=1, flags=0 (merged from 67 regs) | |
| r38(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r39(0): usages=3, flags=0 | |
| r39(1): usages=1, flags=0 (merged from 2 regs) | |
| r39(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r39(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r39(4): usages=172, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r39(5): usages=1, flags=2 KnVal | |
| r39(6): usages=34, deopt=68,66,63,64,61,58,59,56, flags=0 | |
| r39(7): usages=1, flags=0 (merged from 13 regs) | |
| r39(8): usages=1, flags=0 (merged from 67 regs) | |
| r39(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r40(0): usages=2, flags=0 | |
| r40(1): usages=1, deopt=0, flags=3 KnTyp KnVal (type: VMNull) | |
| r40(2): usages=1, flags=0 (merged from 2 regs) | |
| r40(3): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r40(4): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r40(5): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r40(6): usages=11, deopt=68,66,63,64,61,58,59,56, flags=0 | |
| r40(7): usages=4, deopt=68,66,63,64, flags=0 | |
| r40(8): usages=4, deopt=68,66,63,64, flags=0 | |
| r40(9): usages=1, flags=0 (merged from 13 regs) | |
| r40(10): usages=1, flags=0 (merged from 67 regs) | |
| r40(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r41(0): usages=3, flags=0 | |
| r41(1): usages=1, flags=0 (merged from 2 regs) | |
| r41(2): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r41(3): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r41(4): usages=188, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r41(5): usages=1, flags=2 KnVal | |
| r41(6): usages=18, deopt=68,66,63,64,61, flags=0 | |
| r41(7): usages=1, flags=0 (merged from 13 regs) | |
| r41(8): usages=1, flags=0 (merged from 67 regs) | |
| r41(9): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r42(0): usages=2, flags=0 | |
| r42(1): usages=0, flags=0 DeadWriter | |
| r42(2): usages=0, flags=19 KnTyp KnVal TyObj DeadWriter (type: BOOTInt) | |
| r42(3): usages=2, flags=2057 KnTyp Concr KBxSr (type: BOOTInt) | |
| r42(4): usages=1, flags=0 (merged from 2 regs) | |
| r42(5): usages=2, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 2 regs) | |
| r42(6): usages=6, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4,2, flags=0 (merged from 68 regs) | |
| r42(7): usages=195, deopt=68,66,63,64,61,58,59,56,53,54,51,48,49,46,43,44,41,38,39,36,33,34,31,28,29,26,23,24,21,18,19,16,13,14,11,9,7,8,5,4, flags=0 (merged from 67 regs) | |
| r42(8): usages=11, deopt=68,66,63,64,61, flags=0 | |
| r42(9): usages=1, flags=0 (merged from 13 regs) | |
| r42(10): usages=1, flags=0 (merged from 67 regs) | |
| r42(11): usages=0, flags=0 DeadWriter (merged from 2 regs) | |
| r43(0): usages=1, flags=0 | |
| r43(1): usages=1, flags=0 | |
| r43(2): usages=0, flags=0 | |
| r43(3): usages=0, flags=0 | |
| r43(4): usages=0, flags=0 | |
| r43(5): usages=0, flags=0 | |
| r43(6): usages=0, flags=0 | |
| r43(7): usages=0, flags=0 | |
| r43(8): usages=0, flags=0 | |
| r43(9): usages=0, flags=0 | |
| r43(10): usages=0, flags=0 | |
| r43(11): usages=0, flags=0 | |
| r43(12): usages=0, flags=0 | |
| Spesh slots: | |
| 0 = STable (BOOTHash) | |
| 1 = Type Object (NQPMu) | |
| 2 = NULL | |
| 3 = NULL | |
| 4 = NULL | |
| 5 = NULL | |
| 6 = Type Object (int) | |
| 7 = NULL | |
| 8 = NULL | |
| 9 = Type Object (num) | |
| 10 = NULL | |
| 11 = NULL | |
| 12 = Type Object (str) | |
| 13 = NULL | |
| 14 = NULL | |
| 15 = Type Object (int8) | |
| 16 = NULL | |
| 17 = NULL | |
| 18 = Type Object (int16) | |
| 19 = NULL | |
| 20 = NULL | |
| 21 = Type Object (int32) | |
| 22 = NULL | |
| 23 = NULL | |
| 24 = Type Object (uint8) | |
| 25 = NULL | |
| 26 = NULL | |
| 27 = Type Object (uint16) | |
| 28 = NULL | |
| 29 = NULL | |
| 30 = Type Object (uint32) | |
| 31 = NULL | |
| 32 = NULL | |
| 33 = Type Object (uint64) | |
| 34 = NULL | |
| 35 = NULL | |
| 36 = STable (BOOTInt) | |
| 37 = STable (BOOTInt) | |
| Frame size: 3246 bytes | |
| Specialization took 3120us (total 12772us) | |
| JIT was successful and compilation took 9343us | |
| Bytecode size: 12097 byte | |
| ======== | |
| Latest guard tree for 'SET_BLOCK_OUTER_CTX' (cuid: 103, file: gen/moar/stage2/NQPHLL.nqp:1499) | |
| 0: CALLSITE 0x7f844c1156c0 | Y: 1, N: 0 | |
| 1: LOAD ARG 0 | Y: 2 | |
| 2: STABLE CONC Perl6::Actions | Y: 3, N: 0 | |
| 3: LOAD ARG 1 | Y: 4 | |
| 4: STABLE CONC QAST::Block | Y: 5, N: 0 | |
| 5: RESULT 0 | |
| ======== | |
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