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@MasterQ32
Last active September 6, 2019 18:10
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Zig Compiler Crash Report
const Build = @import("std").build;
const builtin = @import("builtin");
const arm_target = Build.Target{
.Cross = Build.CrossTarget{
.arch = builtin.Arch {
.arm = builtin.Arch.Arm32.v7m,
},
.os = builtin.Os.freestanding,
.abi = builtin.Abi.eabi,
},
};
pub fn build(b: *Build.Builder) void {
const mode = b.standardReleaseOptions();
const exe = b.addExecutable("zigvaders", "src/main.zig");
exe.linker_script = "linker.ld";
exe.is_dynamic = false;
exe.setTheTarget(arm_target);
exe.setBuildMode(mode);
exe.install();
const run_cmd = exe.run();
run_cmd.step.dependOn(b.getInstallStep());
const run_step = b.step("run", "Run the app");
run_step.dependOn(&run_cmd.step);
}
[felix@denkplatte zigvaders]$ zig build install
Assertion failed. This is a bug in the Zig compiler.
???:?:?: 0x7f427d5fa559 in ??? (???)
???:?:?: 0x7f427d5b9704 in ??? (???)
The following command terminated unexpectedly:
/home/felix/zig/zig build-exe /home/felix/projects/lowlevel/zigvaders/src/main.zig --cache-dir /home/felix/projects/lowlevel/zigvaders/zig-cache --name zigvaders -target armv7m-freestanding-eabi --linker-script /home/felix/projects/lowlevel/zigvaders/linker.ld --cache on
Build failed. The following command failed:
/home/felix/projects/lowlevel/zigvaders/zig-cache/o/Id3BhaO58eooMmlc1nxzJP-GJ2AlvMQC9OkAkHWgmvAklanKCKhnFPIP2gVWjf9e/build /home/felix/zig/zig /home/felix/projects/lowlevel/zigvaders /home/felix/projects/lowlevel/zigvaders/zig-cache install
# Compiler Version:
# zig-linux-x86_64-0.4.0+0a3c6dbd.tar.xz 8fd970bc3b555508ec4e3ff107cce85f75a690beddc178e67d93fe5998b97a13
/*******************************************
Memory Definitions für LPC 1768
*******************************************/
MEMORY
{
flash (RX) : ORIGIN = 0x00000000, LENGTH = 512k /* .text */
isrram (RW) : ORIGIN = 0x10000000, LENGTH = 256 /* RAM-Sprungtabelle für Interrupts */
ram (RW) : ORIGIN = 0x10000100, LENGTH = 16k-256-32 /* .data, .bss */
ahbram (RW) : ORIGIN = 0x2007C040, LENGTH = 32K-64-32 /* .ahb */
}
/*
* IAP routine location. 1 makes the routine a thumb routine!
*/
IAP = 0x1FFF1FF1;
/*******************************************
Section Definitions
*******************************************/
SECTIONS
{
. = 0;
/* Code-Speicher im Flash ***********/
.text :
{
. = ALIGN(4);
__code_start__ = .;
KEEP(*( .isr_vector ));
*(.text)
*(.text.*)
. = ALIGN(4);
__code_end__ = .;
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
} >flash
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} >flash
. = ALIGN(4);
/* Konstanten im Flash ****************/
.rodata . :
{
*(.rodata)
*(.rodata.*)
PROVIDE(start_ctors = .);
KEEP(*( .init_array ));
KEEP(*(SORT_BY_INIT_PRIORITY( .init_array.* )));
PROVIDE(end_ctors = .);
PROVIDE(start_dtors = .);
KEEP(*( .fini_array ));
KEEP(*(SORT_BY_INIT_PRIORITY( .fini_array.* )));
PROVIDE(end_dtors = .);
} >flash
. = ALIGN(4);
_etext = . ;
PROVIDE (__text__end = .);
/************* RAM ******************************/
isr_ramvector :
{
__isr_ramvector_start__ = . ;
PROVIDE (__isr_ramvector__start = .);
*(.isr_vector_ram)
/*(.gnu.linkonce.b*)*/
. = ALIGN(4);
__isr_ramvector_end__ = . ;
PROVIDE (__isr_ramvector__end = .);
} >isrram
stack 0x10000100 :
{
. = ALIGN(4);
*(.stackarea)
. = ALIGN(4);
} >ram
/* Initialisierte Variablen im Flash */
.data : AT (_etext)
{
__data_start__ = . ;
PROVIDE (__data__start = .) ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
__data_end__ = . ;
PROVIDE (__data__end = .);
} >ram
. = ALIGN(4);
_edata = . ;
.bss :
{
__bss_start__ = . ;
PROVIDE (__bss__start = .);
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b*)
. = ALIGN(4);
__bss_end__ = . ;
PROVIDE (__bss__end = .);
} >ram
_end = .;
PROVIDE (end = .);
/************** AHBRAM **************************/
ahb_ram : AT (ORIGIN(ahbram)) {
*(.ahb)
} >ahbram
}
const std = @import("std");
const builtin = @import("builtin");
const ISR = nakedcc fn () void;
const InterruptTableEntry = packed union {
isr: ISR,
val: u32,
};
fn makeISR(comptime fun: fn () void) ISR {
const ISRHandler = struct {
nakedcc fn invoke() void {
asm volatile ( // interrupt handler preamble
\\mov r0, sp
\\bic r1, r0, #7
\\mov sp, r1
\\push {r0}
);
@inlineCall(fun);
asm volatile ( // Interrupt handler postamble
\\pop {r0}
\\mov sp, r0
\\bx lr
);
}
};
return ISRHandler.invoke;
}
// stack is not set initially
var stack_storage: [1024]u8 align(16) = undefined;
export const fixed_interrupt_table linksection(".isr_vector") = [_]InterruptTableEntry{
InterruptTableEntry{ .val = 0 }, // initial stack memory
InterruptTableEntry{ .isr = makeISR(_start) }, // Reset
InterruptTableEntry{ .isr = makeISR(defaultInterruptHandler) }, // NMI
InterruptTableEntry{ .isr = makeISR(defaultInterruptHandler) }, // HARD fault
InterruptTableEntry{ .isr = makeISR(defaultInterruptHandler) }, // MPU fault
InterruptTableEntry{ .isr = makeISR(defaultInterruptHandler) }, // BUS fault
InterruptTableEntry{ .isr = makeISR(defaultInterruptHandler) }, // USAGE fault
InterruptTableEntry{ .val = 0 }, // checksum of the first 7 entries…
};
fn _start() void {
@newStackCall(stack_storage[0..], kmain);
while (true) {}
}
fn defaultInterruptHandler() void {
while (true) {}
}
fn kmain() void {
while (true) {}
}
pub fn panic(msg: []const u8, error_return_trace: ?*builtin.StackTrace) noreturn {
@setCold(true);
// terminal.write("KERNEL PANIC: ");
// terminal.write(msg);
while (true) {}
}
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