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STM32 GPIO output F1
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| // Input/output registers are spread over two combined registers (CRL, CRH). | |
| if (pin < 8) { | |
| // Set CRL register (CNF & MODE). | |
| uint8_t pinmode = pin * 4; | |
| uint8_t pincnf = pinmode + 2; | |
| if (speed == GPIO_LOW) { instance.regs->CRL |= (0x2 << pinmode); } | |
| else if (speed == GPIO_MID) { instance.regs->CRL |= (0x1 << pinmode); } | |
| else if (speed == GPIO_HIGH) { instance.regs->CRL |= (0x3 << pinmode); } | |
| if (type == GPIO_PUSH_PULL) { instance.regs->CRL &= ~(0x1 << pincnf); } | |
| else if (type == GPIO_OPEN_DRAIN) { instance.regs->CRL |= (0x1 << pincnf); } | |
| } | |
| else { | |
| // Set CRH register. | |
| uint8_t pinmode = (pin - 8) * 4; | |
| uint8_t pincnf = pinmode + 2; | |
| if (speed == GPIO_LOW) { instance.regs->CRH |= (0x2 << pinmode); } | |
| else if (speed == GPIO_MID) { instance.regs->CRH |= (0x1 << pinmode); } | |
| else if (speed == GPIO_HIGH) { instance.regs->CRH |= (0x3 << pinmode); } | |
| if (type == GPIO_PUSH_PULL) { instance.regs->CRH &= ~(0x1 << pincnf); } | |
| else if (type == GPIO_OPEN_DRAIN) { instance.regs->CRH |= (0x1 << pincnf); } | |
| } |
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