RP2040 register definitions translated from C #defines to Go constants

dmaregs.go

package picodma // abitrary package name to keep Go happy

/**
 * TRANSLATED FROM pico-sdk hardware/regs/dma.h which is Copyright (c)
 * 2021 Raspberry Pi (Trading) Ltd. SPDX-License-Identifier: BSD-3-Clause
 */
// =============================================================================
// Register block : DMA
// Version        : 1
// Bus type       : apb
// Description    : DMA with separate read and write masters
// =============================================================================
const (
	// Register    : DMA_CH0_READ_ADDR
	// Description : DMA Channel 0 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH0_READ_ADDR_OFFSET = 0x00000000
	DMA_CH0_READ_ADDR_BITS   = 0xffffffff
	DMA_CH0_READ_ADDR_RESET  = 0x00000000
	DMA_CH0_READ_ADDR_MSB    = 31
	DMA_CH0_READ_ADDR_LSB    = 0
	DMA_CH0_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_WRITE_ADDR
	// Description : DMA Channel 0 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH0_WRITE_ADDR_OFFSET = 0x00000004
	DMA_CH0_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH0_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH0_WRITE_ADDR_MSB    = 31
	DMA_CH0_WRITE_ADDR_LSB    = 0
	DMA_CH0_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_TRANS_COUNT
	// Description : DMA Channel 0 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH0_TRANS_COUNT_OFFSET = 0x00000008
	DMA_CH0_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH0_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH0_TRANS_COUNT_MSB    = 31
	DMA_CH0_TRANS_COUNT_LSB    = 0
	DMA_CH0_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_CTRL_TRIG
	// Description : DMA Channel 0 Control and Status
	DMA_CH0_CTRL_TRIG_OFFSET = 0x0000000c
	DMA_CH0_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH0_CTRL_TRIG_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH0_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH0_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH0_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH0_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH0_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH0_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH0_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH0_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH0_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH0_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH0_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (0).
	DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH0_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH0_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH0_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH0_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH0_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH0_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH0_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH0_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH0_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH0_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH0_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH0_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH0_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH0_CTRL_TRIG_EN_MSB    = 0
	DMA_CH0_CTRL_TRIG_EN_LSB    = 0
	DMA_CH0_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL1_CTRL
	// Description : Alias for channel 0 CTRL register
	DMA_CH0_AL1_CTRL_OFFSET = 0x00000010
	DMA_CH0_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH0_AL1_CTRL_RESET  = "-"
	DMA_CH0_AL1_CTRL_MSB    = 31
	DMA_CH0_AL1_CTRL_LSB    = 0
	DMA_CH0_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL1_READ_ADDR
	// Description : Alias for channel 0 READ_ADDR register
	DMA_CH0_AL1_READ_ADDR_OFFSET = 0x00000014
	DMA_CH0_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH0_AL1_READ_ADDR_RESET  = "-"
	DMA_CH0_AL1_READ_ADDR_MSB    = 31
	DMA_CH0_AL1_READ_ADDR_LSB    = 0
	DMA_CH0_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL1_WRITE_ADDR
	// Description : Alias for channel 0 WRITE_ADDR register
	DMA_CH0_AL1_WRITE_ADDR_OFFSET = 0x00000018
	DMA_CH0_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH0_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH0_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH0_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH0_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 0 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000001c
	DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL2_CTRL
	// Description : Alias for channel 0 CTRL register
	DMA_CH0_AL2_CTRL_OFFSET = 0x00000020
	DMA_CH0_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH0_AL2_CTRL_RESET  = "-"
	DMA_CH0_AL2_CTRL_MSB    = 31
	DMA_CH0_AL2_CTRL_LSB    = 0
	DMA_CH0_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL2_TRANS_COUNT
	// Description : Alias for channel 0 TRANS_COUNT register
	DMA_CH0_AL2_TRANS_COUNT_OFFSET = 0x00000024
	DMA_CH0_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH0_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH0_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH0_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH0_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL2_READ_ADDR
	// Description : Alias for channel 0 READ_ADDR register
	DMA_CH0_AL2_READ_ADDR_OFFSET = 0x00000028
	DMA_CH0_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH0_AL2_READ_ADDR_RESET  = "-"
	DMA_CH0_AL2_READ_ADDR_MSB    = 31
	DMA_CH0_AL2_READ_ADDR_LSB    = 0
	DMA_CH0_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 0 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET = 0x0000002c
	DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL3_CTRL
	// Description : Alias for channel 0 CTRL register
	DMA_CH0_AL3_CTRL_OFFSET = 0x00000030
	DMA_CH0_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH0_AL3_CTRL_RESET  = "-"
	DMA_CH0_AL3_CTRL_MSB    = 31
	DMA_CH0_AL3_CTRL_LSB    = 0
	DMA_CH0_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL3_WRITE_ADDR
	// Description : Alias for channel 0 WRITE_ADDR register
	DMA_CH0_AL3_WRITE_ADDR_OFFSET = 0x00000034
	DMA_CH0_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH0_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH0_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH0_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH0_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL3_TRANS_COUNT
	// Description : Alias for channel 0 TRANS_COUNT register
	DMA_CH0_AL3_TRANS_COUNT_OFFSET = 0x00000038
	DMA_CH0_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH0_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH0_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH0_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH0_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH0_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 0 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET = 0x0000003c
	DMA_CH0_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH0_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH0_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH0_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_READ_ADDR
	// Description : DMA Channel 1 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH1_READ_ADDR_OFFSET = 0x00000040
	DMA_CH1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH1_READ_ADDR_RESET  = 0x00000000
	DMA_CH1_READ_ADDR_MSB    = 31
	DMA_CH1_READ_ADDR_LSB    = 0
	DMA_CH1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_WRITE_ADDR
	// Description : DMA Channel 1 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH1_WRITE_ADDR_OFFSET = 0x00000044
	DMA_CH1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH1_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH1_WRITE_ADDR_MSB    = 31
	DMA_CH1_WRITE_ADDR_LSB    = 0
	DMA_CH1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_TRANS_COUNT
	// Description : DMA Channel 1 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH1_TRANS_COUNT_OFFSET = 0x00000048
	DMA_CH1_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH1_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH1_TRANS_COUNT_MSB    = 31
	DMA_CH1_TRANS_COUNT_LSB    = 0
	DMA_CH1_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_CTRL_TRIG
	// Description : DMA Channel 1 Control and Status
	DMA_CH1_CTRL_TRIG_OFFSET = 0x0000004c
	DMA_CH1_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH1_CTRL_TRIG_RESET  = 0x00000800
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH1_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH1_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH1_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH1_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH1_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH1_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH1_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH1_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH1_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH1_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH1_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (1).
	DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET  = 0x1
	DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH1_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH1_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH1_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH1_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH1_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH1_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH1_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH1_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH1_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH1_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH1_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH1_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH1_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH1_CTRL_TRIG_EN_MSB    = 0
	DMA_CH1_CTRL_TRIG_EN_LSB    = 0
	DMA_CH1_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL1_CTRL
	// Description : Alias for channel 1 CTRL register
	DMA_CH1_AL1_CTRL_OFFSET = 0x00000050
	DMA_CH1_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH1_AL1_CTRL_RESET  = "-"
	DMA_CH1_AL1_CTRL_MSB    = 31
	DMA_CH1_AL1_CTRL_LSB    = 0
	DMA_CH1_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL1_READ_ADDR
	// Description : Alias for channel 1 READ_ADDR register
	DMA_CH1_AL1_READ_ADDR_OFFSET = 0x00000054
	DMA_CH1_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH1_AL1_READ_ADDR_RESET  = "-"
	DMA_CH1_AL1_READ_ADDR_MSB    = 31
	DMA_CH1_AL1_READ_ADDR_LSB    = 0
	DMA_CH1_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL1_WRITE_ADDR
	// Description : Alias for channel 1 WRITE_ADDR register
	DMA_CH1_AL1_WRITE_ADDR_OFFSET = 0x00000058
	DMA_CH1_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH1_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH1_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH1_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH1_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 1 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000005c
	DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL2_CTRL
	// Description : Alias for channel 1 CTRL register
	DMA_CH1_AL2_CTRL_OFFSET = 0x00000060
	DMA_CH1_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH1_AL2_CTRL_RESET  = "-"
	DMA_CH1_AL2_CTRL_MSB    = 31
	DMA_CH1_AL2_CTRL_LSB    = 0
	DMA_CH1_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL2_TRANS_COUNT
	// Description : Alias for channel 1 TRANS_COUNT register
	DMA_CH1_AL2_TRANS_COUNT_OFFSET = 0x00000064
	DMA_CH1_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH1_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH1_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH1_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH1_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL2_READ_ADDR
	// Description : Alias for channel 1 READ_ADDR register
	DMA_CH1_AL2_READ_ADDR_OFFSET = 0x00000068
	DMA_CH1_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH1_AL2_READ_ADDR_RESET  = "-"
	DMA_CH1_AL2_READ_ADDR_MSB    = 31
	DMA_CH1_AL2_READ_ADDR_LSB    = 0
	DMA_CH1_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 1 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET = 0x0000006c
	DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL3_CTRL
	// Description : Alias for channel 1 CTRL register
	DMA_CH1_AL3_CTRL_OFFSET = 0x00000070
	DMA_CH1_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH1_AL3_CTRL_RESET  = "-"
	DMA_CH1_AL3_CTRL_MSB    = 31
	DMA_CH1_AL3_CTRL_LSB    = 0
	DMA_CH1_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL3_WRITE_ADDR
	// Description : Alias for channel 1 WRITE_ADDR register
	DMA_CH1_AL3_WRITE_ADDR_OFFSET = 0x00000074
	DMA_CH1_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH1_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH1_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH1_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH1_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL3_TRANS_COUNT
	// Description : Alias for channel 1 TRANS_COUNT register
	DMA_CH1_AL3_TRANS_COUNT_OFFSET = 0x00000078
	DMA_CH1_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH1_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH1_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH1_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH1_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH1_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 1 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET = 0x0000007c
	DMA_CH1_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH1_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH1_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH1_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_READ_ADDR
	// Description : DMA Channel 2 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH2_READ_ADDR_OFFSET = 0x00000080
	DMA_CH2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH2_READ_ADDR_RESET  = 0x00000000
	DMA_CH2_READ_ADDR_MSB    = 31
	DMA_CH2_READ_ADDR_LSB    = 0
	DMA_CH2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_WRITE_ADDR
	// Description : DMA Channel 2 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH2_WRITE_ADDR_OFFSET = 0x00000084
	DMA_CH2_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH2_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH2_WRITE_ADDR_MSB    = 31
	DMA_CH2_WRITE_ADDR_LSB    = 0
	DMA_CH2_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_TRANS_COUNT
	// Description : DMA Channel 2 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH2_TRANS_COUNT_OFFSET = 0x00000088
	DMA_CH2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH2_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH2_TRANS_COUNT_MSB    = 31
	DMA_CH2_TRANS_COUNT_LSB    = 0
	DMA_CH2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_CTRL_TRIG
	// Description : DMA Channel 2 Control and Status
	DMA_CH2_CTRL_TRIG_OFFSET = 0x0000008c
	DMA_CH2_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH2_CTRL_TRIG_RESET  = 0x00001000
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH2_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH2_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH2_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH2_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH2_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH2_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH2_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH2_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH2_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH2_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH2_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (2).
	DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET  = 0x2
	DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH2_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH2_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH2_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH2_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH2_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH2_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH2_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH2_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH2_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH2_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH2_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH2_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH2_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH2_CTRL_TRIG_EN_MSB    = 0
	DMA_CH2_CTRL_TRIG_EN_LSB    = 0
	DMA_CH2_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL1_CTRL
	// Description : Alias for channel 2 CTRL register
	DMA_CH2_AL1_CTRL_OFFSET = 0x00000090
	DMA_CH2_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH2_AL1_CTRL_RESET  = "-"
	DMA_CH2_AL1_CTRL_MSB    = 31
	DMA_CH2_AL1_CTRL_LSB    = 0
	DMA_CH2_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL1_READ_ADDR
	// Description : Alias for channel 2 READ_ADDR register
	DMA_CH2_AL1_READ_ADDR_OFFSET = 0x00000094
	DMA_CH2_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH2_AL1_READ_ADDR_RESET  = "-"
	DMA_CH2_AL1_READ_ADDR_MSB    = 31
	DMA_CH2_AL1_READ_ADDR_LSB    = 0
	DMA_CH2_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL1_WRITE_ADDR
	// Description : Alias for channel 2 WRITE_ADDR register
	DMA_CH2_AL1_WRITE_ADDR_OFFSET = 0x00000098
	DMA_CH2_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH2_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH2_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH2_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH2_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 2 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000009c
	DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL2_CTRL
	// Description : Alias for channel 2 CTRL register
	DMA_CH2_AL2_CTRL_OFFSET = 0x000000a0
	DMA_CH2_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH2_AL2_CTRL_RESET  = "-"
	DMA_CH2_AL2_CTRL_MSB    = 31
	DMA_CH2_AL2_CTRL_LSB    = 0
	DMA_CH2_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL2_TRANS_COUNT
	// Description : Alias for channel 2 TRANS_COUNT register
	DMA_CH2_AL2_TRANS_COUNT_OFFSET = 0x000000a4
	DMA_CH2_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH2_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH2_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH2_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH2_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL2_READ_ADDR
	// Description : Alias for channel 2 READ_ADDR register
	DMA_CH2_AL2_READ_ADDR_OFFSET = 0x000000a8
	DMA_CH2_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH2_AL2_READ_ADDR_RESET  = "-"
	DMA_CH2_AL2_READ_ADDR_MSB    = 31
	DMA_CH2_AL2_READ_ADDR_LSB    = 0
	DMA_CH2_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 2 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET = 0x000000ac
	DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL3_CTRL
	// Description : Alias for channel 2 CTRL register
	DMA_CH2_AL3_CTRL_OFFSET = 0x000000b0
	DMA_CH2_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH2_AL3_CTRL_RESET  = "-"
	DMA_CH2_AL3_CTRL_MSB    = 31
	DMA_CH2_AL3_CTRL_LSB    = 0
	DMA_CH2_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL3_WRITE_ADDR
	// Description : Alias for channel 2 WRITE_ADDR register
	DMA_CH2_AL3_WRITE_ADDR_OFFSET = 0x000000b4
	DMA_CH2_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH2_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH2_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH2_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH2_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL3_TRANS_COUNT
	// Description : Alias for channel 2 TRANS_COUNT register
	DMA_CH2_AL3_TRANS_COUNT_OFFSET = 0x000000b8
	DMA_CH2_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH2_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH2_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH2_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH2_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH2_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 2 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET = 0x000000bc
	DMA_CH2_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH2_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH2_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH2_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_READ_ADDR
	// Description : DMA Channel 3 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH3_READ_ADDR_OFFSET = 0x000000c0
	DMA_CH3_READ_ADDR_BITS   = 0xffffffff
	DMA_CH3_READ_ADDR_RESET  = 0x00000000
	DMA_CH3_READ_ADDR_MSB    = 31
	DMA_CH3_READ_ADDR_LSB    = 0
	DMA_CH3_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_WRITE_ADDR
	// Description : DMA Channel 3 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH3_WRITE_ADDR_OFFSET = 0x000000c4
	DMA_CH3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH3_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH3_WRITE_ADDR_MSB    = 31
	DMA_CH3_WRITE_ADDR_LSB    = 0
	DMA_CH3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_TRANS_COUNT
	// Description : DMA Channel 3 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH3_TRANS_COUNT_OFFSET = 0x000000c8
	DMA_CH3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH3_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH3_TRANS_COUNT_MSB    = 31
	DMA_CH3_TRANS_COUNT_LSB    = 0
	DMA_CH3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_CTRL_TRIG
	// Description : DMA Channel 3 Control and Status
	DMA_CH3_CTRL_TRIG_OFFSET = 0x000000cc
	DMA_CH3_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH3_CTRL_TRIG_RESET  = 0x00001800
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH3_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH3_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH3_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH3_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH3_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH3_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH3_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH3_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH3_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH3_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH3_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (3).
	DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET  = 0x3
	DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH3_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH3_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH3_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH3_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH3_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH3_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH3_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH3_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH3_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH3_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH3_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH3_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH3_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH3_CTRL_TRIG_EN_MSB    = 0
	DMA_CH3_CTRL_TRIG_EN_LSB    = 0
	DMA_CH3_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL1_CTRL
	// Description : Alias for channel 3 CTRL register
	DMA_CH3_AL1_CTRL_OFFSET = 0x000000d0
	DMA_CH3_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH3_AL1_CTRL_RESET  = "-"
	DMA_CH3_AL1_CTRL_MSB    = 31
	DMA_CH3_AL1_CTRL_LSB    = 0
	DMA_CH3_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL1_READ_ADDR
	// Description : Alias for channel 3 READ_ADDR register
	DMA_CH3_AL1_READ_ADDR_OFFSET = 0x000000d4
	DMA_CH3_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH3_AL1_READ_ADDR_RESET  = "-"
	DMA_CH3_AL1_READ_ADDR_MSB    = 31
	DMA_CH3_AL1_READ_ADDR_LSB    = 0
	DMA_CH3_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL1_WRITE_ADDR
	// Description : Alias for channel 3 WRITE_ADDR register
	DMA_CH3_AL1_WRITE_ADDR_OFFSET = 0x000000d8
	DMA_CH3_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH3_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH3_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH3_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH3_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 3 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET = 0x000000dc
	DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL2_CTRL
	// Description : Alias for channel 3 CTRL register
	DMA_CH3_AL2_CTRL_OFFSET = 0x000000e0
	DMA_CH3_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH3_AL2_CTRL_RESET  = "-"
	DMA_CH3_AL2_CTRL_MSB    = 31
	DMA_CH3_AL2_CTRL_LSB    = 0
	DMA_CH3_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL2_TRANS_COUNT
	// Description : Alias for channel 3 TRANS_COUNT register
	DMA_CH3_AL2_TRANS_COUNT_OFFSET = 0x000000e4
	DMA_CH3_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH3_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH3_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH3_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH3_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL2_READ_ADDR
	// Description : Alias for channel 3 READ_ADDR register
	DMA_CH3_AL2_READ_ADDR_OFFSET = 0x000000e8
	DMA_CH3_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH3_AL2_READ_ADDR_RESET  = "-"
	DMA_CH3_AL2_READ_ADDR_MSB    = 31
	DMA_CH3_AL2_READ_ADDR_LSB    = 0
	DMA_CH3_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 3 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET = 0x000000ec
	DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL3_CTRL
	// Description : Alias for channel 3 CTRL register
	DMA_CH3_AL3_CTRL_OFFSET = 0x000000f0
	DMA_CH3_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH3_AL3_CTRL_RESET  = "-"
	DMA_CH3_AL3_CTRL_MSB    = 31
	DMA_CH3_AL3_CTRL_LSB    = 0
	DMA_CH3_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL3_WRITE_ADDR
	// Description : Alias for channel 3 WRITE_ADDR register
	DMA_CH3_AL3_WRITE_ADDR_OFFSET = 0x000000f4
	DMA_CH3_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH3_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH3_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH3_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH3_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL3_TRANS_COUNT
	// Description : Alias for channel 3 TRANS_COUNT register
	DMA_CH3_AL3_TRANS_COUNT_OFFSET = 0x000000f8
	DMA_CH3_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH3_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH3_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH3_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH3_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH3_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 3 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET = 0x000000fc
	DMA_CH3_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH3_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH3_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH3_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_READ_ADDR
	// Description : DMA Channel 4 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH4_READ_ADDR_OFFSET = 0x00000100
	DMA_CH4_READ_ADDR_BITS   = 0xffffffff
	DMA_CH4_READ_ADDR_RESET  = 0x00000000
	DMA_CH4_READ_ADDR_MSB    = 31
	DMA_CH4_READ_ADDR_LSB    = 0
	DMA_CH4_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_WRITE_ADDR
	// Description : DMA Channel 4 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH4_WRITE_ADDR_OFFSET = 0x00000104
	DMA_CH4_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH4_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH4_WRITE_ADDR_MSB    = 31
	DMA_CH4_WRITE_ADDR_LSB    = 0
	DMA_CH4_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_TRANS_COUNT
	// Description : DMA Channel 4 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH4_TRANS_COUNT_OFFSET = 0x00000108
	DMA_CH4_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH4_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH4_TRANS_COUNT_MSB    = 31
	DMA_CH4_TRANS_COUNT_LSB    = 0
	DMA_CH4_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_CTRL_TRIG
	// Description : DMA Channel 4 Control and Status
	DMA_CH4_CTRL_TRIG_OFFSET = 0x0000010c
	DMA_CH4_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH4_CTRL_TRIG_RESET  = 0x00002000
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH4_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH4_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH4_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH4_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH4_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH4_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH4_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH4_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH4_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH4_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH4_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (4).
	DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET  = 0x4
	DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH4_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH4_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH4_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH4_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH4_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH4_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH4_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH4_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH4_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH4_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH4_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH4_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH4_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH4_CTRL_TRIG_EN_MSB    = 0
	DMA_CH4_CTRL_TRIG_EN_LSB    = 0
	DMA_CH4_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL1_CTRL
	// Description : Alias for channel 4 CTRL register
	DMA_CH4_AL1_CTRL_OFFSET = 0x00000110
	DMA_CH4_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH4_AL1_CTRL_RESET  = "-"
	DMA_CH4_AL1_CTRL_MSB    = 31
	DMA_CH4_AL1_CTRL_LSB    = 0
	DMA_CH4_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL1_READ_ADDR
	// Description : Alias for channel 4 READ_ADDR register
	DMA_CH4_AL1_READ_ADDR_OFFSET = 0x00000114
	DMA_CH4_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH4_AL1_READ_ADDR_RESET  = "-"
	DMA_CH4_AL1_READ_ADDR_MSB    = 31
	DMA_CH4_AL1_READ_ADDR_LSB    = 0
	DMA_CH4_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL1_WRITE_ADDR
	// Description : Alias for channel 4 WRITE_ADDR register
	DMA_CH4_AL1_WRITE_ADDR_OFFSET = 0x00000118
	DMA_CH4_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH4_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH4_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH4_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH4_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 4 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000011c
	DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL2_CTRL
	// Description : Alias for channel 4 CTRL register
	DMA_CH4_AL2_CTRL_OFFSET = 0x00000120
	DMA_CH4_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH4_AL2_CTRL_RESET  = "-"
	DMA_CH4_AL2_CTRL_MSB    = 31
	DMA_CH4_AL2_CTRL_LSB    = 0
	DMA_CH4_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL2_TRANS_COUNT
	// Description : Alias for channel 4 TRANS_COUNT register
	DMA_CH4_AL2_TRANS_COUNT_OFFSET = 0x00000124
	DMA_CH4_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH4_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH4_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH4_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH4_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL2_READ_ADDR
	// Description : Alias for channel 4 READ_ADDR register
	DMA_CH4_AL2_READ_ADDR_OFFSET = 0x00000128
	DMA_CH4_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH4_AL2_READ_ADDR_RESET  = "-"
	DMA_CH4_AL2_READ_ADDR_MSB    = 31
	DMA_CH4_AL2_READ_ADDR_LSB    = 0
	DMA_CH4_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 4 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET = 0x0000012c
	DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL3_CTRL
	// Description : Alias for channel 4 CTRL register
	DMA_CH4_AL3_CTRL_OFFSET = 0x00000130
	DMA_CH4_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH4_AL3_CTRL_RESET  = "-"
	DMA_CH4_AL3_CTRL_MSB    = 31
	DMA_CH4_AL3_CTRL_LSB    = 0
	DMA_CH4_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL3_WRITE_ADDR
	// Description : Alias for channel 4 WRITE_ADDR register
	DMA_CH4_AL3_WRITE_ADDR_OFFSET = 0x00000134
	DMA_CH4_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH4_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH4_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH4_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH4_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL3_TRANS_COUNT
	// Description : Alias for channel 4 TRANS_COUNT register
	DMA_CH4_AL3_TRANS_COUNT_OFFSET = 0x00000138
	DMA_CH4_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH4_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH4_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH4_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH4_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH4_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 4 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET = 0x0000013c
	DMA_CH4_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH4_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH4_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH4_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_READ_ADDR
	// Description : DMA Channel 5 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH5_READ_ADDR_OFFSET = 0x00000140
	DMA_CH5_READ_ADDR_BITS   = 0xffffffff
	DMA_CH5_READ_ADDR_RESET  = 0x00000000
	DMA_CH5_READ_ADDR_MSB    = 31
	DMA_CH5_READ_ADDR_LSB    = 0
	DMA_CH5_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_WRITE_ADDR
	// Description : DMA Channel 5 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH5_WRITE_ADDR_OFFSET = 0x00000144
	DMA_CH5_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH5_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH5_WRITE_ADDR_MSB    = 31
	DMA_CH5_WRITE_ADDR_LSB    = 0
	DMA_CH5_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_TRANS_COUNT
	// Description : DMA Channel 5 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH5_TRANS_COUNT_OFFSET = 0x00000148
	DMA_CH5_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH5_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH5_TRANS_COUNT_MSB    = 31
	DMA_CH5_TRANS_COUNT_LSB    = 0
	DMA_CH5_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_CTRL_TRIG
	// Description : DMA Channel 5 Control and Status
	DMA_CH5_CTRL_TRIG_OFFSET = 0x0000014c
	DMA_CH5_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH5_CTRL_TRIG_RESET  = 0x00002800
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH5_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH5_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH5_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH5_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH5_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH5_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH5_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH5_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH5_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH5_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH5_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (5).
	DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET  = 0x5
	DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH5_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH5_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH5_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH5_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH5_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH5_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH5_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH5_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH5_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH5_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH5_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH5_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH5_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH5_CTRL_TRIG_EN_MSB    = 0
	DMA_CH5_CTRL_TRIG_EN_LSB    = 0
	DMA_CH5_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL1_CTRL
	// Description : Alias for channel 5 CTRL register
	DMA_CH5_AL1_CTRL_OFFSET = 0x00000150
	DMA_CH5_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH5_AL1_CTRL_RESET  = "-"
	DMA_CH5_AL1_CTRL_MSB    = 31
	DMA_CH5_AL1_CTRL_LSB    = 0
	DMA_CH5_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL1_READ_ADDR
	// Description : Alias for channel 5 READ_ADDR register
	DMA_CH5_AL1_READ_ADDR_OFFSET = 0x00000154
	DMA_CH5_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH5_AL1_READ_ADDR_RESET  = "-"
	DMA_CH5_AL1_READ_ADDR_MSB    = 31
	DMA_CH5_AL1_READ_ADDR_LSB    = 0
	DMA_CH5_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL1_WRITE_ADDR
	// Description : Alias for channel 5 WRITE_ADDR register
	DMA_CH5_AL1_WRITE_ADDR_OFFSET = 0x00000158
	DMA_CH5_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH5_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH5_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH5_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH5_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 5 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000015c
	DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL2_CTRL
	// Description : Alias for channel 5 CTRL register
	DMA_CH5_AL2_CTRL_OFFSET = 0x00000160
	DMA_CH5_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH5_AL2_CTRL_RESET  = "-"
	DMA_CH5_AL2_CTRL_MSB    = 31
	DMA_CH5_AL2_CTRL_LSB    = 0
	DMA_CH5_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL2_TRANS_COUNT
	// Description : Alias for channel 5 TRANS_COUNT register
	DMA_CH5_AL2_TRANS_COUNT_OFFSET = 0x00000164
	DMA_CH5_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH5_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH5_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH5_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH5_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL2_READ_ADDR
	// Description : Alias for channel 5 READ_ADDR register
	DMA_CH5_AL2_READ_ADDR_OFFSET = 0x00000168
	DMA_CH5_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH5_AL2_READ_ADDR_RESET  = "-"
	DMA_CH5_AL2_READ_ADDR_MSB    = 31
	DMA_CH5_AL2_READ_ADDR_LSB    = 0
	DMA_CH5_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 5 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET = 0x0000016c
	DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL3_CTRL
	// Description : Alias for channel 5 CTRL register
	DMA_CH5_AL3_CTRL_OFFSET = 0x00000170
	DMA_CH5_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH5_AL3_CTRL_RESET  = "-"
	DMA_CH5_AL3_CTRL_MSB    = 31
	DMA_CH5_AL3_CTRL_LSB    = 0
	DMA_CH5_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL3_WRITE_ADDR
	// Description : Alias for channel 5 WRITE_ADDR register
	DMA_CH5_AL3_WRITE_ADDR_OFFSET = 0x00000174
	DMA_CH5_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH5_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH5_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH5_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH5_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL3_TRANS_COUNT
	// Description : Alias for channel 5 TRANS_COUNT register
	DMA_CH5_AL3_TRANS_COUNT_OFFSET = 0x00000178
	DMA_CH5_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH5_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH5_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH5_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH5_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH5_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 5 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET = 0x0000017c
	DMA_CH5_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH5_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH5_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH5_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_READ_ADDR
	// Description : DMA Channel 6 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH6_READ_ADDR_OFFSET = 0x00000180
	DMA_CH6_READ_ADDR_BITS   = 0xffffffff
	DMA_CH6_READ_ADDR_RESET  = 0x00000000
	DMA_CH6_READ_ADDR_MSB    = 31
	DMA_CH6_READ_ADDR_LSB    = 0
	DMA_CH6_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_WRITE_ADDR
	// Description : DMA Channel 6 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH6_WRITE_ADDR_OFFSET = 0x00000184
	DMA_CH6_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH6_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH6_WRITE_ADDR_MSB    = 31
	DMA_CH6_WRITE_ADDR_LSB    = 0
	DMA_CH6_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_TRANS_COUNT
	// Description : DMA Channel 6 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH6_TRANS_COUNT_OFFSET = 0x00000188
	DMA_CH6_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH6_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH6_TRANS_COUNT_MSB    = 31
	DMA_CH6_TRANS_COUNT_LSB    = 0
	DMA_CH6_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_CTRL_TRIG
	// Description : DMA Channel 6 Control and Status
	DMA_CH6_CTRL_TRIG_OFFSET = 0x0000018c
	DMA_CH6_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH6_CTRL_TRIG_RESET  = 0x00003000
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH6_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH6_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH6_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH6_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH6_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH6_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH6_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH6_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH6_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH6_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH6_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (6).
	DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET  = 0x6
	DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH6_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH6_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH6_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH6_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH6_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH6_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH6_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH6_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH6_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH6_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH6_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH6_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH6_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH6_CTRL_TRIG_EN_MSB    = 0
	DMA_CH6_CTRL_TRIG_EN_LSB    = 0
	DMA_CH6_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL1_CTRL
	// Description : Alias for channel 6 CTRL register
	DMA_CH6_AL1_CTRL_OFFSET = 0x00000190
	DMA_CH6_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH6_AL1_CTRL_RESET  = "-"
	DMA_CH6_AL1_CTRL_MSB    = 31
	DMA_CH6_AL1_CTRL_LSB    = 0
	DMA_CH6_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL1_READ_ADDR
	// Description : Alias for channel 6 READ_ADDR register
	DMA_CH6_AL1_READ_ADDR_OFFSET = 0x00000194
	DMA_CH6_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH6_AL1_READ_ADDR_RESET  = "-"
	DMA_CH6_AL1_READ_ADDR_MSB    = 31
	DMA_CH6_AL1_READ_ADDR_LSB    = 0
	DMA_CH6_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL1_WRITE_ADDR
	// Description : Alias for channel 6 WRITE_ADDR register
	DMA_CH6_AL1_WRITE_ADDR_OFFSET = 0x00000198
	DMA_CH6_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH6_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH6_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH6_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH6_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 6 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000019c
	DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL2_CTRL
	// Description : Alias for channel 6 CTRL register
	DMA_CH6_AL2_CTRL_OFFSET = 0x000001a0
	DMA_CH6_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH6_AL2_CTRL_RESET  = "-"
	DMA_CH6_AL2_CTRL_MSB    = 31
	DMA_CH6_AL2_CTRL_LSB    = 0
	DMA_CH6_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL2_TRANS_COUNT
	// Description : Alias for channel 6 TRANS_COUNT register
	DMA_CH6_AL2_TRANS_COUNT_OFFSET = 0x000001a4
	DMA_CH6_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH6_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH6_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH6_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH6_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL2_READ_ADDR
	// Description : Alias for channel 6 READ_ADDR register
	DMA_CH6_AL2_READ_ADDR_OFFSET = 0x000001a8
	DMA_CH6_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH6_AL2_READ_ADDR_RESET  = "-"
	DMA_CH6_AL2_READ_ADDR_MSB    = 31
	DMA_CH6_AL2_READ_ADDR_LSB    = 0
	DMA_CH6_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 6 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET = 0x000001ac
	DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL3_CTRL
	// Description : Alias for channel 6 CTRL register
	DMA_CH6_AL3_CTRL_OFFSET = 0x000001b0
	DMA_CH6_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH6_AL3_CTRL_RESET  = "-"
	DMA_CH6_AL3_CTRL_MSB    = 31
	DMA_CH6_AL3_CTRL_LSB    = 0
	DMA_CH6_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL3_WRITE_ADDR
	// Description : Alias for channel 6 WRITE_ADDR register
	DMA_CH6_AL3_WRITE_ADDR_OFFSET = 0x000001b4
	DMA_CH6_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH6_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH6_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH6_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH6_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL3_TRANS_COUNT
	// Description : Alias for channel 6 TRANS_COUNT register
	DMA_CH6_AL3_TRANS_COUNT_OFFSET = 0x000001b8
	DMA_CH6_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH6_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH6_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH6_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH6_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH6_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 6 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET = 0x000001bc
	DMA_CH6_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH6_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH6_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH6_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_READ_ADDR
	// Description : DMA Channel 7 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH7_READ_ADDR_OFFSET = 0x000001c0
	DMA_CH7_READ_ADDR_BITS   = 0xffffffff
	DMA_CH7_READ_ADDR_RESET  = 0x00000000
	DMA_CH7_READ_ADDR_MSB    = 31
	DMA_CH7_READ_ADDR_LSB    = 0
	DMA_CH7_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_WRITE_ADDR
	// Description : DMA Channel 7 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH7_WRITE_ADDR_OFFSET = 0x000001c4
	DMA_CH7_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH7_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH7_WRITE_ADDR_MSB    = 31
	DMA_CH7_WRITE_ADDR_LSB    = 0
	DMA_CH7_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_TRANS_COUNT
	// Description : DMA Channel 7 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH7_TRANS_COUNT_OFFSET = 0x000001c8
	DMA_CH7_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH7_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH7_TRANS_COUNT_MSB    = 31
	DMA_CH7_TRANS_COUNT_LSB    = 0
	DMA_CH7_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_CTRL_TRIG
	// Description : DMA Channel 7 Control and Status
	DMA_CH7_CTRL_TRIG_OFFSET = 0x000001cc
	DMA_CH7_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH7_CTRL_TRIG_RESET  = 0x00003800
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH7_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH7_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH7_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH7_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH7_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH7_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH7_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH7_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH7_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH7_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH7_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (7).
	DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET  = 0x7
	DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH7_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH7_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH7_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH7_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH7_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH7_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH7_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH7_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH7_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH7_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH7_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH7_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH7_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH7_CTRL_TRIG_EN_MSB    = 0
	DMA_CH7_CTRL_TRIG_EN_LSB    = 0
	DMA_CH7_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL1_CTRL
	// Description : Alias for channel 7 CTRL register
	DMA_CH7_AL1_CTRL_OFFSET = 0x000001d0
	DMA_CH7_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH7_AL1_CTRL_RESET  = "-"
	DMA_CH7_AL1_CTRL_MSB    = 31
	DMA_CH7_AL1_CTRL_LSB    = 0
	DMA_CH7_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL1_READ_ADDR
	// Description : Alias for channel 7 READ_ADDR register
	DMA_CH7_AL1_READ_ADDR_OFFSET = 0x000001d4
	DMA_CH7_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH7_AL1_READ_ADDR_RESET  = "-"
	DMA_CH7_AL1_READ_ADDR_MSB    = 31
	DMA_CH7_AL1_READ_ADDR_LSB    = 0
	DMA_CH7_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL1_WRITE_ADDR
	// Description : Alias for channel 7 WRITE_ADDR register
	DMA_CH7_AL1_WRITE_ADDR_OFFSET = 0x000001d8
	DMA_CH7_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH7_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH7_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH7_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH7_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 7 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET = 0x000001dc
	DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL2_CTRL
	// Description : Alias for channel 7 CTRL register
	DMA_CH7_AL2_CTRL_OFFSET = 0x000001e0
	DMA_CH7_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH7_AL2_CTRL_RESET  = "-"
	DMA_CH7_AL2_CTRL_MSB    = 31
	DMA_CH7_AL2_CTRL_LSB    = 0
	DMA_CH7_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL2_TRANS_COUNT
	// Description : Alias for channel 7 TRANS_COUNT register
	DMA_CH7_AL2_TRANS_COUNT_OFFSET = 0x000001e4
	DMA_CH7_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH7_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH7_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH7_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH7_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL2_READ_ADDR
	// Description : Alias for channel 7 READ_ADDR register
	DMA_CH7_AL2_READ_ADDR_OFFSET = 0x000001e8
	DMA_CH7_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH7_AL2_READ_ADDR_RESET  = "-"
	DMA_CH7_AL2_READ_ADDR_MSB    = 31
	DMA_CH7_AL2_READ_ADDR_LSB    = 0
	DMA_CH7_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 7 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET = 0x000001ec
	DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL3_CTRL
	// Description : Alias for channel 7 CTRL register
	DMA_CH7_AL3_CTRL_OFFSET = 0x000001f0
	DMA_CH7_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH7_AL3_CTRL_RESET  = "-"
	DMA_CH7_AL3_CTRL_MSB    = 31
	DMA_CH7_AL3_CTRL_LSB    = 0
	DMA_CH7_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL3_WRITE_ADDR
	// Description : Alias for channel 7 WRITE_ADDR register
	DMA_CH7_AL3_WRITE_ADDR_OFFSET = 0x000001f4
	DMA_CH7_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH7_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH7_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH7_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH7_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL3_TRANS_COUNT
	// Description : Alias for channel 7 TRANS_COUNT register
	DMA_CH7_AL3_TRANS_COUNT_OFFSET = 0x000001f8
	DMA_CH7_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH7_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH7_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH7_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH7_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH7_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 7 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET = 0x000001fc
	DMA_CH7_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH7_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH7_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH7_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_READ_ADDR
	// Description : DMA Channel 8 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH8_READ_ADDR_OFFSET = 0x00000200
	DMA_CH8_READ_ADDR_BITS   = 0xffffffff
	DMA_CH8_READ_ADDR_RESET  = 0x00000000
	DMA_CH8_READ_ADDR_MSB    = 31
	DMA_CH8_READ_ADDR_LSB    = 0
	DMA_CH8_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_WRITE_ADDR
	// Description : DMA Channel 8 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH8_WRITE_ADDR_OFFSET = 0x00000204
	DMA_CH8_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH8_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH8_WRITE_ADDR_MSB    = 31
	DMA_CH8_WRITE_ADDR_LSB    = 0
	DMA_CH8_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_TRANS_COUNT
	// Description : DMA Channel 8 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH8_TRANS_COUNT_OFFSET = 0x00000208
	DMA_CH8_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH8_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH8_TRANS_COUNT_MSB    = 31
	DMA_CH8_TRANS_COUNT_LSB    = 0
	DMA_CH8_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_CTRL_TRIG
	// Description : DMA Channel 8 Control and Status
	DMA_CH8_CTRL_TRIG_OFFSET = 0x0000020c
	DMA_CH8_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH8_CTRL_TRIG_RESET  = 0x00004000
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH8_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH8_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH8_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH8_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH8_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH8_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH8_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH8_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH8_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH8_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH8_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (8).
	DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET  = 0x8
	DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH8_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH8_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH8_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH8_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH8_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH8_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH8_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH8_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH8_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH8_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH8_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH8_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH8_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH8_CTRL_TRIG_EN_MSB    = 0
	DMA_CH8_CTRL_TRIG_EN_LSB    = 0
	DMA_CH8_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL1_CTRL
	// Description : Alias for channel 8 CTRL register
	DMA_CH8_AL1_CTRL_OFFSET = 0x00000210
	DMA_CH8_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH8_AL1_CTRL_RESET  = "-"
	DMA_CH8_AL1_CTRL_MSB    = 31
	DMA_CH8_AL1_CTRL_LSB    = 0
	DMA_CH8_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL1_READ_ADDR
	// Description : Alias for channel 8 READ_ADDR register
	DMA_CH8_AL1_READ_ADDR_OFFSET = 0x00000214
	DMA_CH8_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH8_AL1_READ_ADDR_RESET  = "-"
	DMA_CH8_AL1_READ_ADDR_MSB    = 31
	DMA_CH8_AL1_READ_ADDR_LSB    = 0
	DMA_CH8_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL1_WRITE_ADDR
	// Description : Alias for channel 8 WRITE_ADDR register
	DMA_CH8_AL1_WRITE_ADDR_OFFSET = 0x00000218
	DMA_CH8_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH8_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH8_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH8_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH8_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 8 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000021c
	DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL2_CTRL
	// Description : Alias for channel 8 CTRL register
	DMA_CH8_AL2_CTRL_OFFSET = 0x00000220
	DMA_CH8_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH8_AL2_CTRL_RESET  = "-"
	DMA_CH8_AL2_CTRL_MSB    = 31
	DMA_CH8_AL2_CTRL_LSB    = 0
	DMA_CH8_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL2_TRANS_COUNT
	// Description : Alias for channel 8 TRANS_COUNT register
	DMA_CH8_AL2_TRANS_COUNT_OFFSET = 0x00000224
	DMA_CH8_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH8_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH8_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH8_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH8_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL2_READ_ADDR
	// Description : Alias for channel 8 READ_ADDR register
	DMA_CH8_AL2_READ_ADDR_OFFSET = 0x00000228
	DMA_CH8_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH8_AL2_READ_ADDR_RESET  = "-"
	DMA_CH8_AL2_READ_ADDR_MSB    = 31
	DMA_CH8_AL2_READ_ADDR_LSB    = 0
	DMA_CH8_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 8 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET = 0x0000022c
	DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL3_CTRL
	// Description : Alias for channel 8 CTRL register
	DMA_CH8_AL3_CTRL_OFFSET = 0x00000230
	DMA_CH8_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH8_AL3_CTRL_RESET  = "-"
	DMA_CH8_AL3_CTRL_MSB    = 31
	DMA_CH8_AL3_CTRL_LSB    = 0
	DMA_CH8_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL3_WRITE_ADDR
	// Description : Alias for channel 8 WRITE_ADDR register
	DMA_CH8_AL3_WRITE_ADDR_OFFSET = 0x00000234
	DMA_CH8_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH8_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH8_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH8_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH8_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL3_TRANS_COUNT
	// Description : Alias for channel 8 TRANS_COUNT register
	DMA_CH8_AL3_TRANS_COUNT_OFFSET = 0x00000238
	DMA_CH8_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH8_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH8_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH8_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH8_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH8_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 8 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET = 0x0000023c
	DMA_CH8_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH8_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH8_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH8_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_READ_ADDR
	// Description : DMA Channel 9 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH9_READ_ADDR_OFFSET = 0x00000240
	DMA_CH9_READ_ADDR_BITS   = 0xffffffff
	DMA_CH9_READ_ADDR_RESET  = 0x00000000
	DMA_CH9_READ_ADDR_MSB    = 31
	DMA_CH9_READ_ADDR_LSB    = 0
	DMA_CH9_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_WRITE_ADDR
	// Description : DMA Channel 9 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH9_WRITE_ADDR_OFFSET = 0x00000244
	DMA_CH9_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH9_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH9_WRITE_ADDR_MSB    = 31
	DMA_CH9_WRITE_ADDR_LSB    = 0
	DMA_CH9_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_TRANS_COUNT
	// Description : DMA Channel 9 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH9_TRANS_COUNT_OFFSET = 0x00000248
	DMA_CH9_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH9_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH9_TRANS_COUNT_MSB    = 31
	DMA_CH9_TRANS_COUNT_LSB    = 0
	DMA_CH9_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_CTRL_TRIG
	// Description : DMA Channel 9 Control and Status
	DMA_CH9_CTRL_TRIG_OFFSET = 0x0000024c
	DMA_CH9_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH9_CTRL_TRIG_RESET  = 0x00004800
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH9_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH9_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH9_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH9_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH9_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH9_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH9_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH9_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH9_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH9_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH9_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (9).
	DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET  = 0x9
	DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH9_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH9_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH9_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH9_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH9_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH9_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH9_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH9_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH9_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH9_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH9_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH9_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH9_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH9_CTRL_TRIG_EN_MSB    = 0
	DMA_CH9_CTRL_TRIG_EN_LSB    = 0
	DMA_CH9_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL1_CTRL
	// Description : Alias for channel 9 CTRL register
	DMA_CH9_AL1_CTRL_OFFSET = 0x00000250
	DMA_CH9_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH9_AL1_CTRL_RESET  = "-"
	DMA_CH9_AL1_CTRL_MSB    = 31
	DMA_CH9_AL1_CTRL_LSB    = 0
	DMA_CH9_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL1_READ_ADDR
	// Description : Alias for channel 9 READ_ADDR register
	DMA_CH9_AL1_READ_ADDR_OFFSET = 0x00000254
	DMA_CH9_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH9_AL1_READ_ADDR_RESET  = "-"
	DMA_CH9_AL1_READ_ADDR_MSB    = 31
	DMA_CH9_AL1_READ_ADDR_LSB    = 0
	DMA_CH9_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL1_WRITE_ADDR
	// Description : Alias for channel 9 WRITE_ADDR register
	DMA_CH9_AL1_WRITE_ADDR_OFFSET = 0x00000258
	DMA_CH9_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH9_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH9_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH9_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH9_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 9 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000025c
	DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL2_CTRL
	// Description : Alias for channel 9 CTRL register
	DMA_CH9_AL2_CTRL_OFFSET = 0x00000260
	DMA_CH9_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH9_AL2_CTRL_RESET  = "-"
	DMA_CH9_AL2_CTRL_MSB    = 31
	DMA_CH9_AL2_CTRL_LSB    = 0
	DMA_CH9_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL2_TRANS_COUNT
	// Description : Alias for channel 9 TRANS_COUNT register
	DMA_CH9_AL2_TRANS_COUNT_OFFSET = 0x00000264
	DMA_CH9_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH9_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH9_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH9_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH9_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL2_READ_ADDR
	// Description : Alias for channel 9 READ_ADDR register
	DMA_CH9_AL2_READ_ADDR_OFFSET = 0x00000268
	DMA_CH9_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH9_AL2_READ_ADDR_RESET  = "-"
	DMA_CH9_AL2_READ_ADDR_MSB    = 31
	DMA_CH9_AL2_READ_ADDR_LSB    = 0
	DMA_CH9_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 9 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET = 0x0000026c
	DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL3_CTRL
	// Description : Alias for channel 9 CTRL register
	DMA_CH9_AL3_CTRL_OFFSET = 0x00000270
	DMA_CH9_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH9_AL3_CTRL_RESET  = "-"
	DMA_CH9_AL3_CTRL_MSB    = 31
	DMA_CH9_AL3_CTRL_LSB    = 0
	DMA_CH9_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL3_WRITE_ADDR
	// Description : Alias for channel 9 WRITE_ADDR register
	DMA_CH9_AL3_WRITE_ADDR_OFFSET = 0x00000274
	DMA_CH9_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH9_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH9_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH9_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH9_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL3_TRANS_COUNT
	// Description : Alias for channel 9 TRANS_COUNT register
	DMA_CH9_AL3_TRANS_COUNT_OFFSET = 0x00000278
	DMA_CH9_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH9_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH9_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH9_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH9_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH9_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 9 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET = 0x0000027c
	DMA_CH9_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH9_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH9_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH9_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_READ_ADDR
	// Description : DMA Channel 10 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH10_READ_ADDR_OFFSET = 0x00000280
	DMA_CH10_READ_ADDR_BITS   = 0xffffffff
	DMA_CH10_READ_ADDR_RESET  = 0x00000000
	DMA_CH10_READ_ADDR_MSB    = 31
	DMA_CH10_READ_ADDR_LSB    = 0
	DMA_CH10_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_WRITE_ADDR
	// Description : DMA Channel 10 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH10_WRITE_ADDR_OFFSET = 0x00000284
	DMA_CH10_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH10_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH10_WRITE_ADDR_MSB    = 31
	DMA_CH10_WRITE_ADDR_LSB    = 0
	DMA_CH10_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_TRANS_COUNT
	// Description : DMA Channel 10 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH10_TRANS_COUNT_OFFSET = 0x00000288
	DMA_CH10_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH10_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH10_TRANS_COUNT_MSB    = 31
	DMA_CH10_TRANS_COUNT_LSB    = 0
	DMA_CH10_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_CTRL_TRIG
	// Description : DMA Channel 10 Control and Status
	DMA_CH10_CTRL_TRIG_OFFSET = 0x0000028c
	DMA_CH10_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH10_CTRL_TRIG_RESET  = 0x00005000
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH10_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH10_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH10_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH10_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH10_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH10_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH10_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH10_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH10_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH10_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH10_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (10).
	DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET  = 0xa
	DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH10_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH10_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH10_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH10_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH10_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH10_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH10_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH10_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH10_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH10_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH10_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH10_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH10_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH10_CTRL_TRIG_EN_MSB    = 0
	DMA_CH10_CTRL_TRIG_EN_LSB    = 0
	DMA_CH10_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL1_CTRL
	// Description : Alias for channel 10 CTRL register
	DMA_CH10_AL1_CTRL_OFFSET = 0x00000290
	DMA_CH10_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH10_AL1_CTRL_RESET  = "-"
	DMA_CH10_AL1_CTRL_MSB    = 31
	DMA_CH10_AL1_CTRL_LSB    = 0
	DMA_CH10_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL1_READ_ADDR
	// Description : Alias for channel 10 READ_ADDR register
	DMA_CH10_AL1_READ_ADDR_OFFSET = 0x00000294
	DMA_CH10_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH10_AL1_READ_ADDR_RESET  = "-"
	DMA_CH10_AL1_READ_ADDR_MSB    = 31
	DMA_CH10_AL1_READ_ADDR_LSB    = 0
	DMA_CH10_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL1_WRITE_ADDR
	// Description : Alias for channel 10 WRITE_ADDR register
	DMA_CH10_AL1_WRITE_ADDR_OFFSET = 0x00000298
	DMA_CH10_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH10_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH10_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH10_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH10_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 10 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET = 0x0000029c
	DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL2_CTRL
	// Description : Alias for channel 10 CTRL register
	DMA_CH10_AL2_CTRL_OFFSET = 0x000002a0
	DMA_CH10_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH10_AL2_CTRL_RESET  = "-"
	DMA_CH10_AL2_CTRL_MSB    = 31
	DMA_CH10_AL2_CTRL_LSB    = 0
	DMA_CH10_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL2_TRANS_COUNT
	// Description : Alias for channel 10 TRANS_COUNT register
	DMA_CH10_AL2_TRANS_COUNT_OFFSET = 0x000002a4
	DMA_CH10_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH10_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH10_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH10_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH10_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL2_READ_ADDR
	// Description : Alias for channel 10 READ_ADDR register
	DMA_CH10_AL2_READ_ADDR_OFFSET = 0x000002a8
	DMA_CH10_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH10_AL2_READ_ADDR_RESET  = "-"
	DMA_CH10_AL2_READ_ADDR_MSB    = 31
	DMA_CH10_AL2_READ_ADDR_LSB    = 0
	DMA_CH10_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 10 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET = 0x000002ac
	DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL3_CTRL
	// Description : Alias for channel 10 CTRL register
	DMA_CH10_AL3_CTRL_OFFSET = 0x000002b0
	DMA_CH10_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH10_AL3_CTRL_RESET  = "-"
	DMA_CH10_AL3_CTRL_MSB    = 31
	DMA_CH10_AL3_CTRL_LSB    = 0
	DMA_CH10_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL3_WRITE_ADDR
	// Description : Alias for channel 10 WRITE_ADDR register
	DMA_CH10_AL3_WRITE_ADDR_OFFSET = 0x000002b4
	DMA_CH10_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH10_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH10_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH10_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH10_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL3_TRANS_COUNT
	// Description : Alias for channel 10 TRANS_COUNT register
	DMA_CH10_AL3_TRANS_COUNT_OFFSET = 0x000002b8
	DMA_CH10_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH10_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH10_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH10_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH10_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH10_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 10 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET = 0x000002bc
	DMA_CH10_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH10_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH10_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH10_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_READ_ADDR
	// Description : DMA Channel 11 Read Address pointer
	//               This register updates automatically each time a read completes.
	//               The current value is the next address to be read by this
	//               channel.
	DMA_CH11_READ_ADDR_OFFSET = 0x000002c0
	DMA_CH11_READ_ADDR_BITS   = 0xffffffff
	DMA_CH11_READ_ADDR_RESET  = 0x00000000
	DMA_CH11_READ_ADDR_MSB    = 31
	DMA_CH11_READ_ADDR_LSB    = 0
	DMA_CH11_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_WRITE_ADDR
	// Description : DMA Channel 11 Write Address pointer
	//               This register updates automatically each time a write
	//               completes. The current value is the next address to be written
	//               by this channel.
	DMA_CH11_WRITE_ADDR_OFFSET = 0x000002c4
	DMA_CH11_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH11_WRITE_ADDR_RESET  = 0x00000000
	DMA_CH11_WRITE_ADDR_MSB    = 31
	DMA_CH11_WRITE_ADDR_LSB    = 0
	DMA_CH11_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_TRANS_COUNT
	// Description : DMA Channel 11 Transfer Count
	//               Program the number of bus transfers a channel will perform
	//               before halting. Note that, if transfers are larger than one
	//               byte in size, this is not equal to the number of bytes
	//               transferred (see CTRL_DATA_SIZE).
	//
	//               When the channel is active, reading this register shows the
	//               number of transfers remaining, updating automatically each time
	//               a write transfer completes.
	//
	//               Writing this register sets the RELOAD value for the transfer
	//               counter. Each time this channel is triggered, the RELOAD value
	//               is copied into the live transfer counter. The channel can be
	//               started multiple times, and will perform the same number of
	//               transfers each time, as programmed by most recent write.
	//
	//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
	//               is used as a trigger, the written value is used immediately as
	//               the length of the new transfer sequence, as well as being
	//               written to RELOAD.
	DMA_CH11_TRANS_COUNT_OFFSET = 0x000002c8
	DMA_CH11_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH11_TRANS_COUNT_RESET  = 0x00000000
	DMA_CH11_TRANS_COUNT_MSB    = 31
	DMA_CH11_TRANS_COUNT_LSB    = 0
	DMA_CH11_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_CTRL_TRIG
	// Description : DMA Channel 11 Control and Status
	DMA_CH11_CTRL_TRIG_OFFSET = 0x000002cc
	DMA_CH11_CTRL_TRIG_BITS   = 0xe1ffffff
	DMA_CH11_CTRL_TRIG_RESET  = 0x00005800
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_AHB_ERROR
	// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
	//               halts when it encounters any bus error, and always raises its
	//               channel IRQ flag.
	DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS   = 0x80000000
	DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB    = 31
	DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB    = 31
	DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_READ_ERROR
	// Description : If 1, the channel received a read bus error. Write one to
	//               clear.
	//               READ_ADDR shows the approximate address where the bus error was
	//               encountered (will not to be earlier, or more than 3 transfers
	//               later)
	DMA_CH11_CTRL_TRIG_READ_ERROR_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_READ_ERROR_BITS   = 0x40000000
	DMA_CH11_CTRL_TRIG_READ_ERROR_MSB    = 30
	DMA_CH11_CTRL_TRIG_READ_ERROR_LSB    = 30
	DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_WRITE_ERROR
	// Description : If 1, the channel received a write bus error. Write one to
	//               clear.
	//               WRITE_ADDR shows the approximate address where the bus error
	//               was encountered (will not to be earlier, or more than 5
	//               transfers later)
	DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS   = 0x20000000
	DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB    = 29
	DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB    = 29
	DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS = "WC"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_BUSY
	// Description : This flag goes high when the channel starts a new transfer
	//               sequence, and low when the last transfer of that sequence
	//               completes. Clearing EN while BUSY is high pauses the channel,
	//               and BUSY will stay high while paused.
	//
	//               To terminate a sequence early (and clear the BUSY flag), see
	//               CHAN_ABORT.
	DMA_CH11_CTRL_TRIG_BUSY_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_BUSY_BITS   = 0x01000000
	DMA_CH11_CTRL_TRIG_BUSY_MSB    = 24
	DMA_CH11_CTRL_TRIG_BUSY_LSB    = 24
	DMA_CH11_CTRL_TRIG_BUSY_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_SNIFF_EN
	// Description : If 1, this channel's data transfers are visible to the sniff
	//               hardware, and each transfer will advance the state of the
	//               checksum. This only applies if the sniff hardware is enabled,
	//               and has this channel selected.
	//
	//               This allows checksum to be enabled or disabled on a
	//               per-control- block basis.
	DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS   = 0x00800000
	DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB    = 23
	DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB    = 23
	DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_BSWAP
	// Description : Apply byte-swap transformation to DMA data.
	//               For byte data, this has no effect. For halfword data, the two
	//               bytes of each halfword are swapped. For word data, the four
	//               bytes of each word are swapped to reverse order.
	DMA_CH11_CTRL_TRIG_BSWAP_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_BSWAP_BITS   = 0x00400000
	DMA_CH11_CTRL_TRIG_BSWAP_MSB    = 22
	DMA_CH11_CTRL_TRIG_BSWAP_LSB    = 22
	DMA_CH11_CTRL_TRIG_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_IRQ_QUIET
	// Description : In QUIET mode, the channel does not generate IRQs at the end of
	//               every transfer block. Instead, an IRQ is raised when NULL is
	//               written to a trigger register, indicating the end of a control
	//               block chain.
	//
	//               This reduces the number of interrupts to be serviced by the CPU
	//               when transferring a DMA chain of many small control blocks.
	DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS   = 0x00200000
	DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB    = 21
	DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB    = 21
	DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_TREQ_SEL
	// Description : Select a Transfer Request signal.
	//               The channel uses the transfer request signal to pace its data
	//               transfer rate. Sources for TREQ signals are internal (TIMERS)
	//               or external (DREQ, a Data Request from the system).
	//               0x0 to 0x3a -> select DREQ n as TREQ
	//               0x3b -> Select Timer 0 as TREQ
	//               0x3c -> Select Timer 1 as TREQ
	//               0x3d -> Select Timer 2 as TREQ (Optional)
	//               0x3e -> Select Timer 3 as TREQ (Optional)
	//               0x3f -> Permanent request, for unpaced transfers.
	DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET           = 0x00
	DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS            = 0x001f8000
	DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB             = 20
	DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB             = 15
	DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS          = "RW"
	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    = 0x3b
	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    = 0x3c
	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    = 0x3d
	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    = 0x3e
	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT = 0x3f
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_CHAIN_TO
	// Description : When this channel completes, it will trigger the channel
	//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
	//               channel)_.
	//               Reset value is equal to channel number (11).
	DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET  = 0xb
	DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS   = 0x00007800
	DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB    = 14
	DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB    = 11
	DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_RING_SEL
	// Description : Select whether RING_SIZE applies to read or write addresses.
	//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
	//               boundary. If 1, write addresses are wrapped.
	DMA_CH11_CTRL_TRIG_RING_SEL_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_RING_SEL_BITS   = 0x00000400
	DMA_CH11_CTRL_TRIG_RING_SEL_MSB    = 10
	DMA_CH11_CTRL_TRIG_RING_SEL_LSB    = 10
	DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_RING_SIZE
	// Description : Size of address wrap region. If 0, don't wrap. For values n >
	//               0, only the lower n bits of the address will change. This wraps
	//               the address on a (1 << n) byte boundary, facilitating access to
	//               naturally-aligned ring buffers.
	//
	//               Ring sizes between 2 and 32768 bytes are possible. This can
	//               apply to either read or write addresses, based on value of
	//               RING_SEL.
	//               0x0 -> RING_NONE
	DMA_CH11_CTRL_TRIG_RING_SIZE_RESET           = 0x0
	DMA_CH11_CTRL_TRIG_RING_SIZE_BITS            = 0x000003c0
	DMA_CH11_CTRL_TRIG_RING_SIZE_MSB             = 9
	DMA_CH11_CTRL_TRIG_RING_SIZE_LSB             = 6
	DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS          = "RW"
	DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE = 0x0
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_INCR_WRITE
	// Description : If 1, the write address increments with each transfer. If 0,
	//               each write is directed to the same, initial address.
	//
	//               Generally this should be disabled for memory-to-peripheral
	//               transfers.
	DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS   = 0x00000020
	DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB    = 5
	DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB    = 5
	DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_INCR_READ
	// Description : If 1, the read address increments with each transfer. If 0,
	//               each read is directed to the same, initial address.
	//
	//               Generally this should be disabled for peripheral-to-memory
	//               transfers.
	DMA_CH11_CTRL_TRIG_INCR_READ_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_INCR_READ_BITS   = 0x00000010
	DMA_CH11_CTRL_TRIG_INCR_READ_MSB    = 4
	DMA_CH11_CTRL_TRIG_INCR_READ_LSB    = 4
	DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_DATA_SIZE
	// Description : Set the size of each bus transfer (byte/halfword/word).
	//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
	//               with each transfer.
	//               0x0 -> SIZE_BYTE
	//               0x1 -> SIZE_HALFWORD
	//               0x2 -> SIZE_WORD
	DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET               = 0x0
	DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS                = 0x0000000c
	DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB                 = 3
	DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB                 = 2
	DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS              = "RW"
	DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     = 0x0
	DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD = 0x1
	DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     = 0x2
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY
	// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
	//               scheduling: in each scheduling round, all high priority
	//               channels are considered first, and then only a single low
	//               priority channel, before returning to the high priority
	//               channels.
	//
	//               This only affects the order in which the DMA schedules
	//               channels. The DMA's bus priority is not changed. If the DMA is
	//               not saturated then a low priority channel will see no loss of
	//               throughput.
	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS   = 0x00000002
	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB    = 1
	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB    = 1
	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_CH11_CTRL_TRIG_EN
	// Description : DMA Channel Enable.
	//               When 1, the channel will respond to triggering events, which
	//               will cause it to become BUSY and start transferring data. When
	//               0, the channel will ignore triggers, stop issuing transfers,
	//               and pause the current transfer sequence (i.e. BUSY will remain
	//               high if already high)
	DMA_CH11_CTRL_TRIG_EN_RESET  = 0x0
	DMA_CH11_CTRL_TRIG_EN_BITS   = 0x00000001
	DMA_CH11_CTRL_TRIG_EN_MSB    = 0
	DMA_CH11_CTRL_TRIG_EN_LSB    = 0
	DMA_CH11_CTRL_TRIG_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL1_CTRL
	// Description : Alias for channel 11 CTRL register
	DMA_CH11_AL1_CTRL_OFFSET = 0x000002d0
	DMA_CH11_AL1_CTRL_BITS   = 0xffffffff
	DMA_CH11_AL1_CTRL_RESET  = "-"
	DMA_CH11_AL1_CTRL_MSB    = 31
	DMA_CH11_AL1_CTRL_LSB    = 0
	DMA_CH11_AL1_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL1_READ_ADDR
	// Description : Alias for channel 11 READ_ADDR register
	DMA_CH11_AL1_READ_ADDR_OFFSET = 0x000002d4
	DMA_CH11_AL1_READ_ADDR_BITS   = 0xffffffff
	DMA_CH11_AL1_READ_ADDR_RESET  = "-"
	DMA_CH11_AL1_READ_ADDR_MSB    = 31
	DMA_CH11_AL1_READ_ADDR_LSB    = 0
	DMA_CH11_AL1_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL1_WRITE_ADDR
	// Description : Alias for channel 11 WRITE_ADDR register
	DMA_CH11_AL1_WRITE_ADDR_OFFSET = 0x000002d8
	DMA_CH11_AL1_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH11_AL1_WRITE_ADDR_RESET  = "-"
	DMA_CH11_AL1_WRITE_ADDR_MSB    = 31
	DMA_CH11_AL1_WRITE_ADDR_LSB    = 0
	DMA_CH11_AL1_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL1_TRANS_COUNT_TRIG
	// Description : Alias for channel 11 TRANS_COUNT register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET = 0x000002dc
	DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS   = 0xffffffff
	DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET  = "-"
	DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB    = 31
	DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB    = 0
	DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL2_CTRL
	// Description : Alias for channel 11 CTRL register
	DMA_CH11_AL2_CTRL_OFFSET = 0x000002e0
	DMA_CH11_AL2_CTRL_BITS   = 0xffffffff
	DMA_CH11_AL2_CTRL_RESET  = "-"
	DMA_CH11_AL2_CTRL_MSB    = 31
	DMA_CH11_AL2_CTRL_LSB    = 0
	DMA_CH11_AL2_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL2_TRANS_COUNT
	// Description : Alias for channel 11 TRANS_COUNT register
	DMA_CH11_AL2_TRANS_COUNT_OFFSET = 0x000002e4
	DMA_CH11_AL2_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH11_AL2_TRANS_COUNT_RESET  = "-"
	DMA_CH11_AL2_TRANS_COUNT_MSB    = 31
	DMA_CH11_AL2_TRANS_COUNT_LSB    = 0
	DMA_CH11_AL2_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL2_READ_ADDR
	// Description : Alias for channel 11 READ_ADDR register
	DMA_CH11_AL2_READ_ADDR_OFFSET = 0x000002e8
	DMA_CH11_AL2_READ_ADDR_BITS   = 0xffffffff
	DMA_CH11_AL2_READ_ADDR_RESET  = "-"
	DMA_CH11_AL2_READ_ADDR_MSB    = 31
	DMA_CH11_AL2_READ_ADDR_LSB    = 0
	DMA_CH11_AL2_READ_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL2_WRITE_ADDR_TRIG
	// Description : Alias for channel 11 WRITE_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET = 0x000002ec
	DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET  = "-"
	DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB    = 31
	DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB    = 0
	DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL3_CTRL
	// Description : Alias for channel 11 CTRL register
	DMA_CH11_AL3_CTRL_OFFSET = 0x000002f0
	DMA_CH11_AL3_CTRL_BITS   = 0xffffffff
	DMA_CH11_AL3_CTRL_RESET  = "-"
	DMA_CH11_AL3_CTRL_MSB    = 31
	DMA_CH11_AL3_CTRL_LSB    = 0
	DMA_CH11_AL3_CTRL_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL3_WRITE_ADDR
	// Description : Alias for channel 11 WRITE_ADDR register
	DMA_CH11_AL3_WRITE_ADDR_OFFSET = 0x000002f4
	DMA_CH11_AL3_WRITE_ADDR_BITS   = 0xffffffff
	DMA_CH11_AL3_WRITE_ADDR_RESET  = "-"
	DMA_CH11_AL3_WRITE_ADDR_MSB    = 31
	DMA_CH11_AL3_WRITE_ADDR_LSB    = 0
	DMA_CH11_AL3_WRITE_ADDR_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL3_TRANS_COUNT
	// Description : Alias for channel 11 TRANS_COUNT register
	DMA_CH11_AL3_TRANS_COUNT_OFFSET = 0x000002f8
	DMA_CH11_AL3_TRANS_COUNT_BITS   = 0xffffffff
	DMA_CH11_AL3_TRANS_COUNT_RESET  = "-"
	DMA_CH11_AL3_TRANS_COUNT_MSB    = 31
	DMA_CH11_AL3_TRANS_COUNT_LSB    = 0
	DMA_CH11_AL3_TRANS_COUNT_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_CH11_AL3_READ_ADDR_TRIG
	// Description : Alias for channel 11 READ_ADDR register
	//               This is a trigger register (0xc). Writing a nonzero value will
	//               reload the channel counter and start the channel.
	DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET = 0x000002fc
	DMA_CH11_AL3_READ_ADDR_TRIG_BITS   = 0xffffffff
	DMA_CH11_AL3_READ_ADDR_TRIG_RESET  = "-"
	DMA_CH11_AL3_READ_ADDR_TRIG_MSB    = 31
	DMA_CH11_AL3_READ_ADDR_TRIG_LSB    = 0
	DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_INTR
	// Description : Interrupt Status (raw)
	//               Raw interrupt status for DMA Channels 0..15. Bit n corresponds
	//               to channel n. Ignores any masking or forcing. Channel
	//               interrupts can be cleared by writing a bit mask to INTR, INTS0
	//               or INTS1.
	//
	//               Channel interrupts can be routed to either of two system-level
	//               IRQs based on INTE0 and INTE1.
	//
	//               This can be used vector different channel interrupts to
	//               different ISRs: this might be done to allow NVIC IRQ preemption
	//               for more time-critical channels, or to spread IRQ load across
	//               different cores.
	//
	//               It is also valid to ignore this behaviour and just use
	//               INTE0/INTS0/IRQ 0.
	DMA_INTR_OFFSET = 0x00000400
	DMA_INTR_BITS   = 0x0000ffff
	DMA_INTR_RESET  = 0x00000000
	DMA_INTR_MSB    = 15
	DMA_INTR_LSB    = 0
	DMA_INTR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_INTE0
	// Description : Interrupt Enables for IRQ 0
	//               Set bit n to pass interrupts from channel n to DMA IRQ 0.
	DMA_INTE0_OFFSET = 0x00000404
	DMA_INTE0_BITS   = 0x0000ffff
	DMA_INTE0_RESET  = 0x00000000
	DMA_INTE0_MSB    = 15
	DMA_INTE0_LSB    = 0
	DMA_INTE0_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_INTF0
	// Description : Force Interrupts
	//               Write 1s to force the corresponding bits in INTE0. The
	//               interrupt remains asserted until INTF0 is cleared.
	DMA_INTF0_OFFSET = 0x00000408
	DMA_INTF0_BITS   = 0x0000ffff
	DMA_INTF0_RESET  = 0x00000000
	DMA_INTF0_MSB    = 15
	DMA_INTF0_LSB    = 0
	DMA_INTF0_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_INTS0
	// Description : Interrupt Status for IRQ 0
	//               Indicates active channel interrupt requests which are currently
	//               causing IRQ 0 to be asserted.
	//               Channel interrupts can be cleared by writing a bit mask here.
	DMA_INTS0_OFFSET = 0x0000040c
	DMA_INTS0_BITS   = 0x0000ffff
	DMA_INTS0_RESET  = 0x00000000
	DMA_INTS0_MSB    = 15
	DMA_INTS0_LSB    = 0
	DMA_INTS0_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_INTE1
	// Description : Interrupt Enables for IRQ 1
	//               Set bit n to pass interrupts from channel n to DMA IRQ 1.
	DMA_INTE1_OFFSET = 0x00000414
	DMA_INTE1_BITS   = 0x0000ffff
	DMA_INTE1_RESET  = 0x00000000
	DMA_INTE1_MSB    = 15
	DMA_INTE1_LSB    = 0
	DMA_INTE1_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_INTF1
	// Description : Force Interrupts for IRQ 1
	//               Write 1s to force the corresponding bits in INTE0. The
	//               interrupt remains asserted until INTF0 is cleared.
	DMA_INTF1_OFFSET = 0x00000418
	DMA_INTF1_BITS   = 0x0000ffff
	DMA_INTF1_RESET  = 0x00000000
	DMA_INTF1_MSB    = 15
	DMA_INTF1_LSB    = 0
	DMA_INTF1_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_INTS1
	// Description : Interrupt Status (masked) for IRQ 1
	//               Indicates active channel interrupt requests which are currently
	//               causing IRQ 1 to be asserted.
	//               Channel interrupts can be cleared by writing a bit mask here.
	DMA_INTS1_OFFSET = 0x0000041c
	DMA_INTS1_BITS   = 0x0000ffff
	DMA_INTS1_RESET  = 0x00000000
	DMA_INTS1_MSB    = 15
	DMA_INTS1_LSB    = 0
	DMA_INTS1_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_TIMER0
	// Description : Pacing (X/Y) Fractional Timer
	//               The pacing timer produces TREQ assertions at a rate set by
	//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
	//               cycles and therefore can only generate TREQs at a rate of 1 per
	//               sys_clk (i.e. permanent TREQ) or less.
	DMA_TIMER0_OFFSET = 0x00000420
	DMA_TIMER0_BITS   = 0xffffffff
	DMA_TIMER0_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER0_X
	// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
	//               fractional timer.
	DMA_TIMER0_X_RESET  = 0x0000
	DMA_TIMER0_X_BITS   = 0xffff0000
	DMA_TIMER0_X_MSB    = 31
	DMA_TIMER0_X_LSB    = 16
	DMA_TIMER0_X_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER0_Y
	// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
	//               fractional timer.
	DMA_TIMER0_Y_RESET  = 0x0000
	DMA_TIMER0_Y_BITS   = 0x0000ffff
	DMA_TIMER0_Y_MSB    = 15
	DMA_TIMER0_Y_LSB    = 0
	DMA_TIMER0_Y_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_TIMER1
	// Description : Pacing (X/Y) Fractional Timer
	//               The pacing timer produces TREQ assertions at a rate set by
	//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
	//               cycles and therefore can only generate TREQs at a rate of 1 per
	//               sys_clk (i.e. permanent TREQ) or less.
	DMA_TIMER1_OFFSET = 0x00000424
	DMA_TIMER1_BITS   = 0xffffffff
	DMA_TIMER1_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER1_X
	// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
	//               fractional timer.
	DMA_TIMER1_X_RESET  = 0x0000
	DMA_TIMER1_X_BITS   = 0xffff0000
	DMA_TIMER1_X_MSB    = 31
	DMA_TIMER1_X_LSB    = 16
	DMA_TIMER1_X_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER1_Y
	// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
	//               fractional timer.
	DMA_TIMER1_Y_RESET  = 0x0000
	DMA_TIMER1_Y_BITS   = 0x0000ffff
	DMA_TIMER1_Y_MSB    = 15
	DMA_TIMER1_Y_LSB    = 0
	DMA_TIMER1_Y_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_TIMER2
	// Description : Pacing (X/Y) Fractional Timer
	//               The pacing timer produces TREQ assertions at a rate set by
	//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
	//               cycles and therefore can only generate TREQs at a rate of 1 per
	//               sys_clk (i.e. permanent TREQ) or less.
	DMA_TIMER2_OFFSET = 0x00000428
	DMA_TIMER2_BITS   = 0xffffffff
	DMA_TIMER2_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER2_X
	// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
	//               fractional timer.
	DMA_TIMER2_X_RESET  = 0x0000
	DMA_TIMER2_X_BITS   = 0xffff0000
	DMA_TIMER2_X_MSB    = 31
	DMA_TIMER2_X_LSB    = 16
	DMA_TIMER2_X_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER2_Y
	// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
	//               fractional timer.
	DMA_TIMER2_Y_RESET  = 0x0000
	DMA_TIMER2_Y_BITS   = 0x0000ffff
	DMA_TIMER2_Y_MSB    = 15
	DMA_TIMER2_Y_LSB    = 0
	DMA_TIMER2_Y_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_TIMER3
	// Description : Pacing (X/Y) Fractional Timer
	//               The pacing timer produces TREQ assertions at a rate set by
	//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
	//               cycles and therefore can only generate TREQs at a rate of 1 per
	//               sys_clk (i.e. permanent TREQ) or less.
	DMA_TIMER3_OFFSET = 0x0000042c
	DMA_TIMER3_BITS   = 0xffffffff
	DMA_TIMER3_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER3_X
	// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
	//               fractional timer.
	DMA_TIMER3_X_RESET  = 0x0000
	DMA_TIMER3_X_BITS   = 0xffff0000
	DMA_TIMER3_X_MSB    = 31
	DMA_TIMER3_X_LSB    = 16
	DMA_TIMER3_X_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_TIMER3_Y
	// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
	//               fractional timer.
	DMA_TIMER3_Y_RESET  = 0x0000
	DMA_TIMER3_Y_BITS   = 0x0000ffff
	DMA_TIMER3_Y_MSB    = 15
	DMA_TIMER3_Y_LSB    = 0
	DMA_TIMER3_Y_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_MULTI_CHAN_TRIGGER
	// Description : Trigger one or more channels simultaneously
	//               Each bit in this register corresponds to a DMA channel. Writing
	//               a 1 to the relevant bit is the same as writing to that
	//               channel's trigger register; the channel will start if it is
	//               currently enabled and not already busy.
	DMA_MULTI_CHAN_TRIGGER_OFFSET = 0x00000430
	DMA_MULTI_CHAN_TRIGGER_BITS   = 0x0000ffff
	DMA_MULTI_CHAN_TRIGGER_RESET  = 0x00000000
	DMA_MULTI_CHAN_TRIGGER_MSB    = 15
	DMA_MULTI_CHAN_TRIGGER_LSB    = 0
	DMA_MULTI_CHAN_TRIGGER_ACCESS = "SC"
	// =============================================================================
	// Register    : DMA_SNIFF_CTRL
	// Description : Sniffer Control
	DMA_SNIFF_CTRL_OFFSET = 0x00000434
	DMA_SNIFF_CTRL_BITS   = 0x00000fff
	DMA_SNIFF_CTRL_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_SNIFF_CTRL_OUT_INV
	// Description : If set, the result appears inverted (bitwise complement) when
	//               read. This does not affect the way the checksum is calculated;
	//               the result is transformed on-the-fly between the result
	//               register and the bus.
	DMA_SNIFF_CTRL_OUT_INV_RESET  = 0x0
	DMA_SNIFF_CTRL_OUT_INV_BITS   = 0x00000800
	DMA_SNIFF_CTRL_OUT_INV_MSB    = 11
	DMA_SNIFF_CTRL_OUT_INV_LSB    = 11
	DMA_SNIFF_CTRL_OUT_INV_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_SNIFF_CTRL_OUT_REV
	// Description : If set, the result appears bit-reversed when read. This does
	//               not affect the way the checksum is calculated; the result is
	//               transformed on-the-fly between the result register and the bus.
	DMA_SNIFF_CTRL_OUT_REV_RESET  = 0x0
	DMA_SNIFF_CTRL_OUT_REV_BITS   = 0x00000400
	DMA_SNIFF_CTRL_OUT_REV_MSB    = 10
	DMA_SNIFF_CTRL_OUT_REV_LSB    = 10
	DMA_SNIFF_CTRL_OUT_REV_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_SNIFF_CTRL_BSWAP
	// Description : Locally perform a byte reverse on the sniffed data, before
	//               feeding into checksum.
	//
	//               Note that the sniff hardware is downstream of the DMA channel
	//               byteswap performed in the read master: if channel CTRL_BSWAP
	//               and SNIFF_CTRL_BSWAP are both enabled, their effects cancel
	//               from the sniffer's point of view.
	DMA_SNIFF_CTRL_BSWAP_RESET  = 0x0
	DMA_SNIFF_CTRL_BSWAP_BITS   = 0x00000200
	DMA_SNIFF_CTRL_BSWAP_MSB    = 9
	DMA_SNIFF_CTRL_BSWAP_LSB    = 9
	DMA_SNIFF_CTRL_BSWAP_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_SNIFF_CTRL_CALC
	// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial)
	//               0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit
	//               reversed data
	//               0x2 -> Calculate a CRC-16-CCITT
	//               0x3 -> Calculate a CRC-16-CCITT with bit reversed data
	//               0xe -> XOR reduction over all data. == 1 if the total 1
	//               population count is odd.
	//               0xf -> Calculate a simple 32-bit checksum (addition with a 32
	//               bit accumulator)
	DMA_SNIFF_CTRL_CALC_RESET        = 0x0
	DMA_SNIFF_CTRL_CALC_BITS         = 0x000001e0
	DMA_SNIFF_CTRL_CALC_MSB          = 8
	DMA_SNIFF_CTRL_CALC_LSB          = 5
	DMA_SNIFF_CTRL_CALC_ACCESS       = "RW"
	DMA_SNIFF_CTRL_CALC_VALUE_CRC32  = 0x0
	DMA_SNIFF_CTRL_CALC_VALUE_CRC32R = 0x1
	DMA_SNIFF_CTRL_CALC_VALUE_CRC16  = 0x2
	DMA_SNIFF_CTRL_CALC_VALUE_CRC16R = 0x3
	DMA_SNIFF_CTRL_CALC_VALUE_EVEN   = 0xe
	DMA_SNIFF_CTRL_CALC_VALUE_SUM    = 0xf
	// -----------------------------------------------------------------------------
	// Field       : DMA_SNIFF_CTRL_DMACH
	// Description : DMA channel for Sniffer to observe
	DMA_SNIFF_CTRL_DMACH_RESET  = 0x0
	DMA_SNIFF_CTRL_DMACH_BITS   = 0x0000001e
	DMA_SNIFF_CTRL_DMACH_MSB    = 4
	DMA_SNIFF_CTRL_DMACH_LSB    = 1
	DMA_SNIFF_CTRL_DMACH_ACCESS = "RW"
	// -----------------------------------------------------------------------------
	// Field       : DMA_SNIFF_CTRL_EN
	// Description : Enable sniffer
	DMA_SNIFF_CTRL_EN_RESET  = 0x0
	DMA_SNIFF_CTRL_EN_BITS   = 0x00000001
	DMA_SNIFF_CTRL_EN_MSB    = 0
	DMA_SNIFF_CTRL_EN_LSB    = 0
	DMA_SNIFF_CTRL_EN_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_SNIFF_DATA
	// Description : Data accumulator for sniff hardware
	//               Write an initial seed value here before starting a DMA transfer
	//               on the channel indicated by SNIFF_CTRL_DMACH. The hardware will
	//               update this register each time it observes a read from the
	//               indicated channel. Once the channel completes, the final result
	//               can be read from this register.
	DMA_SNIFF_DATA_OFFSET = 0x00000438
	DMA_SNIFF_DATA_BITS   = 0xffffffff
	DMA_SNIFF_DATA_RESET  = 0x00000000
	DMA_SNIFF_DATA_MSB    = 31
	DMA_SNIFF_DATA_LSB    = 0
	DMA_SNIFF_DATA_ACCESS = "RW"
	// =============================================================================
	// Register    : DMA_FIFO_LEVELS
	// Description : Debug RAF, WAF, TDF levels
	DMA_FIFO_LEVELS_OFFSET = 0x00000440
	DMA_FIFO_LEVELS_BITS   = 0x00ffffff
	DMA_FIFO_LEVELS_RESET  = 0x00000000
	// -----------------------------------------------------------------------------
	// Field       : DMA_FIFO_LEVELS_RAF_LVL
	// Description : Current Read-Address-FIFO fill level
	DMA_FIFO_LEVELS_RAF_LVL_RESET  = 0x00
	DMA_FIFO_LEVELS_RAF_LVL_BITS   = 0x00ff0000
	DMA_FIFO_LEVELS_RAF_LVL_MSB    = 23
	DMA_FIFO_LEVELS_RAF_LVL_LSB    = 16
	DMA_FIFO_LEVELS_RAF_LVL_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_FIFO_LEVELS_WAF_LVL
	// Description : Current Write-Address-FIFO fill level
	DMA_FIFO_LEVELS_WAF_LVL_RESET  = 0x00
	DMA_FIFO_LEVELS_WAF_LVL_BITS   = 0x0000ff00
	DMA_FIFO_LEVELS_WAF_LVL_MSB    = 15
	DMA_FIFO_LEVELS_WAF_LVL_LSB    = 8
	DMA_FIFO_LEVELS_WAF_LVL_ACCESS = "RO"
	// -----------------------------------------------------------------------------
	// Field       : DMA_FIFO_LEVELS_TDF_LVL
	// Description : Current Transfer-Data-FIFO fill level
	DMA_FIFO_LEVELS_TDF_LVL_RESET  = 0x00
	DMA_FIFO_LEVELS_TDF_LVL_BITS   = 0x000000ff
	DMA_FIFO_LEVELS_TDF_LVL_MSB    = 7
	DMA_FIFO_LEVELS_TDF_LVL_LSB    = 0
	DMA_FIFO_LEVELS_TDF_LVL_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CHAN_ABORT
	// Description : Abort an in-progress transfer sequence on one or more channels
	//               Each bit corresponds to a channel. Writing a 1 aborts whatever
	//               transfer sequence is in progress on that channel. The bit will
	//               remain high until any in-flight transfers have been flushed
	//               through the address and data FIFOs.
	//
	//               After writing, this register must be polled until it returns
	//               all-zero. Until this point, it is unsafe to restart the
	//               channel.
	DMA_CHAN_ABORT_OFFSET = 0x00000444
	DMA_CHAN_ABORT_BITS   = 0x0000ffff
	DMA_CHAN_ABORT_RESET  = 0x00000000
	DMA_CHAN_ABORT_MSB    = 15
	DMA_CHAN_ABORT_LSB    = 0
	DMA_CHAN_ABORT_ACCESS = "SC"
	// =============================================================================
	// Register    : DMA_N_CHANNELS
	// Description : The number of channels this DMA instance is equipped with. This
	//               DMA supports up to 16 hardware channels, but can be configured
	//               with as few as one, to minimise silicon area.
	DMA_N_CHANNELS_OFFSET = 0x00000448
	DMA_N_CHANNELS_BITS   = 0x0000001f
	DMA_N_CHANNELS_RESET  = "-"
	DMA_N_CHANNELS_MSB    = 4
	DMA_N_CHANNELS_LSB    = 0
	DMA_N_CHANNELS_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH0_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH0_DBG_CTDREQ_OFFSET = 0x00000800
	DMA_CH0_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH0_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH0_DBG_CTDREQ_MSB    = 5
	DMA_CH0_DBG_CTDREQ_LSB    = 0
	DMA_CH0_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH0_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH0_DBG_TCR_OFFSET = 0x00000804
	DMA_CH0_DBG_TCR_BITS   = 0xffffffff
	DMA_CH0_DBG_TCR_RESET  = 0x00000000
	DMA_CH0_DBG_TCR_MSB    = 31
	DMA_CH0_DBG_TCR_LSB    = 0
	DMA_CH0_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH1_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH1_DBG_CTDREQ_OFFSET = 0x00000840
	DMA_CH1_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH1_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH1_DBG_CTDREQ_MSB    = 5
	DMA_CH1_DBG_CTDREQ_LSB    = 0
	DMA_CH1_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH1_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH1_DBG_TCR_OFFSET = 0x00000844
	DMA_CH1_DBG_TCR_BITS   = 0xffffffff
	DMA_CH1_DBG_TCR_RESET  = 0x00000000
	DMA_CH1_DBG_TCR_MSB    = 31
	DMA_CH1_DBG_TCR_LSB    = 0
	DMA_CH1_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH2_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH2_DBG_CTDREQ_OFFSET = 0x00000880
	DMA_CH2_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH2_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH2_DBG_CTDREQ_MSB    = 5
	DMA_CH2_DBG_CTDREQ_LSB    = 0
	DMA_CH2_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH2_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH2_DBG_TCR_OFFSET = 0x00000884
	DMA_CH2_DBG_TCR_BITS   = 0xffffffff
	DMA_CH2_DBG_TCR_RESET  = 0x00000000
	DMA_CH2_DBG_TCR_MSB    = 31
	DMA_CH2_DBG_TCR_LSB    = 0
	DMA_CH2_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH3_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH3_DBG_CTDREQ_OFFSET = 0x000008c0
	DMA_CH3_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH3_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH3_DBG_CTDREQ_MSB    = 5
	DMA_CH3_DBG_CTDREQ_LSB    = 0
	DMA_CH3_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH3_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH3_DBG_TCR_OFFSET = 0x000008c4
	DMA_CH3_DBG_TCR_BITS   = 0xffffffff
	DMA_CH3_DBG_TCR_RESET  = 0x00000000
	DMA_CH3_DBG_TCR_MSB    = 31
	DMA_CH3_DBG_TCR_LSB    = 0
	DMA_CH3_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH4_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH4_DBG_CTDREQ_OFFSET = 0x00000900
	DMA_CH4_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH4_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH4_DBG_CTDREQ_MSB    = 5
	DMA_CH4_DBG_CTDREQ_LSB    = 0
	DMA_CH4_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH4_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH4_DBG_TCR_OFFSET = 0x00000904
	DMA_CH4_DBG_TCR_BITS   = 0xffffffff
	DMA_CH4_DBG_TCR_RESET  = 0x00000000
	DMA_CH4_DBG_TCR_MSB    = 31
	DMA_CH4_DBG_TCR_LSB    = 0
	DMA_CH4_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH5_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH5_DBG_CTDREQ_OFFSET = 0x00000940
	DMA_CH5_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH5_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH5_DBG_CTDREQ_MSB    = 5
	DMA_CH5_DBG_CTDREQ_LSB    = 0
	DMA_CH5_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH5_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH5_DBG_TCR_OFFSET = 0x00000944
	DMA_CH5_DBG_TCR_BITS   = 0xffffffff
	DMA_CH5_DBG_TCR_RESET  = 0x00000000
	DMA_CH5_DBG_TCR_MSB    = 31
	DMA_CH5_DBG_TCR_LSB    = 0
	DMA_CH5_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH6_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH6_DBG_CTDREQ_OFFSET = 0x00000980
	DMA_CH6_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH6_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH6_DBG_CTDREQ_MSB    = 5
	DMA_CH6_DBG_CTDREQ_LSB    = 0
	DMA_CH6_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH6_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH6_DBG_TCR_OFFSET = 0x00000984
	DMA_CH6_DBG_TCR_BITS   = 0xffffffff
	DMA_CH6_DBG_TCR_RESET  = 0x00000000
	DMA_CH6_DBG_TCR_MSB    = 31
	DMA_CH6_DBG_TCR_LSB    = 0
	DMA_CH6_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH7_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH7_DBG_CTDREQ_OFFSET = 0x000009c0
	DMA_CH7_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH7_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH7_DBG_CTDREQ_MSB    = 5
	DMA_CH7_DBG_CTDREQ_LSB    = 0
	DMA_CH7_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH7_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH7_DBG_TCR_OFFSET = 0x000009c4
	DMA_CH7_DBG_TCR_BITS   = 0xffffffff
	DMA_CH7_DBG_TCR_RESET  = 0x00000000
	DMA_CH7_DBG_TCR_MSB    = 31
	DMA_CH7_DBG_TCR_LSB    = 0
	DMA_CH7_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH8_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH8_DBG_CTDREQ_OFFSET = 0x00000a00
	DMA_CH8_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH8_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH8_DBG_CTDREQ_MSB    = 5
	DMA_CH8_DBG_CTDREQ_LSB    = 0
	DMA_CH8_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH8_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH8_DBG_TCR_OFFSET = 0x00000a04
	DMA_CH8_DBG_TCR_BITS   = 0xffffffff
	DMA_CH8_DBG_TCR_RESET  = 0x00000000
	DMA_CH8_DBG_TCR_MSB    = 31
	DMA_CH8_DBG_TCR_LSB    = 0
	DMA_CH8_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH9_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH9_DBG_CTDREQ_OFFSET = 0x00000a40
	DMA_CH9_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH9_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH9_DBG_CTDREQ_MSB    = 5
	DMA_CH9_DBG_CTDREQ_LSB    = 0
	DMA_CH9_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH9_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH9_DBG_TCR_OFFSET = 0x00000a44
	DMA_CH9_DBG_TCR_BITS   = 0xffffffff
	DMA_CH9_DBG_TCR_RESET  = 0x00000000
	DMA_CH9_DBG_TCR_MSB    = 31
	DMA_CH9_DBG_TCR_LSB    = 0
	DMA_CH9_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH10_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH10_DBG_CTDREQ_OFFSET = 0x00000a80
	DMA_CH10_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH10_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH10_DBG_CTDREQ_MSB    = 5
	DMA_CH10_DBG_CTDREQ_LSB    = 0
	DMA_CH10_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH10_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH10_DBG_TCR_OFFSET = 0x00000a84
	DMA_CH10_DBG_TCR_BITS   = 0xffffffff
	DMA_CH10_DBG_TCR_RESET  = 0x00000000
	DMA_CH10_DBG_TCR_MSB    = 31
	DMA_CH10_DBG_TCR_LSB    = 0
	DMA_CH10_DBG_TCR_ACCESS = "RO"
	// =============================================================================
	// Register    : DMA_CH11_DBG_CTDREQ
	// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
	//               expects it can perform on the peripheral without
	//               overflow/underflow. Write any value: clears the counter, and
	//               cause channel to re-initiate DREQ handshake.
	DMA_CH11_DBG_CTDREQ_OFFSET = 0x00000ac0
	DMA_CH11_DBG_CTDREQ_BITS   = 0x0000003f
	DMA_CH11_DBG_CTDREQ_RESET  = 0x00000000
	DMA_CH11_DBG_CTDREQ_MSB    = 5
	DMA_CH11_DBG_CTDREQ_LSB    = 0
	DMA_CH11_DBG_CTDREQ_ACCESS = "WC"
	// =============================================================================
	// Register    : DMA_CH11_DBG_TCR
	// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
	//               of the next transfer
	DMA_CH11_DBG_TCR_OFFSET = 0x00000ac4
	DMA_CH11_DBG_TCR_BITS   = 0xffffffff
	DMA_CH11_DBG_TCR_RESET  = 0x00000000
	DMA_CH11_DBG_TCR_MSB    = 31
	DMA_CH11_DBG_TCR_LSB    = 0
	DMA_CH11_DBG_TCR_ACCESS = "RO"

// =============================================================================
) // end const block