671 (126.37 % of base) - System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector512`1[ubyte]
; Assembly listing for method System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector512`1[ubyte] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 17 single block inlinees; 9 inlinees without PGO data
+; 0 inlinees with PGO data; 34 single block inlinees; 27 inlinees without PGO data
; Final local variable assignments
;
-; V00 RetBuf [V00,T09] ( 4, 4 ) byref -> rbx single-def
+; V00 RetBuf [V00,T01] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[ubyte]>
-; V02 arg1 [V02,T10] ( 3, 3 ) ubyte -> rsi single-def
-; V03 OutArgs [V03 ] ( 1, 1 ) struct (64) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
-; V04 tmp1 [V04,T18] ( 2, 4 ) simd32 -> [rbp-0x50] spill-single-def "impAppendStmt"
-; V05 tmp2 [V05,T19] ( 2, 4 ) simd32 -> [rbp-0x70] do-not-enreg[HS] hidden-struct-arg "spilled call-like call argument"
-; V06 tmp3 [V06,T15] ( 3, 6 ) simd32 -> [rbp-0x90] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V07 tmp4 [V07,T20] ( 2, 4 ) simd16 -> [rbp-0xA0] spill-single-def "impAppendStmt"
+; V02 arg1 [V02,T02] ( 3, 3 ) ubyte -> rsi single-def
+;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
+; V04 tmp1 [V04,T25] ( 2, 4 ) simd32 -> mm0 "impAppendStmt"
+; V05 tmp2 [V05,T26] ( 2, 4 ) simd32 -> mm1 "spilled call-like call argument"
+; V06 tmp3 [V06,T19] ( 3, 6 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V07 tmp4 [V07,T27] ( 2, 4 ) simd16 -> mm1 "impAppendStmt"
;* V08 tmp5 [V08 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
-; V09 tmp6 [V09,T16] ( 3, 6 ) simd16 -> [rbp-0xB0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V09 tmp6 [V09,T20] ( 3, 6 ) simd16 -> [rbp-0x10] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V10 tmp7 [V10 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V11 tmp8 [V11 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V12 tmp9 [V12 ] ( 2, 5 ) struct ( 8) [rbp-0xB8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V13 tmp10 [V13,T01] ( 5, 17 ) int -> r15 "Inline stloc first use temp"
-; V14 tmp11 [V14 ] ( 2, 10 ) struct ( 8) [rbp-0xC0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V12 tmp9 [V12 ] ( 9, 9 ) struct ( 8) [rbp-0x18] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V13 tmp10 [V13,T11] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V14 tmp11 [V14 ] ( 9, 18 ) struct ( 8) [rbp-0x20] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V15 tmp12 [V15 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V16 tmp13 [V16 ] ( 2, 5 ) struct ( 8) [rbp-0xC8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V17 tmp14 [V17,T02] ( 5, 17 ) int -> r13 "Inline stloc first use temp"
-; V18 tmp15 [V18 ] ( 2, 10 ) struct ( 8) [rbp-0xD0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V19 tmp16 [V19 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V20 tmp17 [V20,T21] ( 3, 3 ) simd16 -> [rbp-0xE0] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-; V21 tmp18 [V21,T17] ( 3, 6 ) simd16 -> [rbp-0xF0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-;* V22 tmp19 [V22 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V23 tmp20 [V23 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V24 tmp21 [V24 ] ( 2, 5 ) struct ( 8) [rbp-0xF8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V25 tmp22 [V25,T03] ( 5, 17 ) int -> r15 "Inline stloc first use temp"
-; V26 tmp23 [V26 ] ( 2, 10 ) struct ( 8) [rbp-0x100] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V27 tmp24 [V27 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V28 tmp25 [V28 ] ( 2, 5 ) struct ( 8) [rbp-0x108] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V29 tmp26 [V29,T04] ( 5, 17 ) int -> r13 "Inline stloc first use temp"
-; V30 tmp27 [V30 ] ( 2, 10 ) struct ( 8) [rbp-0x110] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V16 tmp13 [V16 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V17 tmp14 [V17 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V18 tmp15 [V18 ] ( 9, 9 ) struct ( 8) [rbp-0x28] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V19 tmp16 [V19,T12] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V20 tmp17 [V20 ] ( 9, 18 ) struct ( 8) [rbp-0x30] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V21 tmp18 [V21 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V22 tmp19 [V22 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V23 tmp20 [V23 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V24 tmp21 [V24,T29] ( 3, 3 ) simd16 -> [rbp-0x40] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V25 tmp22 [V25,T21] ( 3, 6 ) simd16 -> [rbp-0x50] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V26 tmp23 [V26 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V27 tmp24 [V27 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V28 tmp25 [V28 ] ( 9, 9 ) struct ( 8) [rbp-0x58] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V29 tmp26 [V29,T13] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V30 tmp27 [V30 ] ( 9, 18 ) struct ( 8) [rbp-0x60] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V31 tmp28 [V31 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V32 tmp29 [V32,T22] ( 3, 3 ) simd16 -> [rbp-0x120] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-;* V33 tmp30 [V33 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V34 tmp31 [V34,T23] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V35 tmp32 [V35,T24] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V36 tmp33 [V36,T11] ( 2, 2 ) long -> r15 "field V10._00 (fldOffset=0x0)" P-INDEP
-; V37 tmp34 [V37,T12] ( 2, 2 ) long -> rdi "field V11._00 (fldOffset=0x0)" P-INDEP
-; V38 tmp35 [V38 ] ( 2, 5 ) long -> [rbp-0xB8] do-not-enreg[X] addr-exposed "field V12._00 (fldOffset=0x0)" P-DEP
-; V39 tmp36 [V39 ] ( 2, 9 ) long -> [rbp-0xC0] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
-; V40 tmp37 [V40 ] ( 2, 5 ) long -> [rbp-0xC8] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
-; V41 tmp38 [V41 ] ( 2, 9 ) long -> [rbp-0xD0] do-not-enreg[X] addr-exposed "field V18._00 (fldOffset=0x0)" P-DEP
-; V42 tmp39 [V42,T13] ( 2, 2 ) long -> r15 "field V22._00 (fldOffset=0x0)" P-INDEP
-; V43 tmp40 [V43,T14] ( 2, 2 ) long -> rsi "field V23._00 (fldOffset=0x0)" P-INDEP
-; V44 tmp41 [V44 ] ( 2, 5 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "field V24._00 (fldOffset=0x0)" P-DEP
-; V45 tmp42 [V45 ] ( 2, 9 ) long -> [rbp-0x100] do-not-enreg[X] addr-exposed "field V26._00 (fldOffset=0x0)" P-DEP
-; V46 tmp43 [V46 ] ( 2, 5 ) long -> [rbp-0x108] do-not-enreg[X] addr-exposed "field V28._00 (fldOffset=0x0)" P-DEP
-; V47 tmp44 [V47 ] ( 2, 9 ) long -> [rbp-0x110] do-not-enreg[X] addr-exposed "field V30._00 (fldOffset=0x0)" P-DEP
-; V48 cse0 [V48,T00] ( 6, 18 ) int -> r14 hoist "CSE #01: aggressive"
-; V49 cse1 [V49,T05] ( 3, 12 ) long -> r13 "CSE #02: aggressive"
-; V50 cse2 [V50,T06] ( 3, 12 ) long -> r12 "CSE #03: aggressive"
-; V51 cse3 [V51,T07] ( 3, 12 ) long -> r13 "CSE #04: aggressive"
-; V52 cse4 [V52,T08] ( 3, 12 ) long -> r12 "CSE #05: aggressive"
+;* V32 tmp29 [V32 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V33 tmp30 [V33 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V34 tmp31 [V34 ] ( 9, 9 ) struct ( 8) [rbp-0x68] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V35 tmp32 [V35,T14] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V36 tmp33 [V36 ] ( 9, 18 ) struct ( 8) [rbp-0x70] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V37 tmp34 [V37 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V38 tmp35 [V38 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V39 tmp36 [V39 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V40 tmp37 [V40,T30] ( 3, 3 ) simd16 -> [rbp-0x80] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V41 tmp38 [V41 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V42 tmp39 [V42,T22] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V43 tmp40 [V43,T28] ( 2, 4 ) simd16 -> mm2 "impAppendStmt"
+;* V44 tmp41 [V44 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
+; V45 tmp42 [V45,T23] ( 3, 6 ) simd16 -> [rbp-0x90] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V46 tmp43 [V46 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V47 tmp44 [V47 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V48 tmp45 [V48 ] ( 9, 9 ) struct ( 8) [rbp-0x98] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V49 tmp46 [V49,T15] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V50 tmp47 [V50 ] ( 9, 18 ) struct ( 8) [rbp-0xA0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V51 tmp48 [V51 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V52 tmp49 [V52 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V53 tmp50 [V53 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V54 tmp51 [V54 ] ( 9, 9 ) struct ( 8) [rbp-0xA8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V55 tmp52 [V55,T16] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V56 tmp53 [V56 ] ( 9, 18 ) struct ( 8) [rbp-0xB0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V57 tmp54 [V57 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V58 tmp55 [V58 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V59 tmp56 [V59 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V60 tmp57 [V60,T31] ( 3, 3 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V61 tmp58 [V61,T24] ( 3, 6 ) simd16 -> [rbp-0xD0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V62 tmp59 [V62 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V63 tmp60 [V63 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V64 tmp61 [V64 ] ( 9, 9 ) struct ( 8) [rbp-0xD8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V65 tmp62 [V65,T17] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V66 tmp63 [V66 ] ( 9, 18 ) struct ( 8) [rbp-0xE0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V67 tmp64 [V67 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V68 tmp65 [V68 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V69 tmp66 [V69 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V70 tmp67 [V70 ] ( 9, 9 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V71 tmp68 [V71,T18] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V72 tmp69 [V72 ] ( 9, 18 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V73 tmp70 [V73 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V74 tmp71 [V74 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V75 tmp72 [V75 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V76 tmp73 [V76,T32] ( 3, 3 ) simd16 -> [rbp-0x100] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V77 tmp74 [V77 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+;* V78 tmp75 [V78 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[ubyte]>
+; V79 tmp76 [V79,T35] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V80 tmp77 [V80,T36] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V81 tmp78 [V81,T03] ( 2, 2 ) long -> rsi "field V10._00 (fldOffset=0x0)" P-INDEP
+; V82 tmp79 [V82,T04] ( 2, 2 ) long -> rax "field V11._00 (fldOffset=0x0)" P-INDEP
+; V83 tmp80 [V83 ] ( 9, 9 ) long -> [rbp-0x18] do-not-enreg[X] addr-exposed "field V12._00 (fldOffset=0x0)" P-DEP
+; V84 tmp81 [V84 ] ( 9, 17 ) long -> [rbp-0x20] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
+; V85 tmp82 [V85 ] ( 9, 9 ) long -> [rbp-0x28] do-not-enreg[X] addr-exposed "field V18._00 (fldOffset=0x0)" P-DEP
+; V86 tmp83 [V86 ] ( 9, 17 ) long -> [rbp-0x30] do-not-enreg[X] addr-exposed "field V20._00 (fldOffset=0x0)" P-DEP
+; V87 tmp84 [V87,T05] ( 2, 2 ) long -> rsi "field V26._00 (fldOffset=0x0)" P-INDEP
+; V88 tmp85 [V88,T06] ( 2, 2 ) long -> rax "field V27._00 (fldOffset=0x0)" P-INDEP
+; V89 tmp86 [V89 ] ( 9, 9 ) long -> [rbp-0x58] do-not-enreg[X] addr-exposed "field V28._00 (fldOffset=0x0)" P-DEP
+; V90 tmp87 [V90 ] ( 9, 17 ) long -> [rbp-0x60] do-not-enreg[X] addr-exposed "field V30._00 (fldOffset=0x0)" P-DEP
+; V91 tmp88 [V91 ] ( 9, 9 ) long -> [rbp-0x68] do-not-enreg[X] addr-exposed "field V34._00 (fldOffset=0x0)" P-DEP
+; V92 tmp89 [V92 ] ( 9, 17 ) long -> [rbp-0x70] do-not-enreg[X] addr-exposed "field V36._00 (fldOffset=0x0)" P-DEP
+; V93 tmp90 [V93,T07] ( 2, 2 ) long -> rsi "field V46._00 (fldOffset=0x0)" P-INDEP
+; V94 tmp91 [V94,T08] ( 2, 2 ) long -> rax "field V47._00 (fldOffset=0x0)" P-INDEP
+; V95 tmp92 [V95 ] ( 9, 9 ) long -> [rbp-0x98] do-not-enreg[X] addr-exposed "field V48._00 (fldOffset=0x0)" P-DEP
+; V96 tmp93 [V96 ] ( 9, 17 ) long -> [rbp-0xA0] do-not-enreg[X] addr-exposed "field V50._00 (fldOffset=0x0)" P-DEP
+; V97 tmp94 [V97 ] ( 9, 9 ) long -> [rbp-0xA8] do-not-enreg[X] addr-exposed "field V54._00 (fldOffset=0x0)" P-DEP
+; V98 tmp95 [V98 ] ( 9, 17 ) long -> [rbp-0xB0] do-not-enreg[X] addr-exposed "field V56._00 (fldOffset=0x0)" P-DEP
+; V99 tmp96 [V99,T09] ( 2, 2 ) long -> rsi "field V62._00 (fldOffset=0x0)" P-INDEP
+; V100 tmp97 [V100,T10] ( 2, 2 ) long -> rax "field V63._00 (fldOffset=0x0)" P-INDEP
+; V101 tmp98 [V101 ] ( 9, 9 ) long -> [rbp-0xD8] do-not-enreg[X] addr-exposed "field V64._00 (fldOffset=0x0)" P-DEP
+; V102 tmp99 [V102 ] ( 9, 17 ) long -> [rbp-0xE0] do-not-enreg[X] addr-exposed "field V66._00 (fldOffset=0x0)" P-DEP
+; V103 tmp100 [V103 ] ( 9, 9 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V70._00 (fldOffset=0x0)" P-DEP
+; V104 tmp101 [V104 ] ( 9, 17 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V72._00 (fldOffset=0x0)" P-DEP
+; V105 tmp102 [V105,T33] ( 2, 2 ) simd32 -> mm0 "field V78._lower (fldOffset=0x0)" P-INDEP
+; V106 tmp103 [V106,T34] ( 2, 2 ) simd32 -> mm1 "field V78._upper (fldOffset=0x20)" P-INDEP
+; V107 cse0 [V107,T00] ( 65, 65 ) int -> rcx "CSE #01: aggressive"
;
-; Lcl frame size = 312
+; Lcl frame size = 256
G_M7625_IG01:
push rbp
- push r15
- push r14
- push r13
- push r12
- push rbx
- sub rsp, 312
- lea rbp, [rsp+0x160]
- mov rbx, rdi
- ;; size=28 bbWeight=1 PerfScore 7.00
+ sub rsp, 256
+ lea rbp, [rsp+0x100]
+ ;; size=16 bbWeight=1 PerfScore 1.75
G_M7625_IG02:
vmovups ymm0, ymmword ptr [rbp+0x10]
- vmovups ymmword ptr [rbp-0x90], ymm0
vmovaps ymm1, ymm0
- vmovaps xmmword ptr [rbp-0xB0], xmm1
- mov rdi, qword ptr [rbp-0xB0]
- mov qword ptr [rbp-0xC0], rdi
- xor r15d, r15d
- movzx r14, sil
- ;; size=46 bbWeight=1 PerfScore 8.75
+ vmovaps xmmword ptr [rbp-0x10], xmm1
+ mov rax, qword ptr [rbp-0x10]
+ mov qword ptr [rbp-0x20], rax
+ movzx rax, byte ptr [rbp-0x20]
+ movzx rcx, sil
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x18], al
+ movzx rax, byte ptr [rbp-0x1F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x17], al
+ movzx rax, byte ptr [rbp-0x1E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x16], al
+ movzx rax, byte ptr [rbp-0x1D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x15], al
+ movzx rax, byte ptr [rbp-0x1C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x14], al
+ movzx rax, byte ptr [rbp-0x1B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x13], al
+ movzx rax, byte ptr [rbp-0x1A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x12], al
+ movzx rax, byte ptr [rbp-0x19]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x11], al
+ mov rsi, qword ptr [rbp-0x18]
+ mov rax, qword ptr [rbp-0x08]
+ mov qword ptr [rbp-0x30], rax
+ movzx rax, byte ptr [rbp-0x30]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x28], al
+ movzx rax, byte ptr [rbp-0x2F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x27], al
+ movzx rax, byte ptr [rbp-0x2E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x26], al
+ movzx rax, byte ptr [rbp-0x2D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x25], al
+ movzx rax, byte ptr [rbp-0x2C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x24], al
+ movzx rax, byte ptr [rbp-0x2B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x23], al
+ movzx rax, byte ptr [rbp-0x2A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x22], al
+ ;; size=203 bbWeight=1 PerfScore 419.25
G_M7625_IG03:
- lea rdi, [rbp-0xC0]
- movsxd r13, r15d
- movzx rdi, byte ptr [rdi+r13]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0xB8]
- mov byte ptr [rdi+r13], al
- inc r15d
- cmp r15d, 8
- jl SHORT G_M7625_IG03
- ;; size=50 bbWeight=4 PerfScore 37.00
+ movzx rax, byte ptr [rbp-0x29]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x21], al
+ mov rax, qword ptr [rbp-0x28]
+ mov qword ptr [rbp-0x40], rsi
+ mov qword ptr [rbp-0x38], rax
+ vmovaps xmm1, xmmword ptr [rbp-0x40]
+ vextractf128 xmm0, ymm0, 1
+ vmovaps xmmword ptr [rbp-0x50], xmm0
+ mov rax, qword ptr [rbp-0x50]
+ mov qword ptr [rbp-0x60], rax
+ movzx rax, byte ptr [rbp-0x60]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x58], al
+ movzx rax, byte ptr [rbp-0x5F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x57], al
+ movzx rax, byte ptr [rbp-0x5E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x56], al
+ movzx rax, byte ptr [rbp-0x5D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x55], al
+ movzx rax, byte ptr [rbp-0x5C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x54], al
+ movzx rax, byte ptr [rbp-0x5B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x53], al
+ movzx rax, byte ptr [rbp-0x5A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x52], al
+ movzx rax, byte ptr [rbp-0x59]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x51], al
+ mov rsi, qword ptr [rbp-0x58]
+ mov rax, qword ptr [rbp-0x48]
+ mov qword ptr [rbp-0x70], rax
+ movzx rax, byte ptr [rbp-0x70]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x68], al
+ movzx rax, byte ptr [rbp-0x6F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x67], al
+ movzx rax, byte ptr [rbp-0x6E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x66], al
+ movzx rax, byte ptr [rbp-0x6D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x65], al
+ movzx rax, byte ptr [rbp-0x6C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x64], al
+ movzx rax, byte ptr [rbp-0x6B]
+ xor edx, edx
+ ;; size=208 bbWeight=1 PerfScore 396.75
G_M7625_IG04:
- mov r15, qword ptr [rbp-0xB8]
- mov rdi, qword ptr [rbp-0xA8]
- mov qword ptr [rbp-0xD0], rdi
- xor r13d, r13d
- ;; size=24 bbWeight=1 PerfScore 3.25
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x63], al
+ movzx rax, byte ptr [rbp-0x6A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x62], al
+ movzx rax, byte ptr [rbp-0x69]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x61], al
+ mov rax, qword ptr [rbp-0x68]
+ mov qword ptr [rbp-0x80], rsi
+ mov qword ptr [rbp-0x78], rax
+ vinserti128 ymm0, ymm1, xmmword ptr [rbp-0x80], 1
+ vmovups ymm1, ymmword ptr [rbp+0x30]
+ vmovaps ymm2, ymm1
+ vmovaps xmmword ptr [rbp-0x90], xmm2
+ mov rax, qword ptr [rbp-0x90]
+ mov qword ptr [rbp-0xA0], rax
+ movzx rax, byte ptr [rbp-0xA0]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x98], al
+ movzx rax, byte ptr [rbp-0x9F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x97], al
+ movzx rax, byte ptr [rbp-0x9E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x96], al
+ movzx rax, byte ptr [rbp-0x9D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x95], al
+ movzx rax, byte ptr [rbp-0x9C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x94], al
+ movzx rax, byte ptr [rbp-0x9B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x93], al
+ movzx rax, byte ptr [rbp-0x9A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x92], al
+ movzx rax, byte ptr [rbp-0x99]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x91], al
+ mov rsi, qword ptr [rbp-0x98]
+ mov rax, qword ptr [rbp-0x88]
+ mov qword ptr [rbp-0xB0], rax
+ movzx rax, byte ptr [rbp-0xB0]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA8], al
+ movzx rax, byte ptr [rbp-0xAF]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA7], al
+ movzx rax, byte ptr [rbp-0xAE]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA6], al
+ movzx rax, byte ptr [rbp-0xAD]
+ xor edx, edx
+ div edx:eax, ecx
+ ;; size=296 bbWeight=1 PerfScore 423.75
G_M7625_IG05:
- lea rdi, [rbp-0xD0]
- movsxd r12, r13d
- movzx rdi, byte ptr [rdi+r12]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0xC8]
- mov byte ptr [rdi+r12], al
- inc r13d
- cmp r13d, 8
- jl SHORT G_M7625_IG05
- ;; size=50 bbWeight=4 PerfScore 37.00
+ mov byte ptr [rbp-0xA5], al
+ movzx rax, byte ptr [rbp-0xAC]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA4], al
+ movzx rax, byte ptr [rbp-0xAB]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA3], al
+ movzx rax, byte ptr [rbp-0xAA]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA2], al
+ movzx rax, byte ptr [rbp-0xA9]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xA1], al
+ mov rax, qword ptr [rbp-0xA8]
+ mov qword ptr [rbp-0xC0], rsi
+ mov qword ptr [rbp-0xB8], rax
+ vmovaps xmm2, xmmword ptr [rbp-0xC0]
+ vextractf128 xmm1, ymm1, 1
+ vmovaps xmmword ptr [rbp-0xD0], xmm1
+ mov rax, qword ptr [rbp-0xD0]
+ mov qword ptr [rbp-0xE0], rax
+ movzx rax, byte ptr [rbp-0xE0]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD8], al
+ movzx rax, byte ptr [rbp-0xDF]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD7], al
+ movzx rax, byte ptr [rbp-0xDE]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD6], al
+ movzx rax, byte ptr [rbp-0xDD]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD5], al
+ movzx rax, byte ptr [rbp-0xDC]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD4], al
+ movzx rax, byte ptr [rbp-0xDB]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD3], al
+ movzx rax, byte ptr [rbp-0xDA]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD2], al
+ movzx rax, byte ptr [rbp-0xD9]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xD1], al
+ mov rsi, qword ptr [rbp-0xD8]
+ mov rax, qword ptr [rbp-0xC8]
+ mov qword ptr [rbp-0xF0], rax
+ movzx rax, byte ptr [rbp-0xF0]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE8], al
+ movzx rax, byte ptr [rbp-0xEF]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE7], al
+ ;; size=322 bbWeight=1 PerfScore 396.50
G_M7625_IG06:
- mov rdi, qword ptr [rbp-0xC8]
- mov qword ptr [rbp-0xE0], r15
- mov qword ptr [rbp-0xD8], rdi
- vmovaps xmm1, xmmword ptr [rbp-0xE0]
- vmovaps xmmword ptr [rbp-0xA0], xmm1
- vmovups ymm0, ymmword ptr [rbp-0x90]
- vextractf128 xmm0, ymm0, 1
- vmovaps xmmword ptr [rbp-0xF0], xmm0
- mov rdi, qword ptr [rbp-0xF0]
- mov qword ptr [rbp-0x100], rdi
- xor r15d, r15d
- ;; size=76 bbWeight=1 PerfScore 16.25
+ movzx rax, byte ptr [rbp-0xEE]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE6], al
+ movzx rax, byte ptr [rbp-0xED]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE5], al
+ movzx rax, byte ptr [rbp-0xEC]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE4], al
+ movzx rax, byte ptr [rbp-0xEB]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE3], al
+ movzx rax, byte ptr [rbp-0xEA]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE2], al
+ movzx rax, byte ptr [rbp-0xE9]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0xE1], al
+ mov rax, qword ptr [rbp-0xE8]
+ mov qword ptr [rbp-0x100], rsi
+ mov qword ptr [rbp-0xF8], rax
+ vinserti128 ymm1, ymm2, xmmword ptr [rbp-0x100], 1
+ vmovups ymmword ptr [rdi], ymm0
+ vmovups ymmword ptr [rdi+0x20], ymm1
+ mov rax, rdi
+ ;; size=145 bbWeight=1 PerfScore 174.75
G_M7625_IG07:
- lea rdi, [rbp-0x100]
- movsxd r13, r15d
- movzx rdi, byte ptr [rdi+r13]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0xF8]
- mov byte ptr [rdi+r13], al
- inc r15d
- cmp r15d, 8
- jl SHORT G_M7625_IG07
- ;; size=50 bbWeight=4 PerfScore 37.00
-G_M7625_IG08:
- mov r15, qword ptr [rbp-0xF8]
- mov rdi, qword ptr [rbp-0xE8]
- mov qword ptr [rbp-0x110], rdi
- xor r13d, r13d
- ;; size=24 bbWeight=1 PerfScore 3.25
-G_M7625_IG09:
- lea rdi, [rbp-0x110]
- movsxd r12, r13d
- movzx rdi, byte ptr [rdi+r12]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rsi, [rbp-0x108]
- mov byte ptr [rsi+r12], al
- inc r13d
- cmp r13d, 8
- jl SHORT G_M7625_IG09
- ;; size=50 bbWeight=4 PerfScore 37.00
-G_M7625_IG10:
- mov rsi, qword ptr [rbp-0x108]
- mov qword ptr [rbp-0x120], r15
- mov qword ptr [rbp-0x118], rsi
- vmovaps xmm1, xmmword ptr [rbp-0xA0]
- vinserti128 ymm0, ymm1, xmmword ptr [rbp-0x120], 1
- vmovups ymmword ptr [rbp-0x50], ymm0
- vmovups ymm1, ymmword ptr [rbp+0x30]
- vmovups ymmword ptr [rsp], ymm1
- mov esi, r14d
- lea rdi, [rbp-0x70]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector256`1[ubyte]:op_Division(System.Runtime.Intrinsics.Vector256`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector256`1[ubyte]
- call [rax]System.Runtime.Intrinsics.Vector256`1[ubyte]:op_Division(System.Runtime.Intrinsics.Vector256`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector256`1[ubyte]
- vmovups ymm0, ymmword ptr [rbp-0x50]
- vmovups ymmword ptr [rsp], ymm0
- vmovups ymm0, ymmword ptr [rbp-0x70]
- vmovups ymmword ptr [rsp+0x20], ymm0
- mov rdi, rbx
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector512:Create[ubyte](System.Runtime.Intrinsics.Vector256`1[ubyte],System.Runtime.Intrinsics.Vector256`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte]
- call [rax]System.Runtime.Intrinsics.Vector512:Create[ubyte](System.Runtime.Intrinsics.Vector256`1[ubyte],System.Runtime.Intrinsics.Vector256`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte]
- mov rax, rbx
- ;; size=112 bbWeight=1 PerfScore 33.75
-G_M7625_IG11:
vzeroupper
- add rsp, 312
- pop rbx
- pop r12
- pop r13
- pop r14
- pop r15
+ add rsp, 256
pop rbp
ret
- ;; size=21 bbWeight=1 PerfScore 5.25
+ ;; size=12 bbWeight=1 PerfScore 2.75
-; Total bytes of code 531, prolog size 25, PerfScore 225.50, instruction count 109, allocated bytes for code 531 (MethodHash=ae93e236) for method System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector512`1[ubyte] (FullOpts)
+; Total bytes of code 1202, prolog size 16, PerfScore 1815.50, instruction count 313, allocated bytes for code 1202 (MethodHash=ae93e236) for method System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector512`1[ubyte] (FullOpts)373 (37.75 % of base) - System.Runtime.Intrinsics.Vector512`1[short]:System.Runtime.Intrinsics.ISimdVector,T>.Divide(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short]
; Assembly listing for method System.Runtime.Intrinsics.Vector512`1[short]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 22 single block inlinees; 8 inlinees without PGO data
+; 0 inlinees with PGO data; 42 single block inlinees; 27 inlinees without PGO data
; Final local variable assignments
;
-; V00 RetBuf [V00,T00] ( 4, 4 ) byref -> rbx single-def
+; V00 RetBuf [V00,T08] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
-; V03 OutArgs [V03 ] ( 1, 1 ) struct (64) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
-; V04 tmp1 [V04,T15] ( 2, 4 ) simd32 -> [rbp-0x30] do-not-enreg[HS] hidden-struct-arg "impAppendStmt"
-; V05 tmp2 [V05,T16] ( 2, 4 ) simd32 -> [rbp-0x50] do-not-enreg[HS] hidden-struct-arg "spilled call-like call argument"
-; V06 tmp3 [V06,T09] ( 3, 6 ) simd32 -> [rbp-0x70] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V07 tmp4 [V07,T10] ( 3, 6 ) simd32 -> [rbp-0x90] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V08 tmp5 [V08,T17] ( 2, 4 ) simd16 -> [rbp-0xA0] spill-single-def "impAppendStmt"
+;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
+; V04 tmp1 [V04,T37] ( 2, 4 ) simd32 -> mm0 "impAppendStmt"
+; V05 tmp2 [V05,T38] ( 2, 4 ) simd32 -> mm1 "spilled call-like call argument"
+; V06 tmp3 [V06,T25] ( 3, 6 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V07 tmp4 [V07,T26] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V08 tmp5 [V08,T39] ( 2, 4 ) simd16 -> mm2 "impAppendStmt"
;* V09 tmp6 [V09 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
-; V10 tmp7 [V10,T11] ( 3, 6 ) simd16 -> [rbp-0xB0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
-; V11 tmp8 [V11,T12] ( 3, 6 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V10 tmp7 [V10,T27] ( 3, 6 ) simd16 -> [rbp-0x10] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V11 tmp8 [V11,T28] ( 3, 6 ) simd16 -> [rbp-0x20] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
;* V12 tmp9 [V12 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[short]>
;* V13 tmp10 [V13 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[short]>
-; V14 tmp11 [V14 ] ( 5, 5 ) struct ( 8) [rbp-0xC8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V15 tmp12 [V15,T05] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V16 tmp13 [V16 ] ( 5, 10 ) struct ( 8) [rbp-0xD0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
-; V17 tmp14 [V17 ] ( 5, 10 ) struct ( 8) [rbp-0xD8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V14 tmp11 [V14 ] ( 5, 5 ) struct ( 8) [rbp-0x28] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V15 tmp12 [V15,T17] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V16 tmp13 [V16 ] ( 5, 10 ) struct ( 8) [rbp-0x30] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V17 tmp14 [V17 ] ( 5, 10 ) struct ( 8) [rbp-0x38] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
;* V18 tmp15 [V18 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
;* V19 tmp16 [V19 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
-; V20 tmp17 [V20 ] ( 5, 5 ) struct ( 8) [rbp-0xE0] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V21 tmp18 [V21,T06] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V22 tmp19 [V22 ] ( 5, 10 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
-; V23 tmp20 [V23 ] ( 5, 10 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V24 tmp21 [V24 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
-;* V25 tmp22 [V25 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
-; V26 tmp23 [V26,T18] ( 3, 3 ) simd16 -> [rbp-0x100] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
-; V27 tmp24 [V27,T13] ( 3, 6 ) simd16 -> [rbp-0x110] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
-; V28 tmp25 [V28,T14] ( 3, 6 ) simd16 -> [rbp-0x120] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
-;* V29 tmp26 [V29 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V30 tmp27 [V30 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[short]>
-; V31 tmp28 [V31 ] ( 5, 5 ) struct ( 8) [rbp-0x128] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V32 tmp29 [V32,T07] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V33 tmp30 [V33 ] ( 5, 10 ) struct ( 8) [rbp-0x130] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
-; V34 tmp31 [V34 ] ( 5, 10 ) struct ( 8) [rbp-0x138] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V35 tmp32 [V35 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
-;* V36 tmp33 [V36 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
-; V37 tmp34 [V37 ] ( 5, 5 ) struct ( 8) [rbp-0x140] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
-;* V38 tmp35 [V38,T08] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V39 tmp36 [V39 ] ( 5, 10 ) struct ( 8) [rbp-0x148] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
-; V40 tmp37 [V40 ] ( 5, 10 ) struct ( 8) [rbp-0x150] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V20 tmp17 [V20,T00] ( 8, 8 ) short -> rcx "Inline return value spill temp"
+;* V21 tmp18 [V21 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V22 tmp19 [V22 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V23 tmp20 [V23 ] ( 5, 5 ) struct ( 8) [rbp-0x40] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V24 tmp21 [V24,T18] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V25 tmp22 [V25 ] ( 5, 10 ) struct ( 8) [rbp-0x48] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V26 tmp23 [V26 ] ( 5, 10 ) struct ( 8) [rbp-0x50] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V27 tmp24 [V27 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V28 tmp25 [V28 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
+; V29 tmp26 [V29,T01] ( 8, 8 ) short -> rsi "Inline return value spill temp"
+;* V30 tmp27 [V30 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V31 tmp28 [V31 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V32 tmp29 [V32,T41] ( 3, 3 ) simd16 -> [rbp-0x60] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V33 tmp30 [V33,T29] ( 3, 6 ) simd16 -> [rbp-0x70] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V34 tmp31 [V34,T30] ( 3, 6 ) simd16 -> [rbp-0x80] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+;* V35 tmp32 [V35 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V36 tmp33 [V36 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V37 tmp34 [V37 ] ( 5, 5 ) struct ( 8) [rbp-0x88] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V38 tmp35 [V38,T19] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V39 tmp36 [V39 ] ( 5, 10 ) struct ( 8) [rbp-0x90] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V40 tmp37 [V40 ] ( 5, 10 ) struct ( 8) [rbp-0x98] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
;* V41 tmp38 [V41 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
;* V42 tmp39 [V42 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
-; V43 tmp40 [V43,T19] ( 3, 3 ) simd16 -> [rbp-0x160] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
-;* V44 tmp41 [V44 ] ( 0, 0 ) simd32 -> zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V45 tmp42 [V45 ] ( 0, 0 ) simd32 -> zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V46 tmp43 [V46,T20] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V47 tmp44 [V47,T21] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V48 tmp45 [V48,T22] ( 1, 1 ) simd32 -> [rbp+0x50] single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V49 tmp46 [V49,T23] ( 1, 1 ) simd32 -> [rbp+0x70] single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-; V50 tmp47 [V50,T01] ( 2, 2 ) long -> r15 "field V12._00 (fldOffset=0x0)" P-INDEP
-; V51 tmp48 [V51,T02] ( 2, 2 ) long -> rdi "field V13._00 (fldOffset=0x0)" P-INDEP
-; V52 tmp49 [V52 ] ( 5, 5 ) long -> [rbp-0xC8] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
-; V53 tmp50 [V53 ] ( 5, 9 ) long -> [rbp-0xD0] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
-; V54 tmp51 [V54 ] ( 5, 9 ) long -> [rbp-0xD8] do-not-enreg[X] addr-exposed "field V17._00 (fldOffset=0x0)" P-DEP
-; V55 tmp52 [V55 ] ( 5, 5 ) long -> [rbp-0xE0] do-not-enreg[X] addr-exposed "field V20._00 (fldOffset=0x0)" P-DEP
-; V56 tmp53 [V56 ] ( 5, 9 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V22._00 (fldOffset=0x0)" P-DEP
-; V57 tmp54 [V57 ] ( 5, 9 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V23._00 (fldOffset=0x0)" P-DEP
-; V58 tmp55 [V58,T03] ( 2, 2 ) long -> r15 "field V29._00 (fldOffset=0x0)" P-INDEP
-; V59 tmp56 [V59,T04] ( 2, 2 ) long -> rdi "field V30._00 (fldOffset=0x0)" P-INDEP
-; V60 tmp57 [V60 ] ( 5, 5 ) long -> [rbp-0x128] do-not-enreg[X] addr-exposed "field V31._00 (fldOffset=0x0)" P-DEP
-; V61 tmp58 [V61 ] ( 5, 9 ) long -> [rbp-0x130] do-not-enreg[X] addr-exposed "field V33._00 (fldOffset=0x0)" P-DEP
-; V62 tmp59 [V62 ] ( 5, 9 ) long -> [rbp-0x138] do-not-enreg[X] addr-exposed "field V34._00 (fldOffset=0x0)" P-DEP
-; V63 tmp60 [V63 ] ( 5, 5 ) long -> [rbp-0x140] do-not-enreg[X] addr-exposed "field V37._00 (fldOffset=0x0)" P-DEP
-; V64 tmp61 [V64 ] ( 5, 9 ) long -> [rbp-0x148] do-not-enreg[X] addr-exposed "field V39._00 (fldOffset=0x0)" P-DEP
-; V65 tmp62 [V65 ] ( 5, 9 ) long -> [rbp-0x150] do-not-enreg[X] addr-exposed "field V40._00 (fldOffset=0x0)" P-DEP
+; V43 tmp40 [V43,T02] ( 8, 8 ) short -> rcx "Inline return value spill temp"
+;* V44 tmp41 [V44 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V45 tmp42 [V45 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V46 tmp43 [V46 ] ( 5, 5 ) struct ( 8) [rbp-0xA0] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V47 tmp44 [V47,T20] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V48 tmp45 [V48 ] ( 5, 10 ) struct ( 8) [rbp-0xA8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V49 tmp46 [V49 ] ( 5, 10 ) struct ( 8) [rbp-0xB0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V50 tmp47 [V50 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V51 tmp48 [V51 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
+; V52 tmp49 [V52,T03] ( 8, 8 ) short -> rsi "Inline return value spill temp"
+;* V53 tmp50 [V53 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V54 tmp51 [V54 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V55 tmp52 [V55,T42] ( 3, 3 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
+;* V56 tmp53 [V56 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V57 tmp54 [V57,T31] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V58 tmp55 [V58,T32] ( 3, 6 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V59 tmp56 [V59,T40] ( 2, 4 ) simd16 -> mm3 "impAppendStmt"
+;* V60 tmp57 [V60 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
+; V61 tmp58 [V61,T33] ( 3, 6 ) simd16 -> [rbp-0xD0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V62 tmp59 [V62,T34] ( 3, 6 ) simd16 -> [rbp-0xE0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+;* V63 tmp60 [V63 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V64 tmp61 [V64 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V65 tmp62 [V65 ] ( 5, 5 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V66 tmp63 [V66,T21] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V67 tmp64 [V67 ] ( 5, 10 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V68 tmp65 [V68 ] ( 5, 10 ) struct ( 8) [rbp-0xF8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V69 tmp66 [V69 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V70 tmp67 [V70 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
+; V71 tmp68 [V71,T04] ( 8, 8 ) short -> rcx "Inline return value spill temp"
+;* V72 tmp69 [V72 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V73 tmp70 [V73 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V74 tmp71 [V74 ] ( 5, 5 ) struct ( 8) [rbp-0x100] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V75 tmp72 [V75,T22] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V76 tmp73 [V76 ] ( 5, 10 ) struct ( 8) [rbp-0x108] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V77 tmp74 [V77 ] ( 5, 10 ) struct ( 8) [rbp-0x110] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V78 tmp75 [V78 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V79 tmp76 [V79 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
+; V80 tmp77 [V80,T05] ( 8, 8 ) short -> rsi "Inline return value spill temp"
+;* V81 tmp78 [V81 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V82 tmp79 [V82 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V83 tmp80 [V83,T43] ( 3, 3 ) simd16 -> [rbp-0x120] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V84 tmp81 [V84,T35] ( 3, 6 ) simd16 -> [rbp-0x130] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+; V85 tmp82 [V85,T36] ( 3, 6 ) simd16 -> [rbp-0x140] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[short]>
+;* V86 tmp83 [V86 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V87 tmp84 [V87 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V88 tmp85 [V88 ] ( 5, 5 ) struct ( 8) [rbp-0x148] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V89 tmp86 [V89,T23] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V90 tmp87 [V90 ] ( 5, 10 ) struct ( 8) [rbp-0x150] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V91 tmp88 [V91 ] ( 5, 10 ) struct ( 8) [rbp-0x158] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V92 tmp89 [V92 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V93 tmp90 [V93 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
+; V94 tmp91 [V94,T06] ( 8, 8 ) short -> rcx "Inline return value spill temp"
+;* V95 tmp92 [V95 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V96 tmp93 [V96 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V97 tmp94 [V97 ] ( 5, 5 ) struct ( 8) [rbp-0x160] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V98 tmp95 [V98,T24] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V99 tmp96 [V99 ] ( 5, 10 ) struct ( 8) [rbp-0x168] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+; V100 tmp97 [V100 ] ( 5, 10 ) struct ( 8) [rbp-0x170] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[short]>
+;* V101 tmp98 [V101 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V102 tmp99 [V102 ] ( 0, 0 ) short -> zero-ref "Inline stloc first use temp"
+; V103 tmp100 [V103,T07] ( 8, 8 ) short -> rsi "Inline return value spill temp"
+;* V104 tmp101 [V104 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+;* V105 tmp102 [V105 ] ( 0, 0 ) short -> zero-ref "Inlining Arg"
+; V106 tmp103 [V106,T44] ( 3, 3 ) simd16 -> [rbp-0x180] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
+;* V107 tmp104 [V107 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V108 tmp105 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V109 tmp106 [V109,T47] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V110 tmp107 [V110,T48] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V111 tmp108 [V111,T49] ( 1, 1 ) simd32 -> [rbp+0x50] single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V112 tmp109 [V112,T50] ( 1, 1 ) simd32 -> [rbp+0x70] single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+; V113 tmp110 [V113,T09] ( 2, 2 ) long -> rcx "field V12._00 (fldOffset=0x0)" P-INDEP
+; V114 tmp111 [V114,T10] ( 2, 2 ) long -> rax "field V13._00 (fldOffset=0x0)" P-INDEP
+; V115 tmp112 [V115 ] ( 5, 5 ) long -> [rbp-0x28] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
+; V116 tmp113 [V116 ] ( 5, 9 ) long -> [rbp-0x30] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
+; V117 tmp114 [V117 ] ( 5, 9 ) long -> [rbp-0x38] do-not-enreg[X] addr-exposed "field V17._00 (fldOffset=0x0)" P-DEP
+; V118 tmp115 [V118 ] ( 5, 5 ) long -> [rbp-0x40] do-not-enreg[X] addr-exposed "field V23._00 (fldOffset=0x0)" P-DEP
+; V119 tmp116 [V119 ] ( 5, 9 ) long -> [rbp-0x48] do-not-enreg[X] addr-exposed "field V25._00 (fldOffset=0x0)" P-DEP
+; V120 tmp117 [V120 ] ( 5, 9 ) long -> [rbp-0x50] do-not-enreg[X] addr-exposed "field V26._00 (fldOffset=0x0)" P-DEP
+; V121 tmp118 [V121,T11] ( 2, 2 ) long -> rcx "field V35._00 (fldOffset=0x0)" P-INDEP
+; V122 tmp119 [V122,T12] ( 2, 2 ) long -> rax "field V36._00 (fldOffset=0x0)" P-INDEP
+; V123 tmp120 [V123 ] ( 5, 5 ) long -> [rbp-0x88] do-not-enreg[X] addr-exposed "field V37._00 (fldOffset=0x0)" P-DEP
+; V124 tmp121 [V124 ] ( 5, 9 ) long -> [rbp-0x90] do-not-enreg[X] addr-exposed "field V39._00 (fldOffset=0x0)" P-DEP
+; V125 tmp122 [V125 ] ( 5, 9 ) long -> [rbp-0x98] do-not-enreg[X] addr-exposed "field V40._00 (fldOffset=0x0)" P-DEP
+; V126 tmp123 [V126 ] ( 5, 5 ) long -> [rbp-0xA0] do-not-enreg[X] addr-exposed "field V46._00 (fldOffset=0x0)" P-DEP
+; V127 tmp124 [V127 ] ( 5, 9 ) long -> [rbp-0xA8] do-not-enreg[X] addr-exposed "field V48._00 (fldOffset=0x0)" P-DEP
+; V128 tmp125 [V128 ] ( 5, 9 ) long -> [rbp-0xB0] do-not-enreg[X] addr-exposed "field V49._00 (fldOffset=0x0)" P-DEP
+; V129 tmp126 [V129,T13] ( 2, 2 ) long -> rcx "field V63._00 (fldOffset=0x0)" P-INDEP
+; V130 tmp127 [V130,T14] ( 2, 2 ) long -> rax "field V64._00 (fldOffset=0x0)" P-INDEP
+; V131 tmp128 [V131 ] ( 5, 5 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V65._00 (fldOffset=0x0)" P-DEP
+; V132 tmp129 [V132 ] ( 5, 9 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V67._00 (fldOffset=0x0)" P-DEP
+; V133 tmp130 [V133 ] ( 5, 9 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "field V68._00 (fldOffset=0x0)" P-DEP
+; V134 tmp131 [V134 ] ( 5, 5 ) long -> [rbp-0x100] do-not-enreg[X] addr-exposed "field V74._00 (fldOffset=0x0)" P-DEP
+; V135 tmp132 [V135 ] ( 5, 9 ) long -> [rbp-0x108] do-not-enreg[X] addr-exposed "field V76._00 (fldOffset=0x0)" P-DEP
+; V136 tmp133 [V136 ] ( 5, 9 ) long -> [rbp-0x110] do-not-enreg[X] addr-exposed "field V77._00 (fldOffset=0x0)" P-DEP
+; V137 tmp134 [V137,T15] ( 2, 2 ) long -> rcx "field V86._00 (fldOffset=0x0)" P-INDEP
+; V138 tmp135 [V138,T16] ( 2, 2 ) long -> rax "field V87._00 (fldOffset=0x0)" P-INDEP
+; V139 tmp136 [V139 ] ( 5, 5 ) long -> [rbp-0x148] do-not-enreg[X] addr-exposed "field V88._00 (fldOffset=0x0)" P-DEP
+; V140 tmp137 [V140 ] ( 5, 9 ) long -> [rbp-0x150] do-not-enreg[X] addr-exposed "field V90._00 (fldOffset=0x0)" P-DEP
+; V141 tmp138 [V141 ] ( 5, 9 ) long -> [rbp-0x158] do-not-enreg[X] addr-exposed "field V91._00 (fldOffset=0x0)" P-DEP
+; V142 tmp139 [V142 ] ( 5, 5 ) long -> [rbp-0x160] do-not-enreg[X] addr-exposed "field V97._00 (fldOffset=0x0)" P-DEP
+; V143 tmp140 [V143 ] ( 5, 9 ) long -> [rbp-0x168] do-not-enreg[X] addr-exposed "field V99._00 (fldOffset=0x0)" P-DEP
+; V144 tmp141 [V144 ] ( 5, 9 ) long -> [rbp-0x170] do-not-enreg[X] addr-exposed "field V100._00 (fldOffset=0x0)" P-DEP
+; V145 tmp142 [V145,T45] ( 2, 2 ) simd32 -> mm0 "field V108._lower (fldOffset=0x0)" P-INDEP
+; V146 tmp143 [V146,T46] ( 2, 2 ) simd32 -> mm1 "field V108._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 400
+; Lcl frame size = 384
G_M48810_IG01:
push rbp
- push r15
- push rbx
- sub rsp, 400
- lea rbp, [rsp+0x1A0]
- mov rbx, rdi
- ;; size=22 bbWeight=1 PerfScore 4.00
+ sub rsp, 384
+ lea rbp, [rsp+0x180]
+ ;; size=16 bbWeight=1 PerfScore 1.75
G_M48810_IG02:
vmovups ymm0, ymmword ptr [rbp+0x10]
- vmovups ymmword ptr [rbp-0x70], ymm0
vmovups ymm1, ymmword ptr [rbp+0x50]
- vmovups ymmword ptr [rbp-0x90], ymm1
vmovaps ymm2, ymm0
- vmovaps xmmword ptr [rbp-0xB0], xmm2
+ vmovaps xmmword ptr [rbp-0x10], xmm2
vmovaps ymm2, ymm1
- vmovaps xmmword ptr [rbp-0xC0], xmm2
- mov rdi, qword ptr [rbp-0xB0]
- mov qword ptr [rbp-0xD0], rdi
- mov rdi, qword ptr [rbp-0xC0]
- mov qword ptr [rbp-0xD8], rdi
- movsx rdi, word ptr [rbp-0xD0]
- movsx rsi, word ptr [rbp-0xD8]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xC8], ax
- movsx rdi, word ptr [rbp-0xCE]
- movsx rsi, word ptr [rbp-0xD6]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xC6], ax
- movsx rdi, word ptr [rbp-0xCC]
- movsx rsi, word ptr [rbp-0xD4]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xC4], ax
- movsx rdi, word ptr [rbp-0xCA]
- movsx rsi, word ptr [rbp-0xD2]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xC2], ax
- mov r15, qword ptr [rbp-0xC8]
- mov rdi, qword ptr [rbp-0xA8]
- mov qword ptr [rbp-0xE8], rdi
- mov rdi, qword ptr [rbp-0xB8]
- mov qword ptr [rbp-0xF0], rdi
- movsx rdi, word ptr [rbp-0xE8]
- movsx rsi, word ptr [rbp-0xF0]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xE0], ax
- movsx rdi, word ptr [rbp-0xE6]
- movsx rsi, word ptr [rbp-0xEE]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xDE], ax
- ;; size=320 bbWeight=1 PerfScore 83.00
+ vmovaps xmmword ptr [rbp-0x20], xmm2
+ mov rax, qword ptr [rbp-0x10]
+ mov qword ptr [rbp-0x30], rax
+ mov rax, qword ptr [rbp-0x20]
+ mov qword ptr [rbp-0x38], rax
+ movsx rax, word ptr [rbp-0x30]
+ movsx rcx, word ptr [rbp-0x38]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x28], cx
+ movsx rax, word ptr [rbp-0x2E]
+ movsx rcx, word ptr [rbp-0x36]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x26], cx
+ movsx rax, word ptr [rbp-0x2C]
+ movsx rcx, word ptr [rbp-0x34]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x24], cx
+ movsx rax, word ptr [rbp-0x2A]
+ movsx rcx, word ptr [rbp-0x32]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x22], cx
+ mov rcx, qword ptr [rbp-0x28]
+ mov rax, qword ptr [rbp-0x08]
+ mov qword ptr [rbp-0x48], rax
+ mov rax, qword ptr [rbp-0x18]
+ mov qword ptr [rbp-0x50], rax
+ movsx rax, word ptr [rbp-0x48]
+ movsx rsi, word ptr [rbp-0x50]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x40], si
+ movsx rax, word ptr [rbp-0x46]
+ movsx rsi, word ptr [rbp-0x4E]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x3E], si
+ movsx rax, word ptr [rbp-0x44]
+ movsx rsi, word ptr [rbp-0x4C]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x3C], si
+ movsx rax, word ptr [rbp-0x42]
+ movsx rsi, word ptr [rbp-0x4A]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x3A], si
+ mov rax, qword ptr [rbp-0x40]
+ mov qword ptr [rbp-0x60], rcx
+ ;; size=240 bbWeight=1 PerfScore 283.50
G_M48810_IG03:
- movsx rdi, word ptr [rbp-0xE4]
- movsx rsi, word ptr [rbp-0xEC]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xDC], ax
- movsx rdi, word ptr [rbp-0xE2]
- movsx rsi, word ptr [rbp-0xEA]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0xDA], ax
- mov rdi, qword ptr [rbp-0xE0]
- mov qword ptr [rbp-0x100], r15
- mov qword ptr [rbp-0xF8], rdi
- vmovaps xmm0, xmmword ptr [rbp-0x100]
- vmovaps xmmword ptr [rbp-0xA0], xmm0
- vmovups ymm1, ymmword ptr [rbp-0x70]
- vextractf128 xmm1, ymm1, 1
- vmovaps xmmword ptr [rbp-0x110], xmm1
- vmovups ymm1, ymmword ptr [rbp-0x90]
- vextractf128 xmm1, ymm1, 1
- vmovaps xmmword ptr [rbp-0x120], xmm1
- mov rdi, qword ptr [rbp-0x110]
- mov qword ptr [rbp-0x130], rdi
- mov rdi, qword ptr [rbp-0x120]
- mov qword ptr [rbp-0x138], rdi
- movsx rdi, word ptr [rbp-0x130]
- movsx rsi, word ptr [rbp-0x138]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x128], ax
- movsx rdi, word ptr [rbp-0x12E]
- movsx rsi, word ptr [rbp-0x136]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x126], ax
- movsx rdi, word ptr [rbp-0x12C]
- movsx rsi, word ptr [rbp-0x134]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x124], ax
- movsx rdi, word ptr [rbp-0x12A]
- movsx rsi, word ptr [rbp-0x132]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x122], ax
- mov r15, qword ptr [rbp-0x128]
- mov rdi, qword ptr [rbp-0x108]
- ;; size=330 bbWeight=1 PerfScore 88.50
+ mov qword ptr [rbp-0x58], rax
+ vmovaps xmm2, xmmword ptr [rbp-0x60]
+ vextractf128 xmm0, ymm0, 1
+ vmovaps xmmword ptr [rbp-0x70], xmm0
+ vextractf128 xmm0, ymm1, 1
+ vmovaps xmmword ptr [rbp-0x80], xmm0
+ mov rax, qword ptr [rbp-0x70]
+ mov qword ptr [rbp-0x90], rax
+ mov rax, qword ptr [rbp-0x80]
+ mov qword ptr [rbp-0x98], rax
+ movsx rax, word ptr [rbp-0x90]
+ movsx rcx, word ptr [rbp-0x98]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x88], cx
+ movsx rax, word ptr [rbp-0x8E]
+ movsx rcx, word ptr [rbp-0x96]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x86], cx
+ movsx rax, word ptr [rbp-0x8C]
+ movsx rcx, word ptr [rbp-0x94]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x84], cx
+ movsx rax, word ptr [rbp-0x8A]
+ movsx rcx, word ptr [rbp-0x92]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x82], cx
+ mov rcx, qword ptr [rbp-0x88]
+ mov rax, qword ptr [rbp-0x68]
+ mov qword ptr [rbp-0xA8], rax
+ mov rax, qword ptr [rbp-0x78]
+ mov qword ptr [rbp-0xB0], rax
+ movsx rax, word ptr [rbp-0xA8]
+ movsx rsi, word ptr [rbp-0xB0]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0xA0], si
+ movsx rax, word ptr [rbp-0xA6]
+ movsx rsi, word ptr [rbp-0xAE]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x9E], si
+ movsx rax, word ptr [rbp-0xA4]
+ movsx rsi, word ptr [rbp-0xAC]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x9C], si
+ movsx rax, word ptr [rbp-0xA2]
+ movsx rsi, word ptr [rbp-0xAA]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x9A], si
+ mov rax, qword ptr [rbp-0xA0]
+ mov qword ptr [rbp-0xC0], rcx
+ ;; size=336 bbWeight=1 PerfScore 283.00
G_M48810_IG04:
- mov qword ptr [rbp-0x148], rdi
- mov rdi, qword ptr [rbp-0x118]
- mov qword ptr [rbp-0x150], rdi
- movsx rdi, word ptr [rbp-0x148]
- movsx rsi, word ptr [rbp-0x150]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x140], ax
- movsx rdi, word ptr [rbp-0x146]
- movsx rsi, word ptr [rbp-0x14E]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x13E], ax
- movsx rdi, word ptr [rbp-0x144]
- movsx rsi, word ptr [rbp-0x14C]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x13C], ax
- movsx rdi, word ptr [rbp-0x142]
- movsx rsi, word ptr [rbp-0x14A]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- call [rax]System.Runtime.Intrinsics.Scalar`1[short]:Divide(short,short):short
- mov word ptr [rbp-0x13A], ax
- mov rdi, qword ptr [rbp-0x140]
- mov qword ptr [rbp-0x160], r15
- mov qword ptr [rbp-0x158], rdi
- vmovaps xmm0, xmmword ptr [rbp-0xA0]
- vmovups xmmword ptr [rsp], xmm0
- vmovaps xmm0, xmmword ptr [rbp-0x160]
- vmovups xmmword ptr [rsp+0x10], xmm0
- lea rdi, [rbp-0x30]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector256:Create[short](System.Runtime.Intrinsics.Vector128`1[short],System.Runtime.Intrinsics.Vector128`1[short]):System.Runtime.Intrinsics.Vector256`1[short]
- call [rax]System.Runtime.Intrinsics.Vector256:Create[short](System.Runtime.Intrinsics.Vector128`1[short],System.Runtime.Intrinsics.Vector128`1[short]):System.Runtime.Intrinsics.Vector256`1[short]
- vmovups ymm0, ymmword ptr [rbp+0x30]
- vmovups ymmword ptr [rsp], ymm0
- vmovups ymm0, ymmword ptr [rbp+0x70]
- vmovups ymmword ptr [rsp+0x20], ymm0
- lea rdi, [rbp-0x50]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector256`1[short]:op_Division(System.Runtime.Intrinsics.Vector256`1[short],System.Runtime.Intrinsics.Vector256`1[short]):System.Runtime.Intrinsics.Vector256`1[short]
- call [rax]System.Runtime.Intrinsics.Vector256`1[short]:op_Division(System.Runtime.Intrinsics.Vector256`1[short],System.Runtime.Intrinsics.Vector256`1[short]):System.Runtime.Intrinsics.Vector256`1[short]
- vmovups ymm0, ymmword ptr [rbp-0x30]
- vmovups ymmword ptr [rsp], ymm0
- vmovups ymm0, ymmword ptr [rbp-0x50]
- vmovups ymmword ptr [rsp+0x20], ymm0
- mov rdi, rbx
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector512:Create[short](System.Runtime.Intrinsics.Vector256`1[short],System.Runtime.Intrinsics.Vector256`1[short]):System.Runtime.Intrinsics.Vector512`1[short]
- ;; size=296 bbWeight=1 PerfScore 83.00
+ mov qword ptr [rbp-0xB8], rax
+ vinserti128 ymm0, ymm2, xmmword ptr [rbp-0xC0], 1
+ vmovups ymm1, ymmword ptr [rbp+0x30]
+ vmovups ymm2, ymmword ptr [rbp+0x70]
+ vmovaps ymm3, ymm1
+ vmovaps xmmword ptr [rbp-0xD0], xmm3
+ vmovaps ymm3, ymm2
+ vmovaps xmmword ptr [rbp-0xE0], xmm3
+ mov rax, qword ptr [rbp-0xD0]
+ mov qword ptr [rbp-0xF0], rax
+ mov rax, qword ptr [rbp-0xE0]
+ mov qword ptr [rbp-0xF8], rax
+ movsx rax, word ptr [rbp-0xF0]
+ movsx rcx, word ptr [rbp-0xF8]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0xE8], cx
+ movsx rax, word ptr [rbp-0xEE]
+ movsx rcx, word ptr [rbp-0xF6]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0xE6], cx
+ movsx rax, word ptr [rbp-0xEC]
+ movsx rcx, word ptr [rbp-0xF4]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0xE4], cx
+ movsx rax, word ptr [rbp-0xEA]
+ movsx rcx, word ptr [rbp-0xF2]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0xE2], cx
+ mov rcx, qword ptr [rbp-0xE8]
+ mov rax, qword ptr [rbp-0xC8]
+ mov qword ptr [rbp-0x108], rax
+ mov rax, qword ptr [rbp-0xD8]
+ mov qword ptr [rbp-0x110], rax
+ movsx rax, word ptr [rbp-0x108]
+ movsx rsi, word ptr [rbp-0x110]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x100], si
+ movsx rax, word ptr [rbp-0x106]
+ movsx rsi, word ptr [rbp-0x10E]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0xFE], si
+ movsx rax, word ptr [rbp-0x104]
+ movsx rsi, word ptr [rbp-0x10C]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0xFC], si
+ movsx rax, word ptr [rbp-0x102]
+ movsx rsi, word ptr [rbp-0x10A]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0xFA], si
+ ;; size=354 bbWeight=1 PerfScore 286.50
G_M48810_IG05:
- call [rax]System.Runtime.Intrinsics.Vector512:Create[short](System.Runtime.Intrinsics.Vector256`1[short],System.Runtime.Intrinsics.Vector256`1[short]):System.Runtime.Intrinsics.Vector512`1[short]
- mov rax, rbx
- ;; size=5 bbWeight=1 PerfScore 3.25
+ mov rax, qword ptr [rbp-0x100]
+ mov qword ptr [rbp-0x120], rcx
+ mov qword ptr [rbp-0x118], rax
+ vmovaps xmm3, xmmword ptr [rbp-0x120]
+ vextractf128 xmm1, ymm1, 1
+ vmovaps xmmword ptr [rbp-0x130], xmm1
+ vextractf128 xmm1, ymm2, 1
+ vmovaps xmmword ptr [rbp-0x140], xmm1
+ mov rax, qword ptr [rbp-0x130]
+ mov qword ptr [rbp-0x150], rax
+ mov rax, qword ptr [rbp-0x140]
+ mov qword ptr [rbp-0x158], rax
+ movsx rax, word ptr [rbp-0x150]
+ movsx rcx, word ptr [rbp-0x158]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x148], cx
+ movsx rax, word ptr [rbp-0x14E]
+ movsx rcx, word ptr [rbp-0x156]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x146], cx
+ movsx rax, word ptr [rbp-0x14C]
+ movsx rcx, word ptr [rbp-0x154]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x144], cx
+ movsx rax, word ptr [rbp-0x14A]
+ movsx rcx, word ptr [rbp-0x152]
+ cdq
+ idiv edx:eax, ecx
+ movsx rcx, ax
+ mov word ptr [rbp-0x142], cx
+ mov rcx, qword ptr [rbp-0x148]
+ mov rax, qword ptr [rbp-0x128]
+ mov qword ptr [rbp-0x168], rax
+ mov rax, qword ptr [rbp-0x138]
+ mov qword ptr [rbp-0x170], rax
+ movsx rax, word ptr [rbp-0x168]
+ movsx rsi, word ptr [rbp-0x170]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x160], si
+ movsx rax, word ptr [rbp-0x166]
+ movsx rsi, word ptr [rbp-0x16E]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x15E], si
+ movsx rax, word ptr [rbp-0x164]
+ movsx rsi, word ptr [rbp-0x16C]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x15C], si
+ movsx rax, word ptr [rbp-0x162]
+ movsx rsi, word ptr [rbp-0x16A]
+ cdq
+ idiv edx:eax, esi
+ movsx rsi, ax
+ mov word ptr [rbp-0x15A], si
+ ;; size=360 bbWeight=1 PerfScore 283.00
G_M48810_IG06:
+ mov rax, qword ptr [rbp-0x160]
+ mov qword ptr [rbp-0x180], rcx
+ mov qword ptr [rbp-0x178], rax
+ vinserti128 ymm1, ymm3, xmmword ptr [rbp-0x180], 1
+ vmovups ymmword ptr [rdi], ymm0
+ vmovups ymmword ptr [rdi+0x20], ymm1
+ mov rax, rdi
+ ;; size=43 bbWeight=1 PerfScore 11.25
+G_M48810_IG07:
vzeroupper
- add rsp, 400
- pop rbx
- pop r15
+ add rsp, 384
pop rbp
ret
- ;; size=15 bbWeight=1 PerfScore 3.75
+ ;; size=12 bbWeight=1 PerfScore 2.75
-; Total bytes of code 988, prolog size 19, PerfScore 265.50, instruction count 154, allocated bytes for code 988 (MethodHash=e38d4155) for method System.Runtime.Intrinsics.Vector512`1[short]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
+; Total bytes of code 1361, prolog size 16, PerfScore 1151.75, instruction count 274, allocated bytes for code 1361 (MethodHash=e38d4155) for method System.Runtime.Intrinsics.Vector512`1[short]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)183 (26.52 % of base) - System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],System.Runtime.Intrinsics.Vector512`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte]
; Assembly listing for method System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],System.Runtime.Intrinsics.Vector512`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
-; partially interruptible
+; fully interruptible
; No PGO data
-; 0 inlinees with PGO data; 22 single block inlinees; 8 inlinees without PGO data
+; 0 inlinees with PGO data; 42 single block inlinees; 27 inlinees without PGO data
; Final local variable assignments
;
-; V00 RetBuf [V00,T08] ( 4, 4 ) byref -> rbx single-def
+; V00 RetBuf [V00,T16] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[ubyte]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[ubyte]>
-; V03 OutArgs [V03 ] ( 1, 1 ) struct (64) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
-; V04 tmp1 [V04,T19] ( 2, 4 ) simd32 -> [rbp-0x50] do-not-enreg[HS] hidden-struct-arg "impAppendStmt"
-; V05 tmp2 [V05,T20] ( 2, 4 ) simd32 -> [rbp-0x70] do-not-enreg[HS] hidden-struct-arg "spilled call-like call argument"
-; V06 tmp3 [V06,T13] ( 3, 6 ) simd32 -> [rbp-0x90] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V07 tmp4 [V07,T14] ( 3, 6 ) simd32 -> [rbp-0xB0] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V08 tmp5 [V08,T21] ( 2, 4 ) simd16 -> [rbp-0xC0] spill-single-def "impAppendStmt"
+;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
+; V04 tmp1 [V04,T37] ( 2, 4 ) simd32 -> mm0 "impAppendStmt"
+; V05 tmp2 [V05,T38] ( 2, 4 ) simd32 -> mm1 "spilled call-like call argument"
+; V06 tmp3 [V06,T25] ( 3, 6 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V07 tmp4 [V07,T26] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V08 tmp5 [V08,T39] ( 2, 4 ) simd16 -> mm2 "impAppendStmt"
;* V09 tmp6 [V09 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
-; V10 tmp7 [V10,T15] ( 3, 6 ) simd16 -> [rbp-0xD0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-; V11 tmp8 [V11,T16] ( 3, 6 ) simd16 -> [rbp-0xE0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V10 tmp7 [V10,T27] ( 3, 6 ) simd16 -> [rbp-0x10] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V11 tmp8 [V11,T28] ( 3, 6 ) simd16 -> [rbp-0x20] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V12 tmp9 [V12 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V13 tmp10 [V13 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V14 tmp11 [V14 ] ( 2, 5 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V15 tmp12 [V15,T00] ( 5, 17 ) int -> r15 "Inline stloc first use temp"
-; V16 tmp13 [V16 ] ( 2, 10 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V17 tmp14 [V17 ] ( 2, 10 ) struct ( 8) [rbp-0xF8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V14 tmp11 [V14 ] ( 2, 5 ) struct ( 8) [rbp-0x28] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V15 tmp12 [V15,T00] ( 5, 17 ) int -> rcx "Inline stloc first use temp"
+; V16 tmp13 [V16 ] ( 2, 10 ) struct ( 8) [rbp-0x30] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V17 tmp14 [V17 ] ( 2, 10 ) struct ( 8) [rbp-0x38] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V18 tmp15 [V18 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
;* V19 tmp16 [V19 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V20 tmp17 [V20 ] ( 2, 5 ) struct ( 8) [rbp-0x100] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V21 tmp18 [V21,T01] ( 5, 17 ) int -> r14 "Inline stloc first use temp"
-; V22 tmp19 [V22 ] ( 2, 10 ) struct ( 8) [rbp-0x108] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V23 tmp20 [V23 ] ( 2, 10 ) struct ( 8) [rbp-0x110] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V24 tmp21 [V24 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
-;* V25 tmp22 [V25 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V26 tmp23 [V26,T22] ( 3, 3 ) simd16 -> [rbp-0x120] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-; V27 tmp24 [V27,T17] ( 3, 6 ) simd16 -> [rbp-0x130] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-; V28 tmp25 [V28,T18] ( 3, 6 ) simd16 -> [rbp-0x140] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-;* V29 tmp26 [V29 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V30 tmp27 [V30 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V31 tmp28 [V31 ] ( 2, 5 ) struct ( 8) [rbp-0x148] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V32 tmp29 [V32,T02] ( 5, 17 ) int -> r15 "Inline stloc first use temp"
-; V33 tmp30 [V33 ] ( 2, 10 ) struct ( 8) [rbp-0x150] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V34 tmp31 [V34 ] ( 2, 10 ) struct ( 8) [rbp-0x158] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V35 tmp32 [V35 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
-;* V36 tmp33 [V36 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V37 tmp34 [V37 ] ( 2, 5 ) struct ( 8) [rbp-0x160] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V38 tmp35 [V38,T03] ( 5, 17 ) int -> r14 "Inline stloc first use temp"
-; V39 tmp36 [V39 ] ( 2, 10 ) struct ( 8) [rbp-0x168] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V40 tmp37 [V40 ] ( 2, 10 ) struct ( 8) [rbp-0x170] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V20 tmp17 [V20 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V21 tmp18 [V21 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V22 tmp19 [V22 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V23 tmp20 [V23 ] ( 2, 5 ) struct ( 8) [rbp-0x40] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V24 tmp21 [V24,T01] ( 5, 17 ) int -> rsi "Inline stloc first use temp"
+; V25 tmp22 [V25 ] ( 2, 10 ) struct ( 8) [rbp-0x48] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V26 tmp23 [V26 ] ( 2, 10 ) struct ( 8) [rbp-0x50] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V27 tmp24 [V27 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V28 tmp25 [V28 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V29 tmp26 [V29 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V30 tmp27 [V30 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V31 tmp28 [V31 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V32 tmp29 [V32,T41] ( 3, 3 ) simd16 -> [rbp-0x60] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V33 tmp30 [V33,T29] ( 3, 6 ) simd16 -> [rbp-0x70] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V34 tmp31 [V34,T30] ( 3, 6 ) simd16 -> [rbp-0x80] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V35 tmp32 [V35 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V36 tmp33 [V36 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V37 tmp34 [V37 ] ( 2, 5 ) struct ( 8) [rbp-0x88] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V38 tmp35 [V38,T02] ( 5, 17 ) int -> rcx "Inline stloc first use temp"
+; V39 tmp36 [V39 ] ( 2, 10 ) struct ( 8) [rbp-0x90] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V40 tmp37 [V40 ] ( 2, 10 ) struct ( 8) [rbp-0x98] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V41 tmp38 [V41 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
;* V42 tmp39 [V42 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V43 tmp40 [V43,T23] ( 3, 3 ) simd16 -> [rbp-0x180] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-;* V44 tmp41 [V44 ] ( 0, 0 ) simd32 -> zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-;* V45 tmp42 [V45 ] ( 0, 0 ) simd32 -> zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V46 tmp43 [V46,T24] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V47 tmp44 [V47,T25] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V48 tmp45 [V48,T26] ( 1, 1 ) simd32 -> [rbp+0x50] single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V49 tmp46 [V49,T27] ( 1, 1 ) simd32 -> [rbp+0x70] single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-; V50 tmp47 [V50,T09] ( 2, 2 ) long -> r15 "field V12._00 (fldOffset=0x0)" P-INDEP
-; V51 tmp48 [V51,T10] ( 2, 2 ) long -> rdi "field V13._00 (fldOffset=0x0)" P-INDEP
-; V52 tmp49 [V52 ] ( 2, 5 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
-; V53 tmp50 [V53 ] ( 2, 9 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
-; V54 tmp51 [V54 ] ( 2, 9 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "field V17._00 (fldOffset=0x0)" P-DEP
-; V55 tmp52 [V55 ] ( 2, 5 ) long -> [rbp-0x100] do-not-enreg[X] addr-exposed "field V20._00 (fldOffset=0x0)" P-DEP
-; V56 tmp53 [V56 ] ( 2, 9 ) long -> [rbp-0x108] do-not-enreg[X] addr-exposed "field V22._00 (fldOffset=0x0)" P-DEP
-; V57 tmp54 [V57 ] ( 2, 9 ) long -> [rbp-0x110] do-not-enreg[X] addr-exposed "field V23._00 (fldOffset=0x0)" P-DEP
-; V58 tmp55 [V58,T11] ( 2, 2 ) long -> r15 "field V29._00 (fldOffset=0x0)" P-INDEP
-; V59 tmp56 [V59,T12] ( 2, 2 ) long -> rdi "field V30._00 (fldOffset=0x0)" P-INDEP
-; V60 tmp57 [V60 ] ( 2, 5 ) long -> [rbp-0x148] do-not-enreg[X] addr-exposed "field V31._00 (fldOffset=0x0)" P-DEP
-; V61 tmp58 [V61 ] ( 2, 9 ) long -> [rbp-0x150] do-not-enreg[X] addr-exposed "field V33._00 (fldOffset=0x0)" P-DEP
-; V62 tmp59 [V62 ] ( 2, 9 ) long -> [rbp-0x158] do-not-enreg[X] addr-exposed "field V34._00 (fldOffset=0x0)" P-DEP
-; V63 tmp60 [V63 ] ( 2, 5 ) long -> [rbp-0x160] do-not-enreg[X] addr-exposed "field V37._00 (fldOffset=0x0)" P-DEP
-; V64 tmp61 [V64 ] ( 2, 9 ) long -> [rbp-0x168] do-not-enreg[X] addr-exposed "field V39._00 (fldOffset=0x0)" P-DEP
-; V65 tmp62 [V65 ] ( 2, 9 ) long -> [rbp-0x170] do-not-enreg[X] addr-exposed "field V40._00 (fldOffset=0x0)" P-DEP
-; V66 cse0 [V66,T04] ( 4, 16 ) long -> r14 "CSE #01: aggressive"
-; V67 cse1 [V67,T05] ( 4, 16 ) long -> r13 "CSE #02: aggressive"
-; V68 cse2 [V68,T06] ( 4, 16 ) long -> r14 "CSE #03: aggressive"
-; V69 cse3 [V69,T07] ( 4, 16 ) long -> r13 "CSE #04: aggressive"
+;* V43 tmp40 [V43 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V44 tmp41 [V44 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V45 tmp42 [V45 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V46 tmp43 [V46 ] ( 2, 5 ) struct ( 8) [rbp-0xA0] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V47 tmp44 [V47,T03] ( 5, 17 ) int -> rsi "Inline stloc first use temp"
+; V48 tmp45 [V48 ] ( 2, 10 ) struct ( 8) [rbp-0xA8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V49 tmp46 [V49 ] ( 2, 10 ) struct ( 8) [rbp-0xB0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V50 tmp47 [V50 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V51 tmp48 [V51 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V52 tmp49 [V52 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V53 tmp50 [V53 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V54 tmp51 [V54 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V55 tmp52 [V55,T42] ( 3, 3 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V56 tmp53 [V56 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V57 tmp54 [V57,T31] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V58 tmp55 [V58,T32] ( 3, 6 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V59 tmp56 [V59,T40] ( 2, 4 ) simd16 -> mm3 "impAppendStmt"
+;* V60 tmp57 [V60 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
+; V61 tmp58 [V61,T33] ( 3, 6 ) simd16 -> [rbp-0xD0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V62 tmp59 [V62,T34] ( 3, 6 ) simd16 -> [rbp-0xE0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V63 tmp60 [V63 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V64 tmp61 [V64 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V65 tmp62 [V65 ] ( 2, 5 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V66 tmp63 [V66,T04] ( 5, 17 ) int -> rcx "Inline stloc first use temp"
+; V67 tmp64 [V67 ] ( 2, 10 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V68 tmp65 [V68 ] ( 2, 10 ) struct ( 8) [rbp-0xF8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V69 tmp66 [V69 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V70 tmp67 [V70 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V71 tmp68 [V71 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V72 tmp69 [V72 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V73 tmp70 [V73 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V74 tmp71 [V74 ] ( 2, 5 ) struct ( 8) [rbp-0x100] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V75 tmp72 [V75,T05] ( 5, 17 ) int -> rsi "Inline stloc first use temp"
+; V76 tmp73 [V76 ] ( 2, 10 ) struct ( 8) [rbp-0x108] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V77 tmp74 [V77 ] ( 2, 10 ) struct ( 8) [rbp-0x110] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V78 tmp75 [V78 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V79 tmp76 [V79 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V80 tmp77 [V80 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V81 tmp78 [V81 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V82 tmp79 [V82 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V83 tmp80 [V83,T43] ( 3, 3 ) simd16 -> [rbp-0x120] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V84 tmp81 [V84,T35] ( 3, 6 ) simd16 -> [rbp-0x130] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V85 tmp82 [V85,T36] ( 3, 6 ) simd16 -> [rbp-0x140] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V86 tmp83 [V86 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V87 tmp84 [V87 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V88 tmp85 [V88 ] ( 2, 5 ) struct ( 8) [rbp-0x148] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V89 tmp86 [V89,T06] ( 5, 17 ) int -> rcx "Inline stloc first use temp"
+; V90 tmp87 [V90 ] ( 2, 10 ) struct ( 8) [rbp-0x150] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V91 tmp88 [V91 ] ( 2, 10 ) struct ( 8) [rbp-0x158] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V92 tmp89 [V92 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V93 tmp90 [V93 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V94 tmp91 [V94 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V95 tmp92 [V95 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V96 tmp93 [V96 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V97 tmp94 [V97 ] ( 2, 5 ) struct ( 8) [rbp-0x160] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V98 tmp95 [V98,T07] ( 5, 17 ) int -> rsi "Inline stloc first use temp"
+; V99 tmp96 [V99 ] ( 2, 10 ) struct ( 8) [rbp-0x168] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V100 tmp97 [V100 ] ( 2, 10 ) struct ( 8) [rbp-0x170] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V101 tmp98 [V101 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V102 tmp99 [V102 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V103 tmp100 [V103 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V104 tmp101 [V104 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V105 tmp102 [V105 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V106 tmp103 [V106,T44] ( 3, 3 ) simd16 -> [rbp-0x180] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V107 tmp104 [V107 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+;* V108 tmp105 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[ubyte]>
+; V109 tmp106 [V109,T47] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V110 tmp107 [V110,T48] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V111 tmp108 [V111,T49] ( 1, 1 ) simd32 -> [rbp+0x50] single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V112 tmp109 [V112,T50] ( 1, 1 ) simd32 -> [rbp+0x70] single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+; V113 tmp110 [V113,T17] ( 2, 2 ) long -> rcx "field V12._00 (fldOffset=0x0)" P-INDEP
+; V114 tmp111 [V114,T18] ( 2, 2 ) long -> rax "field V13._00 (fldOffset=0x0)" P-INDEP
+; V115 tmp112 [V115 ] ( 2, 5 ) long -> [rbp-0x28] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
+; V116 tmp113 [V116 ] ( 2, 9 ) long -> [rbp-0x30] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
+; V117 tmp114 [V117 ] ( 2, 9 ) long -> [rbp-0x38] do-not-enreg[X] addr-exposed "field V17._00 (fldOffset=0x0)" P-DEP
+; V118 tmp115 [V118 ] ( 2, 5 ) long -> [rbp-0x40] do-not-enreg[X] addr-exposed "field V23._00 (fldOffset=0x0)" P-DEP
+; V119 tmp116 [V119 ] ( 2, 9 ) long -> [rbp-0x48] do-not-enreg[X] addr-exposed "field V25._00 (fldOffset=0x0)" P-DEP
+; V120 tmp117 [V120 ] ( 2, 9 ) long -> [rbp-0x50] do-not-enreg[X] addr-exposed "field V26._00 (fldOffset=0x0)" P-DEP
+; V121 tmp118 [V121,T19] ( 2, 2 ) long -> rcx "field V35._00 (fldOffset=0x0)" P-INDEP
+; V122 tmp119 [V122,T20] ( 2, 2 ) long -> rax "field V36._00 (fldOffset=0x0)" P-INDEP
+; V123 tmp120 [V123 ] ( 2, 5 ) long -> [rbp-0x88] do-not-enreg[X] addr-exposed "field V37._00 (fldOffset=0x0)" P-DEP
+; V124 tmp121 [V124 ] ( 2, 9 ) long -> [rbp-0x90] do-not-enreg[X] addr-exposed "field V39._00 (fldOffset=0x0)" P-DEP
+; V125 tmp122 [V125 ] ( 2, 9 ) long -> [rbp-0x98] do-not-enreg[X] addr-exposed "field V40._00 (fldOffset=0x0)" P-DEP
+; V126 tmp123 [V126 ] ( 2, 5 ) long -> [rbp-0xA0] do-not-enreg[X] addr-exposed "field V46._00 (fldOffset=0x0)" P-DEP
+; V127 tmp124 [V127 ] ( 2, 9 ) long -> [rbp-0xA8] do-not-enreg[X] addr-exposed "field V48._00 (fldOffset=0x0)" P-DEP
+; V128 tmp125 [V128 ] ( 2, 9 ) long -> [rbp-0xB0] do-not-enreg[X] addr-exposed "field V49._00 (fldOffset=0x0)" P-DEP
+; V129 tmp126 [V129,T21] ( 2, 2 ) long -> rcx "field V63._00 (fldOffset=0x0)" P-INDEP
+; V130 tmp127 [V130,T22] ( 2, 2 ) long -> rax "field V64._00 (fldOffset=0x0)" P-INDEP
+; V131 tmp128 [V131 ] ( 2, 5 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V65._00 (fldOffset=0x0)" P-DEP
+; V132 tmp129 [V132 ] ( 2, 9 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V67._00 (fldOffset=0x0)" P-DEP
+; V133 tmp130 [V133 ] ( 2, 9 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "field V68._00 (fldOffset=0x0)" P-DEP
+; V134 tmp131 [V134 ] ( 2, 5 ) long -> [rbp-0x100] do-not-enreg[X] addr-exposed "field V74._00 (fldOffset=0x0)" P-DEP
+; V135 tmp132 [V135 ] ( 2, 9 ) long -> [rbp-0x108] do-not-enreg[X] addr-exposed "field V76._00 (fldOffset=0x0)" P-DEP
+; V136 tmp133 [V136 ] ( 2, 9 ) long -> [rbp-0x110] do-not-enreg[X] addr-exposed "field V77._00 (fldOffset=0x0)" P-DEP
+; V137 tmp134 [V137,T23] ( 2, 2 ) long -> rcx "field V86._00 (fldOffset=0x0)" P-INDEP
+; V138 tmp135 [V138,T24] ( 2, 2 ) long -> rax "field V87._00 (fldOffset=0x0)" P-INDEP
+; V139 tmp136 [V139 ] ( 2, 5 ) long -> [rbp-0x148] do-not-enreg[X] addr-exposed "field V88._00 (fldOffset=0x0)" P-DEP
+; V140 tmp137 [V140 ] ( 2, 9 ) long -> [rbp-0x150] do-not-enreg[X] addr-exposed "field V90._00 (fldOffset=0x0)" P-DEP
+; V141 tmp138 [V141 ] ( 2, 9 ) long -> [rbp-0x158] do-not-enreg[X] addr-exposed "field V91._00 (fldOffset=0x0)" P-DEP
+; V142 tmp139 [V142 ] ( 2, 5 ) long -> [rbp-0x160] do-not-enreg[X] addr-exposed "field V97._00 (fldOffset=0x0)" P-DEP
+; V143 tmp140 [V143 ] ( 2, 9 ) long -> [rbp-0x168] do-not-enreg[X] addr-exposed "field V99._00 (fldOffset=0x0)" P-DEP
+; V144 tmp141 [V144 ] ( 2, 9 ) long -> [rbp-0x170] do-not-enreg[X] addr-exposed "field V100._00 (fldOffset=0x0)" P-DEP
+; V145 tmp142 [V145,T45] ( 2, 2 ) simd32 -> mm0 "field V108._lower (fldOffset=0x0)" P-INDEP
+; V146 tmp143 [V146,T46] ( 2, 2 ) simd32 -> mm1 "field V108._upper (fldOffset=0x20)" P-INDEP
+; V147 cse0 [V147,T08] ( 4, 16 ) long -> rsi "CSE #01: moderate"
+; V148 cse1 [V148,T09] ( 4, 16 ) long -> r8 "CSE #02: moderate"
+; V149 cse2 [V149,T10] ( 4, 16 ) long -> rsi "CSE #03: moderate"
+; V150 cse3 [V150,T11] ( 4, 16 ) long -> r8 "CSE #04: moderate"
+; V151 cse4 [V151,T12] ( 4, 16 ) long -> rsi "CSE #05: moderate"
+; V152 cse5 [V152,T13] ( 4, 16 ) long -> r8 "CSE #06: moderate"
+; V153 cse6 [V153,T14] ( 4, 16 ) long -> rsi "CSE #07: moderate"
+; V154 cse7 [V154,T15] ( 4, 16 ) long -> r8 "CSE #08: moderate"
;
-; Lcl frame size = 416
+; Lcl frame size = 384
G_M5802_IG01:
push rbp
- push r15
- push r14
- push r13
- push rbx
- sub rsp, 416
- lea rbp, [rsp+0x1C0]
- mov rbx, rdi
- ;; size=26 bbWeight=1 PerfScore 6.00
+ sub rsp, 384
+ lea rbp, [rsp+0x180]
+ ;; size=16 bbWeight=1 PerfScore 1.75
G_M5802_IG02:
vmovups ymm0, ymmword ptr [rbp+0x10]
- vmovups ymmword ptr [rbp-0x90], ymm0
vmovups ymm1, ymmword ptr [rbp+0x50]
- vmovups ymmword ptr [rbp-0xB0], ymm1
vmovaps ymm2, ymm0
- vmovaps xmmword ptr [rbp-0xD0], xmm2
+ vmovaps xmmword ptr [rbp-0x10], xmm2
vmovaps ymm2, ymm1
- vmovaps xmmword ptr [rbp-0xE0], xmm2
- mov rdi, qword ptr [rbp-0xD0]
- mov qword ptr [rbp-0xF0], rdi
- mov rdi, qword ptr [rbp-0xE0]
- mov qword ptr [rbp-0xF8], rdi
- xor r15d, r15d
- ;; size=81 bbWeight=1 PerfScore 16.75
+ vmovaps xmmword ptr [rbp-0x20], xmm2
+ mov rax, qword ptr [rbp-0x10]
+ mov qword ptr [rbp-0x30], rax
+ mov rax, qword ptr [rbp-0x20]
+ mov qword ptr [rbp-0x38], rax
+ xor ecx, ecx
+ align [2 bytes for IG03]
+ ;; size=48 bbWeight=1 PerfScore 15.00
G_M5802_IG03:
- lea rdi, [rbp-0xF0]
- movsxd r14, r15d
- movzx rdi, byte ptr [rdi+r14]
- lea rsi, [rbp-0xF8]
- movzx rsi, byte ptr [rsi+r14]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0xE8]
- mov byte ptr [rdi+r14], al
- inc r15d
- cmp r15d, 8
+ lea rax, [rbp-0x30]
+ movsxd rsi, ecx
+ movzx rax, byte ptr [rax+rsi]
+ lea rdx, [rbp-0x38]
+ movzx r8, byte ptr [rdx+rsi]
+ xor edx, edx
+ div edx:eax, r8d
+ lea rdx, [rbp-0x28]
+ mov byte ptr [rdx+rsi], al
+ inc ecx
+ cmp ecx, 8
jl SHORT G_M5802_IG03
- ;; size=59 bbWeight=4 PerfScore 46.00
+ ;; size=39 bbWeight=4 PerfScore 134.00
G_M5802_IG04:
- mov r15, qword ptr [rbp-0xE8]
- mov rdi, qword ptr [rbp-0xC8]
- mov qword ptr [rbp-0x108], rdi
- mov rdi, qword ptr [rbp-0xD8]
- mov qword ptr [rbp-0x110], rdi
- xor r14d, r14d
- ;; size=38 bbWeight=1 PerfScore 5.25
+ mov rcx, qword ptr [rbp-0x28]
+ mov rax, qword ptr [rbp-0x08]
+ mov qword ptr [rbp-0x48], rax
+ mov rax, qword ptr [rbp-0x18]
+ mov qword ptr [rbp-0x50], rax
+ xor esi, esi
+ align [3 bytes for IG05]
+ ;; size=25 bbWeight=1 PerfScore 5.50
G_M5802_IG05:
- lea rdi, [rbp-0x108]
- movsxd r13, r14d
- movzx rdi, byte ptr [rdi+r13]
- lea rsi, [rbp-0x110]
- movzx rsi, byte ptr [rsi+r13]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0x100]
- mov byte ptr [rdi+r13], al
- inc r14d
- cmp r14d, 8
+ lea rax, [rbp-0x48]
+ movsxd r8, esi
+ movzx rax, byte ptr [rax+r8]
+ lea rdx, [rbp-0x50]
+ movzx r9, byte ptr [rdx+r8]
+ xor edx, edx
+ div edx:eax, r9d
+ lea rdx, [rbp-0x40]
+ mov byte ptr [rdx+r8], al
+ inc esi
+ cmp esi, 8
jl SHORT G_M5802_IG05
- ;; size=59 bbWeight=4 PerfScore 46.00
+ ;; size=41 bbWeight=4 PerfScore 134.00
G_M5802_IG06:
- mov rdi, qword ptr [rbp-0x100]
- mov qword ptr [rbp-0x120], r15
- mov qword ptr [rbp-0x118], rdi
- vmovaps xmm2, xmmword ptr [rbp-0x120]
- vmovaps xmmword ptr [rbp-0xC0], xmm2
- vmovups ymm0, ymmword ptr [rbp-0x90]
+ mov rax, qword ptr [rbp-0x40]
+ mov qword ptr [rbp-0x60], rcx
+ mov qword ptr [rbp-0x58], rax
+ vmovaps xmm2, xmmword ptr [rbp-0x60]
vextractf128 xmm0, ymm0, 1
- vmovaps xmmword ptr [rbp-0x130], xmm0
- vmovups ymm1, ymmword ptr [rbp-0xB0]
+ vmovaps xmmword ptr [rbp-0x70], xmm0
vextractf128 xmm0, ymm1, 1
- vmovaps xmmword ptr [rbp-0x140], xmm0
- mov rdi, qword ptr [rbp-0x130]
- mov qword ptr [rbp-0x150], rdi
- mov rdi, qword ptr [rbp-0x140]
- mov qword ptr [rbp-0x158], rdi
- xor r15d, r15d
- ;; size=112 bbWeight=1 PerfScore 25.25
+ vmovaps xmmword ptr [rbp-0x80], xmm0
+ mov rax, qword ptr [rbp-0x70]
+ mov qword ptr [rbp-0x90], rax
+ mov rax, qword ptr [rbp-0x80]
+ mov qword ptr [rbp-0x98], rax
+ xor ecx, ecx
+ align [0 bytes for IG07]
+ ;; size=63 bbWeight=1 PerfScore 16.25
G_M5802_IG07:
- lea rdi, [rbp-0x150]
- movsxd r14, r15d
- movzx rdi, byte ptr [rdi+r14]
- lea rsi, [rbp-0x158]
- movzx rsi, byte ptr [rsi+r14]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0x148]
- mov byte ptr [rdi+r14], al
- inc r15d
- cmp r15d, 8
+ lea rax, [rbp-0x90]
+ movsxd rsi, ecx
+ movzx rax, byte ptr [rax+rsi]
+ lea rdx, [rbp-0x98]
+ movzx r8, byte ptr [rdx+rsi]
+ xor edx, edx
+ div edx:eax, r8d
+ lea rdx, [rbp-0x88]
+ mov byte ptr [rdx+rsi], al
+ inc ecx
+ cmp ecx, 8
jl SHORT G_M5802_IG07
- ;; size=59 bbWeight=4 PerfScore 46.00
+ ;; size=48 bbWeight=4 PerfScore 134.00
G_M5802_IG08:
- mov r15, qword ptr [rbp-0x148]
- mov rdi, qword ptr [rbp-0x128]
- mov qword ptr [rbp-0x168], rdi
- mov rdi, qword ptr [rbp-0x138]
- mov qword ptr [rbp-0x170], rdi
- xor r14d, r14d
- ;; size=38 bbWeight=1 PerfScore 5.25
+ mov rcx, qword ptr [rbp-0x88]
+ mov rax, qword ptr [rbp-0x68]
+ mov qword ptr [rbp-0xA8], rax
+ mov rax, qword ptr [rbp-0x78]
+ mov qword ptr [rbp-0xB0], rax
+ xor esi, esi
+ align [0 bytes for IG09]
+ ;; size=31 bbWeight=1 PerfScore 5.25
G_M5802_IG09:
- lea rdi, [rbp-0x168]
- movsxd r13, r14d
- movzx rdi, byte ptr [rdi+r13]
- lea rsi, [rbp-0x170]
- movzx rsi, byte ptr [rsi+r13]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0x160]
- mov byte ptr [rdi+r13], al
- inc r14d
- cmp r14d, 8
+ lea rax, [rbp-0xA8]
+ movsxd r8, esi
+ movzx rax, byte ptr [rax+r8]
+ lea rdx, [rbp-0xB0]
+ movzx r9, byte ptr [rdx+r8]
+ xor edx, edx
+ div edx:eax, r9d
+ lea rdx, [rbp-0xA0]
+ mov byte ptr [rdx+r8], al
+ inc esi
+ cmp esi, 8
jl SHORT G_M5802_IG09
- ;; size=59 bbWeight=4 PerfScore 46.00
+ ;; size=50 bbWeight=4 PerfScore 134.00
G_M5802_IG10:
- mov rdi, qword ptr [rbp-0x160]
- mov qword ptr [rbp-0x180], r15
- mov qword ptr [rbp-0x178], rdi
- vmovaps xmm2, xmmword ptr [rbp-0xC0]
- vmovups xmmword ptr [rsp], xmm2
- vmovaps xmm0, xmmword ptr [rbp-0x180]
- vmovups xmmword ptr [rsp+0x10], xmm0
- lea rdi, [rbp-0x50]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector256:Create[ubyte](System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector256`1[ubyte]
- call [rax]System.Runtime.Intrinsics.Vector256:Create[ubyte](System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector256`1[ubyte]
- vmovups ymm0, ymmword ptr [rbp+0x30]
- vmovups ymmword ptr [rsp], ymm0
- vmovups ymm0, ymmword ptr [rbp+0x70]
- vmovups ymmword ptr [rsp+0x20], ymm0
- lea rdi, [rbp-0x70]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector256`1[ubyte]:op_Division(System.Runtime.Intrinsics.Vector256`1[ubyte],System.Runtime.Intrinsics.Vector256`1[ubyte]):System.Runtime.Intrinsics.Vector256`1[ubyte]
- call [rax]System.Runtime.Intrinsics.Vector256`1[ubyte]:op_Division(System.Runtime.Intrinsics.Vector256`1[ubyte],System.Runtime.Intrinsics.Vector256`1[ubyte]):System.Runtime.Intrinsics.Vector256`1[ubyte]
- vmovups ymm0, ymmword ptr [rbp-0x50]
- vmovups ymmword ptr [rsp], ymm0
- vmovups ymm0, ymmword ptr [rbp-0x70]
- vmovups ymmword ptr [rsp+0x20], ymm0
- mov rdi, rbx
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector512:Create[ubyte](System.Runtime.Intrinsics.Vector256`1[ubyte],System.Runtime.Intrinsics.Vector256`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte]
- call [rax]System.Runtime.Intrinsics.Vector512:Create[ubyte](System.Runtime.Intrinsics.Vector256`1[ubyte],System.Runtime.Intrinsics.Vector256`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte]
- mov rax, rbx
- ;; size=140 bbWeight=1 PerfScore 42.25
+ mov rax, qword ptr [rbp-0xA0]
+ mov qword ptr [rbp-0xC0], rcx
+ mov qword ptr [rbp-0xB8], rax
+ vinserti128 ymm0, ymm2, xmmword ptr [rbp-0xC0], 1
+ vmovups ymm1, ymmword ptr [rbp+0x30]
+ vmovups ymm2, ymmword ptr [rbp+0x70]
+ vmovaps ymm3, ymm1
+ vmovaps xmmword ptr [rbp-0xD0], xmm3
+ vmovaps ymm3, ymm2
+ vmovaps xmmword ptr [rbp-0xE0], xmm3
+ mov rax, qword ptr [rbp-0xD0]
+ mov qword ptr [rbp-0xF0], rax
+ mov rax, qword ptr [rbp-0xE0]
+ mov qword ptr [rbp-0xF8], rax
+ xor ecx, ecx
+ align [0 bytes for IG11]
+ ;; size=95 bbWeight=1 PerfScore 21.75
G_M5802_IG11:
+ lea rax, [rbp-0xF0]
+ movsxd rsi, ecx
+ movzx rax, byte ptr [rax+rsi]
+ lea rdx, [rbp-0xF8]
+ movzx r8, byte ptr [rdx+rsi]
+ xor edx, edx
+ div edx:eax, r8d
+ lea rdx, [rbp-0xE8]
+ mov byte ptr [rdx+rsi], al
+ inc ecx
+ cmp ecx, 8
+ jl SHORT G_M5802_IG11
+ ;; size=48 bbWeight=4 PerfScore 134.00
+G_M5802_IG12:
+ mov rcx, qword ptr [rbp-0xE8]
+ mov rax, qword ptr [rbp-0xC8]
+ mov qword ptr [rbp-0x108], rax
+ mov rax, qword ptr [rbp-0xD8]
+ mov qword ptr [rbp-0x110], rax
+ xor esi, esi
+ align [3 bytes for IG13]
+ ;; size=40 bbWeight=1 PerfScore 5.50
+G_M5802_IG13:
+ lea rax, [rbp-0x108]
+ movsxd r8, esi
+ movzx rax, byte ptr [rax+r8]
+ lea rdx, [rbp-0x110]
+ movzx r9, byte ptr [rdx+r8]
+ xor edx, edx
+ div edx:eax, r9d
+ lea rdx, [rbp-0x100]
+ mov byte ptr [rdx+r8], al
+ inc esi
+ cmp esi, 8
+ jl SHORT G_M5802_IG13
+ ;; size=50 bbWeight=4 PerfScore 134.00
+G_M5802_IG14:
+ mov rax, qword ptr [rbp-0x100]
+ mov qword ptr [rbp-0x120], rcx
+ mov qword ptr [rbp-0x118], rax
+ vmovaps xmm3, xmmword ptr [rbp-0x120]
+ vextractf128 xmm1, ymm1, 1
+ vmovaps xmmword ptr [rbp-0x130], xmm1
+ vextractf128 xmm1, ymm2, 1
+ vmovaps xmmword ptr [rbp-0x140], xmm1
+ mov rax, qword ptr [rbp-0x130]
+ mov qword ptr [rbp-0x150], rax
+ mov rax, qword ptr [rbp-0x140]
+ mov qword ptr [rbp-0x158], rax
+ xor ecx, ecx
+ align [0 bytes for IG15]
+ ;; size=87 bbWeight=1 PerfScore 16.25
+G_M5802_IG15:
+ lea rax, [rbp-0x150]
+ movsxd rsi, ecx
+ movzx rax, byte ptr [rax+rsi]
+ lea rdx, [rbp-0x158]
+ movzx r8, byte ptr [rdx+rsi]
+ xor edx, edx
+ div edx:eax, r8d
+ lea rdx, [rbp-0x148]
+ mov byte ptr [rdx+rsi], al
+ inc ecx
+ cmp ecx, 8
+ jl SHORT G_M5802_IG15
+ ;; size=48 bbWeight=4 PerfScore 134.00
+G_M5802_IG16:
+ mov rcx, qword ptr [rbp-0x148]
+ mov rax, qword ptr [rbp-0x128]
+ mov qword ptr [rbp-0x168], rax
+ mov rax, qword ptr [rbp-0x138]
+ mov qword ptr [rbp-0x170], rax
+ xor esi, esi
+ align [2 bytes for IG17]
+ ;; size=39 bbWeight=1 PerfScore 5.50
+G_M5802_IG17:
+ lea rax, [rbp-0x168]
+ movsxd r8, esi
+ movzx rax, byte ptr [rax+r8]
+ lea rdx, [rbp-0x170]
+ movzx r9, byte ptr [rdx+r8]
+ xor edx, edx
+ div edx:eax, r9d
+ lea rdx, [rbp-0x160]
+ mov byte ptr [rdx+r8], al
+ inc esi
+ cmp esi, 8
+ jl SHORT G_M5802_IG17
+ ;; size=50 bbWeight=4 PerfScore 134.00
+G_M5802_IG18:
+ mov rax, qword ptr [rbp-0x160]
+ mov qword ptr [rbp-0x180], rcx
+ mov qword ptr [rbp-0x178], rax
+ vinserti128 ymm1, ymm3, xmmword ptr [rbp-0x180], 1
+ vmovups ymmword ptr [rdi], ymm0
+ vmovups ymmword ptr [rdi+0x20], ymm1
+ mov rax, rdi
+ ;; size=43 bbWeight=1 PerfScore 11.25
+G_M5802_IG19:
vzeroupper
- add rsp, 416
- pop rbx
- pop r13
- pop r14
- pop r15
+ add rsp, 384
pop rbp
ret
- ;; size=19 bbWeight=1 PerfScore 4.75
+ ;; size=12 bbWeight=1 PerfScore 2.75
-; Total bytes of code 690, prolog size 23, PerfScore 289.50, instruction count 130, allocated bytes for code 690 (MethodHash=d21fe955) for method System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],System.Runtime.Intrinsics.Vector512`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte] (FullOpts)
+; Total bytes of code 873, prolog size 16, PerfScore 1178.75, instruction count 194, allocated bytes for code 873 (MethodHash=d21fe955) for method System.Runtime.Intrinsics.Vector512`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Divide(System.Runtime.Intrinsics.Vector512`1[ubyte],System.Runtime.Intrinsics.Vector512`1[ubyte]):System.Runtime.Intrinsics.Vector512`1[ubyte] (FullOpts)138 (418.18 % of base) - System.Runtime.Intrinsics.Vector128:Sum[ubyte](System.Runtime.Intrinsics.Vector128`1[ubyte]):ubyte
; Assembly listing for method System.Runtime.Intrinsics.Vector128:Sum[ubyte](System.Runtime.Intrinsics.Vector128`1[ubyte]):ubyte (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
-; fully interruptible
+; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data
+; 0 inlinees with PGO data; 2 single block inlinees; 5 inlinees without PGO data
; Final local variable assignments
;
-; V00 arg0 [V00 ] ( 1, 4 ) simd16 -> [rbp+0x10] do-not-enreg[XS] addr-exposed ld-addr-op single-def <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-; V01 loc0 [V01,T01] ( 4, 10 ) ubyte -> rax ld-addr-op
-; V02 loc1 [V02,T00] ( 5, 17 ) int -> rcx
-;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
-;* V04 tmp1 [V04 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
-;* V05 tmp2 [V05 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
-;* V06 tmp3 [V06 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
-;* V07 tmp4 [V07 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V00 arg0 [V00,T07] ( 2, 2 ) simd16 -> [rbp+0x10] do-not-enreg[SF] single-def <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
+; V02 tmp1 [V02,T02] ( 2, 4 ) int -> rax "impAppendStmt"
+; V03 tmp2 [V03,T00] ( 16, 16 ) ubyte -> rax ld-addr-op "Inline ldloca(s) first use temp"
+;* V04 tmp3 [V04,T05] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V05 tmp4 [V05 ] ( 9, 18 ) struct ( 8) [rbp-0x08] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V06 tmp5 [V06 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V07 tmp6 [V07 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V08 tmp7 [V08 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V09 tmp8 [V09 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V10 tmp9 [V10,T01] ( 16, 16 ) ubyte -> rcx ld-addr-op "Inline ldloca(s) first use temp"
+;* V11 tmp10 [V11,T06] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V12 tmp11 [V12 ] ( 9, 18 ) struct ( 8) [rbp-0x10] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V13 tmp12 [V13 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
+;* V14 tmp13 [V14 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V15 tmp14 [V15 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V16 tmp15 [V16 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V17 tmp16 [V17 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V18 tmp17 [V18 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+;* V19 tmp18 [V19 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V20 tmp19 [V20 ] ( 9, 17 ) long -> [rbp-0x08] do-not-enreg[X] addr-exposed "field V05._00 (fldOffset=0x0)" P-DEP
+; V21 tmp20 [V21 ] ( 9, 17 ) long -> [rbp-0x10] do-not-enreg[X] addr-exposed "field V12._00 (fldOffset=0x0)" P-DEP
+; V22 cse0 [V22,T03] ( 2, 2 ) int -> rax "CSE #01: moderate"
+; V23 cse1 [V23,T04] ( 2, 2 ) int -> rcx "CSE #02: moderate"
;
-; Lcl frame size = 0
+; Lcl frame size = 16
G_M25758_IG01:
push rbp
- mov rbp, rsp
- ;; size=4 bbWeight=1 PerfScore 1.25
+ sub rsp, 16
+ lea rbp, [rsp+0x10]
+ ;; size=10 bbWeight=1 PerfScore 1.75
G_M25758_IG02:
- xor eax, eax
- xor ecx, ecx
- align [0 bytes for IG03]
- ;; size=4 bbWeight=1 PerfScore 0.50
-G_M25758_IG03:
- lea rdx, [rbp+0x10]
- movsxd rdi, ecx
- movzx rdx, byte ptr [rdx+rdi]
- add eax, edx
+ mov rax, qword ptr [rbp+0x10]
+ mov qword ptr [rbp-0x08], rax
+ movzx rax, byte ptr [rbp-0x08]
+ movzx rcx, byte ptr [rbp-0x07]
+ add eax, ecx
+ movzx rax, al
+ movzx rcx, byte ptr [rbp-0x06]
+ add ecx, eax
+ movzx rax, cl
+ movzx rcx, byte ptr [rbp-0x05]
+ add ecx, eax
+ movzx rax, cl
+ movzx rcx, byte ptr [rbp-0x04]
+ add ecx, eax
+ movzx rax, cl
+ movzx rcx, byte ptr [rbp-0x03]
+ add ecx, eax
+ movzx rax, cl
+ movzx rcx, byte ptr [rbp-0x02]
+ add ecx, eax
+ movzx rax, cl
+ movzx rcx, byte ptr [rbp-0x01]
+ add ecx, eax
+ movzx rax, cl
+ mov rcx, qword ptr [rbp+0x18]
+ mov qword ptr [rbp-0x10], rcx
+ movzx rcx, byte ptr [rbp-0x10]
+ movzx rdx, byte ptr [rbp-0x0F]
+ add ecx, edx
+ movzx rcx, cl
+ movzx rdx, byte ptr [rbp-0x0E]
+ add edx, ecx
+ movzx rcx, dl
+ movzx rdx, byte ptr [rbp-0x0D]
+ add edx, ecx
+ movzx rcx, dl
+ movzx rdx, byte ptr [rbp-0x0C]
+ add edx, ecx
+ movzx rcx, dl
+ movzx rdx, byte ptr [rbp-0x0B]
+ add edx, ecx
+ movzx rcx, dl
+ movzx rdx, byte ptr [rbp-0x0A]
+ add edx, ecx
+ movzx rcx, dl
+ movzx rdx, byte ptr [rbp-0x09]
+ add edx, ecx
+ movzx rcx, dl
+ add eax, ecx
movzx rax, al
- inc ecx
- cmp ecx, 16
- jl SHORT G_M25758_IG03
- ;; size=23 bbWeight=4 PerfScore 19.00
-G_M25758_IG04:
+ ;; size=155 bbWeight=1 PerfScore 27.50
+G_M25758_IG03:
+ add rsp, 16
pop rbp
ret
- ;; size=2 bbWeight=1 PerfScore 1.50
+ ;; size=6 bbWeight=1 PerfScore 1.75
-; Total bytes of code 33, prolog size 4, PerfScore 22.25, instruction count 15, allocated bytes for code 33 (MethodHash=651f9b61) for method System.Runtime.Intrinsics.Vector128:Sum[ubyte](System.Runtime.Intrinsics.Vector128`1[ubyte]):ubyte (FullOpts)
+; Total bytes of code 171, prolog size 10, PerfScore 31.00, instruction count 56, allocated bytes for code 171 (MethodHash=651f9b61) for method System.Runtime.Intrinsics.Vector128:Sum[ubyte](System.Runtime.Intrinsics.Vector128`1[ubyte]):ubyte (FullOpts)101 (17.50 % of base) - System.Runtime.Intrinsics.Vector512`1[long]:System.Runtime.Intrinsics.ISimdVector,T>.Dot(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):long
; Assembly listing for method System.Runtime.Intrinsics.Vector512`1[long]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Dot(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):long (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 24 single block inlinees; 9 inlinees without PGO data
+; 0 inlinees with PGO data; 44 single block inlinees; 28 inlinees without PGO data
; Final local variable assignments
;
;* V00 arg0 [V00 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V01 arg1 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
-; V02 OutArgs [V02 ] ( 1, 1 ) struct (64) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
-;* V03 tmp1 [V03 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-; V04 tmp2 [V04,T26] ( 3, 6 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V05 tmp3 [V05,T27] ( 3, 6 ) simd32 -> [rbp-0x50] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V06 tmp4 [V06,T00] ( 2, 4 ) long -> rbx "impAppendStmt"
-; V07 tmp5 [V07,T28] ( 3, 6 ) simd16 -> [rbp-0x60] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
-; V08 tmp6 [V08,T29] ( 3, 6 ) simd16 -> [rbp-0x70] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
-; V09 tmp7 [V09,T01] ( 2, 4 ) long -> rbx "impAppendStmt"
-;* V10 tmp8 [V10 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V11 tmp9 [V11 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V12 tmp10 [V12 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V13 tmp11 [V13 ] ( 2, 2 ) struct ( 8) [rbp-0x78] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V14 tmp12 [V14,T18] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V15 tmp13 [V15 ] ( 2, 4 ) struct ( 8) [rbp-0x80] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V16 tmp14 [V16 ] ( 2, 4 ) struct ( 8) [rbp-0x88] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V17 tmp15 [V17 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-;* V18 tmp16 [V18 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
-;* V19 tmp17 [V19 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
-;* V20 tmp18 [V20 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
-; V21 tmp19 [V21,T06] ( 2, 2 ) long -> rbx ld-addr-op "Inline ldloca(s) first use temp"
-;* V22 tmp20 [V22,T19] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V23 tmp21 [V23 ] ( 2, 4 ) struct ( 8) [rbp-0x90] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V24 tmp22 [V24 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-;* V25 tmp23 [V25 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V26 tmp24 [V26 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V27 tmp25 [V27 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V28 tmp26 [V28 ] ( 2, 2 ) struct ( 8) [rbp-0x98] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V29 tmp27 [V29,T20] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V30 tmp28 [V30 ] ( 2, 4 ) struct ( 8) [rbp-0xA0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V31 tmp29 [V31 ] ( 2, 4 ) struct ( 8) [rbp-0xA8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V32 tmp30 [V32 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-;* V33 tmp31 [V33 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
-; V34 tmp32 [V34,T07] ( 2, 2 ) long -> rsi ld-addr-op "Inline ldloca(s) first use temp"
-;* V35 tmp33 [V35,T21] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V36 tmp34 [V36 ] ( 2, 4 ) struct ( 8) [rbp-0xB0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V37 tmp35 [V37 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-; V38 tmp36 [V38,T30] ( 3, 6 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
-; V39 tmp37 [V39,T31] ( 3, 6 ) simd16 -> [rbp-0xD0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
-; V40 tmp38 [V40,T02] ( 2, 4 ) long -> r15 "impAppendStmt"
-;* V41 tmp39 [V41 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V42 tmp40 [V42 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V43 tmp41 [V43 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V44 tmp42 [V44 ] ( 2, 2 ) struct ( 8) [rbp-0xD8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V45 tmp43 [V45,T22] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V46 tmp44 [V46 ] ( 2, 4 ) struct ( 8) [rbp-0xE0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V47 tmp45 [V47 ] ( 2, 4 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V48 tmp46 [V48 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-;* V49 tmp47 [V49 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
-; V50 tmp48 [V50,T08] ( 2, 2 ) long -> r15 ld-addr-op "Inline ldloca(s) first use temp"
-;* V51 tmp49 [V51,T23] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V52 tmp50 [V52 ] ( 2, 4 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V53 tmp51 [V53 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-;* V54 tmp52 [V54 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V55 tmp53 [V55 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V56 tmp54 [V56 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V57 tmp55 [V57 ] ( 2, 2 ) struct ( 8) [rbp-0xF8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V58 tmp56 [V58,T24] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V59 tmp57 [V59 ] ( 2, 4 ) struct ( 8) [rbp-0x100] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-; V60 tmp58 [V60 ] ( 2, 4 ) struct ( 8) [rbp-0x108] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V61 tmp59 [V61 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-;* V62 tmp60 [V62 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
-; V63 tmp61 [V63,T09] ( 2, 2 ) long -> rsi ld-addr-op "Inline ldloca(s) first use temp"
-;* V64 tmp62 [V64,T25] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
-; V65 tmp63 [V65 ] ( 2, 4 ) struct ( 8) [rbp-0x110] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
-;* V66 tmp64 [V66 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
-; V67 tmp65 [V67,T32] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V00._lower (fldOffset=0x0)" P-INDEP
-; V68 tmp66 [V68,T33] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V00._upper (fldOffset=0x20)" P-INDEP
-; V69 tmp67 [V69,T34] ( 1, 1 ) simd32 -> [rbp+0x50] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V70 tmp68 [V70,T35] ( 1, 1 ) simd32 -> [rbp+0x70] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V71 tmp69 [V71,T10] ( 2, 2 ) long -> rsi "field V10._00 (fldOffset=0x0)" P-INDEP
-; V72 tmp70 [V72,T11] ( 2, 2 ) long -> rdi "field V11._00 (fldOffset=0x0)" P-INDEP
-;* V73 tmp71 [V73 ] ( 0, 0 ) long -> zero-ref "field V12._00 (fldOffset=0x0)" P-INDEP
-; V74 tmp72 [V74 ] ( 2, 2 ) long -> [rbp-0x78] do-not-enreg[X] addr-exposed "field V13._00 (fldOffset=0x0)" P-DEP
-; V75 tmp73 [V75 ] ( 2, 3 ) long -> [rbp-0x80] do-not-enreg[X] addr-exposed "field V15._00 (fldOffset=0x0)" P-DEP
-; V76 tmp74 [V76 ] ( 2, 3 ) long -> [rbp-0x88] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
-; V77 tmp75 [V77 ] ( 2, 3 ) long -> [rbp-0x90] do-not-enreg[X] addr-exposed "field V23._00 (fldOffset=0x0)" P-DEP
-; V78 tmp76 [V78,T12] ( 2, 2 ) long -> rdi "field V25._00 (fldOffset=0x0)" P-INDEP
-; V79 tmp77 [V79,T13] ( 2, 2 ) long -> rsi "field V26._00 (fldOffset=0x0)" P-INDEP
-;* V80 tmp78 [V80 ] ( 0, 0 ) long -> zero-ref "field V27._00 (fldOffset=0x0)" P-INDEP
-; V81 tmp79 [V81 ] ( 2, 2 ) long -> [rbp-0x98] do-not-enreg[X] addr-exposed "field V28._00 (fldOffset=0x0)" P-DEP
-; V82 tmp80 [V82 ] ( 2, 3 ) long -> [rbp-0xA0] do-not-enreg[X] addr-exposed "field V30._00 (fldOffset=0x0)" P-DEP
-; V83 tmp81 [V83 ] ( 2, 3 ) long -> [rbp-0xA8] do-not-enreg[X] addr-exposed "field V31._00 (fldOffset=0x0)" P-DEP
-; V84 tmp82 [V84 ] ( 2, 3 ) long -> [rbp-0xB0] do-not-enreg[X] addr-exposed "field V36._00 (fldOffset=0x0)" P-DEP
-; V85 tmp83 [V85,T14] ( 2, 2 ) long -> rdi "field V41._00 (fldOffset=0x0)" P-INDEP
-; V86 tmp84 [V86,T15] ( 2, 2 ) long -> rsi "field V42._00 (fldOffset=0x0)" P-INDEP
-;* V87 tmp85 [V87 ] ( 0, 0 ) long -> zero-ref "field V43._00 (fldOffset=0x0)" P-INDEP
-; V88 tmp86 [V88 ] ( 2, 2 ) long -> [rbp-0xD8] do-not-enreg[X] addr-exposed "field V44._00 (fldOffset=0x0)" P-DEP
-; V89 tmp87 [V89 ] ( 2, 3 ) long -> [rbp-0xE0] do-not-enreg[X] addr-exposed "field V46._00 (fldOffset=0x0)" P-DEP
-; V90 tmp88 [V90 ] ( 2, 3 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V47._00 (fldOffset=0x0)" P-DEP
-; V91 tmp89 [V91 ] ( 2, 3 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V52._00 (fldOffset=0x0)" P-DEP
-; V92 tmp90 [V92,T16] ( 2, 2 ) long -> rdi "field V54._00 (fldOffset=0x0)" P-INDEP
-; V93 tmp91 [V93,T17] ( 2, 2 ) long -> rsi "field V55._00 (fldOffset=0x0)" P-INDEP
-;* V94 tmp92 [V94 ] ( 0, 0 ) long -> zero-ref "field V56._00 (fldOffset=0x0)" P-INDEP
-; V95 tmp93 [V95 ] ( 2, 2 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "field V57._00 (fldOffset=0x0)" P-DEP
-; V96 tmp94 [V96 ] ( 2, 3 ) long -> [rbp-0x100] do-not-enreg[X] addr-exposed "field V59._00 (fldOffset=0x0)" P-DEP
-; V97 tmp95 [V97 ] ( 2, 3 ) long -> [rbp-0x108] do-not-enreg[X] addr-exposed "field V60._00 (fldOffset=0x0)" P-DEP
-; V98 tmp96 [V98 ] ( 2, 3 ) long -> [rbp-0x110] do-not-enreg[X] addr-exposed "field V65._00 (fldOffset=0x0)" P-DEP
-; V99 tmp97 [V99,T03] ( 2, 4 ) long -> rsi "argument with side effect"
-; V100 tmp98 [V100,T04] ( 2, 4 ) long -> rbx "argument with side effect"
-; V101 tmp99 [V101,T05] ( 2, 4 ) long -> rsi "argument with side effect"
+;# V02 OutArgs [V02 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
+;* V03 tmp1 [V03 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V04 tmp2 [V04,T18] ( 3, 6 ) simd32 -> mm0 "impAppendStmt"
+; V05 tmp3 [V05,T19] ( 3, 6 ) simd32 -> mm1 "spilled call-like call argument"
+; V06 tmp4 [V06,T20] ( 3, 6 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V07 tmp5 [V07,T21] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V08 tmp6 [V08,T34] ( 2, 4 ) simd16 -> mm2 "impAppendStmt"
+;* V09 tmp7 [V09 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
+; V10 tmp8 [V10,T22] ( 3, 6 ) simd16 -> [rbp-0x10] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+; V11 tmp9 [V11,T23] ( 3, 6 ) simd16 -> [rbp-0x20] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+;* V12 tmp10 [V12 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V13 tmp11 [V13 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V14 tmp12 [V14 ] ( 2, 2 ) struct ( 8) [rbp-0x28] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V15 tmp13 [V15,T10] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V16 tmp14 [V16 ] ( 2, 4 ) struct ( 8) [rbp-0x30] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V17 tmp15 [V17 ] ( 2, 4 ) struct ( 8) [rbp-0x38] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V18 tmp16 [V18 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V19 tmp17 [V19 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V20 tmp18 [V20 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V21 tmp19 [V21 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V22 tmp20 [V22 ] ( 2, 2 ) struct ( 8) [rbp-0x40] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V23 tmp21 [V23,T11] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V24 tmp22 [V24 ] ( 2, 4 ) struct ( 8) [rbp-0x48] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V25 tmp23 [V25 ] ( 2, 4 ) struct ( 8) [rbp-0x50] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V26 tmp24 [V26 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V27 tmp25 [V27 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V28 tmp26 [V28 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V29 tmp27 [V29 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V30 tmp28 [V30,T36] ( 3, 3 ) simd16 -> [rbp-0x60] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[long]>
+; V31 tmp29 [V31,T24] ( 3, 6 ) simd16 -> [rbp-0x70] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+; V32 tmp30 [V32,T25] ( 3, 6 ) simd16 -> [rbp-0x80] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+;* V33 tmp31 [V33 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V34 tmp32 [V34 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V35 tmp33 [V35 ] ( 2, 2 ) struct ( 8) [rbp-0x88] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V36 tmp34 [V36,T12] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V37 tmp35 [V37 ] ( 2, 4 ) struct ( 8) [rbp-0x90] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V38 tmp36 [V38 ] ( 2, 4 ) struct ( 8) [rbp-0x98] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V39 tmp37 [V39 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V40 tmp38 [V40 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V41 tmp39 [V41 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V42 tmp40 [V42 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V43 tmp41 [V43 ] ( 2, 2 ) struct ( 8) [rbp-0xA0] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V44 tmp42 [V44,T13] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V45 tmp43 [V45 ] ( 2, 4 ) struct ( 8) [rbp-0xA8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V46 tmp44 [V46 ] ( 2, 4 ) struct ( 8) [rbp-0xB0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V47 tmp45 [V47 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V48 tmp46 [V48 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V49 tmp47 [V49 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V50 tmp48 [V50 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V51 tmp49 [V51,T37] ( 3, 3 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[long]>
+;* V52 tmp50 [V52 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V53 tmp51 [V53,T26] ( 3, 6 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V54 tmp52 [V54,T27] ( 3, 6 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V55 tmp53 [V55,T35] ( 2, 4 ) simd16 -> mm3 "impAppendStmt"
+;* V56 tmp54 [V56 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
+; V57 tmp55 [V57,T28] ( 3, 6 ) simd16 -> [rbp-0xD0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+; V58 tmp56 [V58,T29] ( 3, 6 ) simd16 -> [rbp-0xE0] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+;* V59 tmp57 [V59 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V60 tmp58 [V60 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V61 tmp59 [V61 ] ( 2, 2 ) struct ( 8) [rbp-0xE8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V62 tmp60 [V62,T14] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V63 tmp61 [V63 ] ( 2, 4 ) struct ( 8) [rbp-0xF0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V64 tmp62 [V64 ] ( 2, 4 ) struct ( 8) [rbp-0xF8] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V65 tmp63 [V65 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V66 tmp64 [V66 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V67 tmp65 [V67 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V68 tmp66 [V68 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V69 tmp67 [V69 ] ( 2, 2 ) struct ( 8) [rbp-0x100] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V70 tmp68 [V70,T15] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V71 tmp69 [V71 ] ( 2, 4 ) struct ( 8) [rbp-0x108] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V72 tmp70 [V72 ] ( 2, 4 ) struct ( 8) [rbp-0x110] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V73 tmp71 [V73 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V74 tmp72 [V74 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V75 tmp73 [V75 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V76 tmp74 [V76 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V77 tmp75 [V77,T38] ( 3, 3 ) simd16 -> [rbp-0x120] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[long]>
+; V78 tmp76 [V78,T30] ( 3, 6 ) simd16 -> [rbp-0x130] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+; V79 tmp77 [V79,T31] ( 3, 6 ) simd16 -> [rbp-0x140] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[long]>
+;* V80 tmp78 [V80 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V81 tmp79 [V81 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V82 tmp80 [V82 ] ( 2, 2 ) struct ( 8) [rbp-0x148] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V83 tmp81 [V83,T16] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V84 tmp82 [V84 ] ( 2, 4 ) struct ( 8) [rbp-0x150] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V85 tmp83 [V85 ] ( 2, 4 ) struct ( 8) [rbp-0x158] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V86 tmp84 [V86 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V87 tmp85 [V87 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V88 tmp86 [V88 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V89 tmp87 [V89 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V90 tmp88 [V90 ] ( 2, 2 ) struct ( 8) [rbp-0x160] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V91 tmp89 [V91,T17] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V92 tmp90 [V92 ] ( 2, 4 ) struct ( 8) [rbp-0x168] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+; V93 tmp91 [V93 ] ( 2, 4 ) struct ( 8) [rbp-0x170] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[long]>
+;* V94 tmp92 [V94 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
+;* V95 tmp93 [V95 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
+;* V96 tmp94 [V96 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+;* V97 tmp95 [V97 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
+; V98 tmp96 [V98,T39] ( 3, 3 ) simd16 -> [rbp-0x180] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[long]>
+;* V99 tmp97 [V99 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V100 tmp98 [V100 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V101 tmp99 [V101 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+; V102 tmp100 [V102,T32] ( 3, 6 ) simd16 -> mm0 "fgMakeTemp is creating a new local variable"
+;* V103 tmp101 [V103 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+; V104 tmp102 [V104,T33] ( 3, 6 ) simd16 -> mm0 "fgMakeTemp is creating a new local variable"
+;* V105 tmp103 [V105 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
+; V106 tmp104 [V106,T00] ( 2, 4 ) long -> rax "Inlining Arg"
+; V107 tmp105 [V107,T01] ( 2, 4 ) long -> rcx "Inlining Arg"
+; V108 tmp106 [V108,T40] ( 1, 1 ) simd32 -> [rbp+0x10] single-def "field V00._lower (fldOffset=0x0)" P-INDEP
+; V109 tmp107 [V109,T41] ( 1, 1 ) simd32 -> [rbp+0x30] single-def "field V00._upper (fldOffset=0x20)" P-INDEP
+; V110 tmp108 [V110,T42] ( 1, 1 ) simd32 -> [rbp+0x50] single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V111 tmp109 [V111,T43] ( 1, 1 ) simd32 -> [rbp+0x70] single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+;* V112 tmp110 [V112 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V113 tmp111 [V113 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
+; V114 tmp112 [V114,T02] ( 2, 2 ) long -> rax "field V12._00 (fldOffset=0x0)" P-INDEP
+; V115 tmp113 [V115,T03] ( 2, 2 ) long -> rcx "field V13._00 (fldOffset=0x0)" P-INDEP
+; V116 tmp114 [V116 ] ( 2, 2 ) long -> [rbp-0x28] do-not-enreg[X] addr-exposed "field V14._00 (fldOffset=0x0)" P-DEP
+; V117 tmp115 [V117 ] ( 2, 3 ) long -> [rbp-0x30] do-not-enreg[X] addr-exposed "field V16._00 (fldOffset=0x0)" P-DEP
+; V118 tmp116 [V118 ] ( 2, 3 ) long -> [rbp-0x38] do-not-enreg[X] addr-exposed "field V17._00 (fldOffset=0x0)" P-DEP
+; V119 tmp117 [V119 ] ( 2, 2 ) long -> [rbp-0x40] do-not-enreg[X] addr-exposed "field V22._00 (fldOffset=0x0)" P-DEP
+; V120 tmp118 [V120 ] ( 2, 3 ) long -> [rbp-0x48] do-not-enreg[X] addr-exposed "field V24._00 (fldOffset=0x0)" P-DEP
+; V121 tmp119 [V121 ] ( 2, 3 ) long -> [rbp-0x50] do-not-enreg[X] addr-exposed "field V25._00 (fldOffset=0x0)" P-DEP
+; V122 tmp120 [V122,T04] ( 2, 2 ) long -> rax "field V33._00 (fldOffset=0x0)" P-INDEP
+; V123 tmp121 [V123,T05] ( 2, 2 ) long -> rcx "field V34._00 (fldOffset=0x0)" P-INDEP
+; V124 tmp122 [V124 ] ( 2, 2 ) long -> [rbp-0x88] do-not-enreg[X] addr-exposed "field V35._00 (fldOffset=0x0)" P-DEP
+; V125 tmp123 [V125 ] ( 2, 3 ) long -> [rbp-0x90] do-not-enreg[X] addr-exposed "field V37._00 (fldOffset=0x0)" P-DEP
+; V126 tmp124 [V126 ] ( 2, 3 ) long -> [rbp-0x98] do-not-enreg[X] addr-exposed "field V38._00 (fldOffset=0x0)" P-DEP
+; V127 tmp125 [V127 ] ( 2, 2 ) long -> [rbp-0xA0] do-not-enreg[X] addr-exposed "field V43._00 (fldOffset=0x0)" P-DEP
+; V128 tmp126 [V128 ] ( 2, 3 ) long -> [rbp-0xA8] do-not-enreg[X] addr-exposed "field V45._00 (fldOffset=0x0)" P-DEP
+; V129 tmp127 [V129 ] ( 2, 3 ) long -> [rbp-0xB0] do-not-enreg[X] addr-exposed "field V46._00 (fldOffset=0x0)" P-DEP
+; V130 tmp128 [V130,T06] ( 2, 2 ) long -> rax "field V59._00 (fldOffset=0x0)" P-INDEP
+; V131 tmp129 [V131,T07] ( 2, 2 ) long -> rcx "field V60._00 (fldOffset=0x0)" P-INDEP
+; V132 tmp130 [V132 ] ( 2, 2 ) long -> [rbp-0xE8] do-not-enreg[X] addr-exposed "field V61._00 (fldOffset=0x0)" P-DEP
+; V133 tmp131 [V133 ] ( 2, 3 ) long -> [rbp-0xF0] do-not-enreg[X] addr-exposed "field V63._00 (fldOffset=0x0)" P-DEP
+; V134 tmp132 [V134 ] ( 2, 3 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "field V64._00 (fldOffset=0x0)" P-DEP
+; V135 tmp133 [V135 ] ( 2, 2 ) long -> [rbp-0x100] do-not-enreg[X] addr-exposed "field V69._00 (fldOffset=0x0)" P-DEP
+; V136 tmp134 [V136 ] ( 2, 3 ) long -> [rbp-0x108] do-not-enreg[X] addr-exposed "field V71._00 (fldOffset=0x0)" P-DEP
+; V137 tmp135 [V137 ] ( 2, 3 ) long -> [rbp-0x110] do-not-enreg[X] addr-exposed "field V72._00 (fldOffset=0x0)" P-DEP
+; V138 tmp136 [V138,T08] ( 2, 2 ) long -> rax "field V80._00 (fldOffset=0x0)" P-INDEP
+; V139 tmp137 [V139,T09] ( 2, 2 ) long -> rcx "field V81._00 (fldOffset=0x0)" P-INDEP
+; V140 tmp138 [V140 ] ( 2, 2 ) long -> [rbp-0x148] do-not-enreg[X] addr-exposed "field V82._00 (fldOffset=0x0)" P-DEP
+; V141 tmp139 [V141 ] ( 2, 3 ) long -> [rbp-0x150] do-not-enreg[X] addr-exposed "field V84._00 (fldOffset=0x0)" P-DEP
+; V142 tmp140 [V142 ] ( 2, 3 ) long -> [rbp-0x158] do-not-enreg[X] addr-exposed "field V85._00 (fldOffset=0x0)" P-DEP
+; V143 tmp141 [V143 ] ( 2, 2 ) long -> [rbp-0x160] do-not-enreg[X] addr-exposed "field V90._00 (fldOffset=0x0)" P-DEP
+; V144 tmp142 [V144 ] ( 2, 3 ) long -> [rbp-0x168] do-not-enreg[X] addr-exposed "field V92._00 (fldOffset=0x0)" P-DEP
+; V145 tmp143 [V145 ] ( 2, 3 ) long -> [rbp-0x170] do-not-enreg[X] addr-exposed "field V93._00 (fldOffset=0x0)" P-DEP
+;* V146 tmp144 [V146 ] ( 0, 0 ) simd32 -> zero-ref "field V100._lower (fldOffset=0x0)" P-INDEP
+;* V147 tmp145 [V147 ] ( 0, 0 ) simd32 -> zero-ref "field V100._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 320
+; Lcl frame size = 384
G_M31589_IG01:
push rbp
- push r15
- push rbx
- sub rsp, 320
- lea rbp, [rsp+0x150]
- ;; size=19 bbWeight=1 PerfScore 3.75
+ sub rsp, 384
+ lea rbp, [rsp+0x180]
+ ;; size=16 bbWeight=1 PerfScore 1.75
G_M31589_IG02:
vmovups ymm0, ymmword ptr [rbp+0x10]
- vmovups ymmword ptr [rbp-0x30], ymm0
vmovups ymm1, ymmword ptr [rbp+0x50]
- vmovups ymmword ptr [rbp-0x50], ymm1
vmovaps ymm2, ymm0
- vmovaps xmmword ptr [rbp-0x60], xmm2
+ vmovaps xmmword ptr [rbp-0x10], xmm2
vmovaps ymm2, ymm1
- vmovaps xmmword ptr [rbp-0x70], xmm2
- mov rsi, qword ptr [rbp-0x60]
- mov rdi, qword ptr [rbp-0x70]
- mov qword ptr [rbp-0x80], rsi
- mov qword ptr [rbp-0x88], rdi
- mov rsi, qword ptr [rbp-0x80]
- imul rsi, qword ptr [rbp-0x88]
- mov qword ptr [rbp-0x78], rsi
- mov rsi, qword ptr [rbp-0x78]
- mov qword ptr [rbp-0x90], rsi
- mov rsi, qword ptr [rbp-0x90]
- xor edi, edi
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov rbx, rax
- mov rdi, qword ptr [rbp-0x58]
- mov rsi, qword ptr [rbp-0x68]
- mov qword ptr [rbp-0xA0], rdi
- mov qword ptr [rbp-0xA8], rsi
- mov rdi, qword ptr [rbp-0xA0]
- mov rsi, qword ptr [rbp-0xA8]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Multiply(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Multiply(long,long):long
- mov qword ptr [rbp-0x98], rax
- mov rsi, qword ptr [rbp-0x98]
- mov qword ptr [rbp-0xB0], rsi
- mov rsi, qword ptr [rbp-0xB0]
- xor edi, edi
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov rsi, rax
- mov rdi, rbx
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov rbx, rax
- vmovups ymm0, ymmword ptr [rbp-0x30]
+ vmovaps xmmword ptr [rbp-0x20], xmm2
+ mov rax, qword ptr [rbp-0x10]
+ mov qword ptr [rbp-0x30], rax
+ mov rax, qword ptr [rbp-0x20]
+ mov qword ptr [rbp-0x38], rax
+ mov rax, qword ptr [rbp-0x30]
+ imul rax, qword ptr [rbp-0x38]
+ mov qword ptr [rbp-0x28], rax
+ mov rax, qword ptr [rbp-0x28]
+ mov rcx, qword ptr [rbp-0x08]
+ mov qword ptr [rbp-0x48], rcx
+ mov rcx, qword ptr [rbp-0x18]
+ mov qword ptr [rbp-0x50], rcx
+ mov rcx, qword ptr [rbp-0x48]
+ imul rcx, qword ptr [rbp-0x50]
+ mov qword ptr [rbp-0x40], rcx
+ mov rcx, qword ptr [rbp-0x40]
+ mov qword ptr [rbp-0x60], rax
+ mov qword ptr [rbp-0x58], rcx
+ vmovaps xmm2, xmmword ptr [rbp-0x60]
vextractf128 xmm0, ymm0, 1
- vmovaps xmmword ptr [rbp-0xC0], xmm0
- vmovups ymm1, ymmword ptr [rbp-0x50]
+ vmovaps xmmword ptr [rbp-0x70], xmm0
vextractf128 xmm0, ymm1, 1
- vmovaps xmmword ptr [rbp-0xD0], xmm0
- mov rdi, qword ptr [rbp-0xC0]
- mov rsi, qword ptr [rbp-0xD0]
- mov qword ptr [rbp-0xE0], rdi
- mov qword ptr [rbp-0xE8], rsi
- mov rdi, qword ptr [rbp-0xE0]
- mov rsi, qword ptr [rbp-0xE8]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Multiply(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Multiply(long,long):long
- mov qword ptr [rbp-0xD8], rax
- mov rsi, qword ptr [rbp-0xD8]
- mov qword ptr [rbp-0xF0], rsi
- mov rsi, qword ptr [rbp-0xF0]
- xor edi, edi
- ;; size=341 bbWeight=1 PerfScore 77.50
-G_M31589_IG03:
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov r15, rax
- mov rdi, qword ptr [rbp-0xB8]
- mov rsi, qword ptr [rbp-0xC8]
- mov qword ptr [rbp-0x100], rdi
- mov qword ptr [rbp-0x108], rsi
- mov rdi, qword ptr [rbp-0x100]
- mov rsi, qword ptr [rbp-0x108]
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Multiply(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Multiply(long,long):long
+ vmovaps xmmword ptr [rbp-0x80], xmm0
+ mov rax, qword ptr [rbp-0x70]
+ mov qword ptr [rbp-0x90], rax
+ mov rax, qword ptr [rbp-0x80]
+ mov qword ptr [rbp-0x98], rax
+ mov rax, qword ptr [rbp-0x90]
+ imul rax, qword ptr [rbp-0x98]
+ mov qword ptr [rbp-0x88], rax
+ mov rax, qword ptr [rbp-0x88]
+ mov rcx, qword ptr [rbp-0x68]
+ mov qword ptr [rbp-0xA8], rcx
+ mov rcx, qword ptr [rbp-0x78]
+ mov qword ptr [rbp-0xB0], rcx
+ mov rcx, qword ptr [rbp-0xA8]
+ imul rcx, qword ptr [rbp-0xB0]
+ mov qword ptr [rbp-0xA0], rcx
+ mov rcx, qword ptr [rbp-0xA0]
+ mov qword ptr [rbp-0xC0], rax
+ mov qword ptr [rbp-0xB8], rcx
+ vinserti128 ymm0, ymm2, xmmword ptr [rbp-0xC0], 1
+ vmovups ymm1, ymmword ptr [rbp+0x30]
+ vmovups ymm2, ymmword ptr [rbp+0x70]
+ vmovaps ymm3, ymm1
+ vmovaps xmmword ptr [rbp-0xD0], xmm3
+ vmovaps ymm3, ymm2
+ vmovaps xmmword ptr [rbp-0xE0], xmm3
+ mov rax, qword ptr [rbp-0xD0]
+ mov qword ptr [rbp-0xF0], rax
+ mov rax, qword ptr [rbp-0xE0]
mov qword ptr [rbp-0xF8], rax
- mov rsi, qword ptr [rbp-0xF8]
- mov qword ptr [rbp-0x110], rsi
- mov rsi, qword ptr [rbp-0x110]
- xor edi, edi
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov rsi, rax
- mov rdi, r15
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov rsi, rax
- mov rdi, rbx
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- mov rbx, rax
- vmovups ymm0, ymmword ptr [rbp+0x30]
- vmovups ymmword ptr [rsp], ymm0
- vmovups ymm0, ymmword ptr [rbp+0x70]
- vmovups ymmword ptr [rsp+0x20], ymm0
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Vector256:Dot[long](System.Runtime.Intrinsics.Vector256`1[long],System.Runtime.Intrinsics.Vector256`1[long]):long
- call [rax]System.Runtime.Intrinsics.Vector256:Dot[long](System.Runtime.Intrinsics.Vector256`1[long],System.Runtime.Intrinsics.Vector256`1[long]):long
- mov rsi, rax
- mov rdi, rbx
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- call [rax]System.Runtime.Intrinsics.Scalar`1[long]:Add(long,long):long
- nop
- ;; size=202 bbWeight=1 PerfScore 45.25
+ mov rax, qword ptr [rbp-0xF0]
+ imul rax, qword ptr [rbp-0xF8]
+ mov qword ptr [rbp-0xE8], rax
+ ;; size=339 bbWeight=1 PerfScore 92.00
+G_M31589_IG03:
+ mov rax, qword ptr [rbp-0xE8]
+ mov rcx, qword ptr [rbp-0xC8]
+ mov qword ptr [rbp-0x108], rcx
+ mov rcx, qword ptr [rbp-0xD8]
+ mov qword ptr [rbp-0x110], rcx
+ mov rcx, qword ptr [rbp-0x108]
+ imul rcx, qword ptr [rbp-0x110]
+ mov qword ptr [rbp-0x100], rcx
+ mov rcx, qword ptr [rbp-0x100]
+ mov qword ptr [rbp-0x120], rax
+ mov qword ptr [rbp-0x118], rcx
+ vmovaps xmm3, xmmword ptr [rbp-0x120]
+ vextractf128 xmm1, ymm1, 1
+ vmovaps xmmword ptr [rbp-0x130], xmm1
+ vextractf128 xmm1, ymm2, 1
+ vmovaps xmmword ptr [rbp-0x140], xmm1
+ mov rax, qword ptr [rbp-0x130]
+ mov qword ptr [rbp-0x150], rax
+ mov rax, qword ptr [rbp-0x140]
+ mov qword ptr [rbp-0x158], rax
+ mov rax, qword ptr [rbp-0x150]
+ imul rax, qword ptr [rbp-0x158]
+ mov qword ptr [rbp-0x148], rax
+ mov rax, qword ptr [rbp-0x148]
+ mov rcx, qword ptr [rbp-0x128]
+ mov qword ptr [rbp-0x168], rcx
+ mov rcx, qword ptr [rbp-0x138]
+ mov qword ptr [rbp-0x170], rcx
+ mov rcx, qword ptr [rbp-0x168]
+ imul rcx, qword ptr [rbp-0x170]
+ mov qword ptr [rbp-0x160], rcx
+ mov rcx, qword ptr [rbp-0x160]
+ mov qword ptr [rbp-0x180], rax
+ mov qword ptr [rbp-0x178], rcx
+ vinserti128 ymm1, ymm3, xmmword ptr [rbp-0x180], 1
+ vmovaps ymm2, ymm0
+ vextracti128 xmm0, ymm0, 1
+ vpaddq xmm0, xmm0, xmm2
+ vpsrldq xmm2, xmm0, 8
+ vpaddq xmm0, xmm2, xmm0
+ vmovd rax, xmm0
+ vmovaps ymm0, ymm1
+ vextracti128 xmm1, ymm1, 1
+ vpaddq xmm0, xmm1, xmm0
+ vpsrldq xmm1, xmm0, 8
+ vpaddq xmm0, xmm1, xmm0
+ vmovd rcx, xmm0
+ add rax, rcx
+ ;; size=311 bbWeight=1 PerfScore 63.08
G_M31589_IG04:
vzeroupper
- add rsp, 320
- pop rbx
- pop r15
+ add rsp, 384
pop rbp
ret
- ;; size=15 bbWeight=1 PerfScore 3.75
+ ;; size=12 bbWeight=1 PerfScore 2.75
-; Total bytes of code 577, prolog size 19, PerfScore 130.25, instruction count 110, allocated bytes for code 577 (MethodHash=a646849a) for method System.Runtime.Intrinsics.Vector512`1[long]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Dot(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):long (FullOpts)
+; Total bytes of code 678, prolog size 16, PerfScore 159.58, instruction count 116, allocated bytes for code 678 (MethodHash=a646849a) for method System.Runtime.Intrinsics.Vector512`1[long]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector512<T>,T>.Dot(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):long (FullOpts)87 (26.44 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 16 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 33 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V05 loc2 [V05 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V06 loc3 [V06 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;# V07 OutArgs [V07 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V08 tmp1 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V09 tmp2 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V10 tmp3 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V11 tmp4 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V12 tmp5 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V13 tmp6 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V14 tmp7 [V14 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V15 tmp8 [V15 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V16 tmp9 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V17 tmp10 [V17 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V18 tmp11 [V18 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V19 tmp12 [V19 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V20 tmp13 [V20,T01] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V21 tmp14 [V21,T02] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V22 tmp15 [V22 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V23 tmp16 [V23 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V24 tmp17 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V25 tmp18 [V25,T03] ( 4, 8 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V26 tmp19 [V26,T04] ( 4, 8 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V27 tmp20 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V28 tmp21 [V28,T09] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V29 tmp22 [V29,T10] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V30 tmp23 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V31 tmp24 [V31 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V33 tmp26 [V33 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V34 tmp27 [V34,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V35 tmp28 [V35,T12] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V36 tmp29 [V36 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V37 tmp30 [V37,T21] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V38 tmp31 [V38,T22] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V39 tmp32 [V39 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V40 tmp33 [V40,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V41 tmp34 [V41,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V42 tmp35 [V42 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V43 tmp36 [V43,T23] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V44 tmp37 [V44,T24] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V45 tmp38 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V46 tmp39 [V46,T25] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V47 tmp40 [V47,T26] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V48 tmp41 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V49 tmp42 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V50 tmp43 [V50,T15] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V51 tmp44 [V51,T16] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V19 tmp12 [V19 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V20 tmp13 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V21 tmp14 [V21,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V22 tmp15 [V22,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V23 tmp16 [V23 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V24 tmp17 [V24 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V25 tmp18 [V25 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V26 tmp19 [V26 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V27 tmp20 [V27,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V28 tmp21 [V28,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V30 tmp23 [V30,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V31 tmp24 [V31,T10] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V33 tmp26 [V33 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V34 tmp27 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V36 tmp29 [V36,T11] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V37 tmp30 [V37,T12] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V38 tmp31 [V38 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V39 tmp32 [V39 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V40 tmp33 [V40 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V41 tmp34 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V42 tmp35 [V42,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V43 tmp36 [V43,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V44 tmp37 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V45 tmp38 [V45,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V46 tmp39 [V46,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V47 tmp40 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V48 tmp41 [V48,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V49 tmp42 [V49,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V50 tmp43 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V51 tmp44 [V51,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V52 tmp45 [V52,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
;* V53 tmp46 [V53 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V54 tmp47 [V54,T17] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V55 tmp48 [V55,T18] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V56 tmp49 [V56 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V57 tmp50 [V57,T27] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V58 tmp51 [V58,T28] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V54 tmp47 [V54,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V55 tmp48 [V55,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V56 tmp49 [V56 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V57 tmp50 [V57 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V58 tmp51 [V58 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V59 tmp52 [V59 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V60 tmp53 [V60,T29] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V61 tmp54 [V61,T30] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V62 tmp55 [V62,T05] ( 6, 6 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V63 tmp56 [V63,T06] ( 6, 6 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V64 tmp57 [V64,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V65 tmp58 [V65,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp59 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp60 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp61 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp62 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp63 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp64 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp65 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp66 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp67 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp68 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp69 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp70 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp71 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp72 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp73 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp74 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp75 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp76 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp77 [V84,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp78 [V85,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp79 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp80 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp81 [V88,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp82 [V89,T32] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp83 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp84 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp85 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp86 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp87 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp88 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp89 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp90 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp91 [V98 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp92 [V99 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp93 [V100,T37] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp94 [V101,T38] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp95 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp96 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp97 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp98 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp99 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp100 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp101 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp102 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp103 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp104 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp105 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp106 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp107 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp108 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp109 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp110 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp111 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp112 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp113 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp114 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp115 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp116 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
-; V124 tmp117 [V124,T33] ( 2, 2 ) simd32 -> mm0 single-def "field V59._lower (fldOffset=0x0)" P-INDEP
-; V125 tmp118 [V125,T34] ( 2, 2 ) simd32 -> mm1 single-def "field V59._upper (fldOffset=0x20)" P-INDEP
-; V126 cse0 [V126,T19] ( 4, 4 ) simd32 -> mm4 "CSE #01: moderate"
-; V127 cse1 [V127,T20] ( 4, 4 ) simd32 -> mm6 "CSE #02: moderate"
+; V60 tmp53 [V60,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V61 tmp54 [V61,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V62 tmp55 [V62 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V63 tmp56 [V63,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V64 tmp57 [V64,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V65 tmp58 [V65 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V66 tmp59 [V66,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V67 tmp60 [V67,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V68 tmp61 [V68 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V69 tmp62 [V69,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V70 tmp63 [V70,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V71 tmp64 [V71 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V72 tmp65 [V72 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V73 tmp66 [V73 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V74 tmp67 [V74 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V75 tmp68 [V75,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V76 tmp69 [V76,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V77 tmp70 [V77 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V78 tmp71 [V78,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V79 tmp72 [V79,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V80 tmp73 [V80 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V81 tmp74 [V81,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V82 tmp75 [V82,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V83 tmp76 [V83 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V84 tmp77 [V84,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V85 tmp78 [V85,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V86 tmp79 [V86 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V87 tmp80 [V87 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V88 tmp81 [V88,T15] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V89 tmp82 [V89,T16] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V90 tmp83 [V90 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V91 tmp84 [V91 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V92 tmp85 [V92,T17] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V93 tmp86 [V93,T18] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V94 tmp87 [V94 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V95 tmp88 [V95 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V96 tmp89 [V96 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V97 tmp90 [V97 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V98 tmp91 [V98,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V99 tmp92 [V99,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V100 tmp93 [V100 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V101 tmp94 [V101,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V102 tmp95 [V102,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V103 tmp96 [V103 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V104 tmp97 [V104,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V105 tmp98 [V105,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V106 tmp99 [V106 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V107 tmp100 [V107,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V108 tmp101 [V108,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V109 tmp102 [V109 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V110 tmp103 [V110 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V111 tmp104 [V111 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V112 tmp105 [V112 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V113 tmp106 [V113,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V114 tmp107 [V114,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V115 tmp108 [V115 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V116 tmp109 [V116,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V117 tmp110 [V117,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V118 tmp111 [V118 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V119 tmp112 [V119,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V120 tmp113 [V120,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V121 tmp114 [V121 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V122 tmp115 [V122,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V123 tmp116 [V123,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V124 tmp117 [V124,T05] ( 7, 7 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V125 tmp118 [V125,T06] ( 7, 7 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V126 tmp119 [V126,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V127 tmp120 [V127,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp121 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp122 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp123 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp124 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp125 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp126 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp127 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp128 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp129 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp130 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp131 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp132 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp133 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp134 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp135 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp136 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp137 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp138 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp139 [V146,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp140 [V147,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp141 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp142 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp143 [V150,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp144 [V151,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp145 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp146 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp147 [V154 ] ( 0, 0 ) simd32 -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp148 [V155 ] ( 0, 0 ) simd32 -> zero-ref "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp149 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp150 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp151 [V158 ] ( 0, 0 ) simd32 -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp152 [V159 ] ( 0, 0 ) simd32 -> zero-ref "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp153 [V160 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp154 [V161 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp155 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp156 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp157 [V164 ] ( 0, 0 ) simd32 -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp158 [V165 ] ( 0, 0 ) simd32 -> zero-ref "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp159 [V166,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+; V167 tmp160 [V167,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp161 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp162 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp163 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp164 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp165 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp166 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp167 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp168 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp169 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp170 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp171 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp172 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp173 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp174 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp175 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp176 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp177 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp178 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp179 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp180 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp181 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp182 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp183 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp184 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp185 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp186 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp187 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp188 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp189 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V62._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp190 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V62._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp191 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V65._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp192 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V65._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp193 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp194 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp195 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp196 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp197 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp198 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp199 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp200 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp201 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp202 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp203 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V77._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp204 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V77._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp205 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V80._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp206 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V80._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp207 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp208 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp209 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp210 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp211 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp212 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp213 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp214 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp215 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp216 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp217 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp218 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp219 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp220 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp221 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp222 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp223 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp224 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp225 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp226 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp227 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp228 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp229 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp230 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp231 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp232 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp233 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp234 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp235 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp236 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp237 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp238 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp239 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V115._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp240 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V115._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp241 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V118._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp242 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V118._upper (fldOffset=0x20)" P-INDEP
+; V250 tmp243 [V250,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V121._lower (fldOffset=0x0)" P-INDEP
+; V251 tmp244 [V251,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V121._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M46802_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M46802_IG02:
vxorps ymm4, ymm4, ymm4
vpcmpgtq ymm4, ymm4, ymm0
vxorps ymm5, ymm5, ymm5
vpsubq ymm5, ymm5, ymm0
- vpand ymm5, ymm5, ymm4
- vpandn ymm6, ymm4, ymm0
- vpor ymm5, ymm6, ymm5
+ vpblendvb ymm4, ymm0, ymm5, ymm4
+ vxorps ymm5, ymm5, ymm5
+ vpcmpgtq ymm5, ymm5, ymm1
+ vxorps ymm6, ymm6, ymm6
+ vpsubq ymm6, ymm6, ymm1
+ vpblendvb ymm5, ymm1, ymm6, ymm5
vxorps ymm6, ymm6, ymm6
- vpcmpgtq ymm6, ymm6, ymm1
+ vpcmpgtq ymm6, ymm6, ymm2
vxorps ymm7, ymm7, ymm7
- vpsubq ymm7, ymm7, ymm1
- vpand ymm7, ymm7, ymm6
- vpandn ymm8, ymm6, ymm1
- vpor ymm7, ymm8, ymm7
+ vpsubq ymm7, ymm7, ymm2
+ vpblendvb ymm6, ymm2, ymm7, ymm6
+ vxorps ymm7, ymm7, ymm7
+ vpcmpgtq ymm7, ymm7, ymm3
vxorps ymm8, ymm8, ymm8
- vpcmpgtq ymm8, ymm8, ymm2
- vxorps ymm9, ymm9, ymm9
- vpsubq ymm9, ymm9, ymm2
- vpblendvb ymm8, ymm2, ymm9, ymm8
- vxorps ymm9, ymm9, ymm9
- vpcmpgtq ymm9, ymm9, ymm3
+ vpsubq ymm8, ymm8, ymm3
+ vpblendvb ymm7, ymm3, ymm8, ymm7
+ vpcmpeqq ymm8, ymm4, ymm6
+ vpcmpeqq ymm9, ymm5, ymm7
vxorps ymm10, ymm10, ymm10
- vpsubq ymm10, ymm10, ymm3
- vpblendvb ymm9, ymm3, ymm10, ymm9
- vpcmpeqq ymm10, ymm5, ymm8
- vpcmpeqq ymm11, ymm7, ymm9
- vpand ymm12, ymm2, ymm4
- vpandn ymm4, ymm4, ymm0
- vpor ymm4, ymm4, ymm12
- vpand ymm12, ymm3, ymm6
- vpandn ymm6, ymm6, ymm1
- vpor ymm6, ymm6, ymm12
- vpcmpgtq ymm12, ymm5, ymm8
- vpcmpgtq ymm13, ymm7, ymm9
+ vpcmpgtq ymm11, ymm10, ymm0
+ vpcmpgtq ymm10, ymm10, ymm1
+ vpand ymm12, ymm11, ymm2
+ vpand ymm13, ymm10, ymm3
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm0, ymm11
+ vpand ymm10, ymm1, ymm10
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
+ vpcmpgtq ymm12, ymm4, ymm6
+ vpcmpgtq ymm13, ymm5, ymm7
vpand ymm14, ymm0, ymm12
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm1, ymm13
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
- vpand ymm4, ymm10, ymm4
- vpandn ymm10, ymm10, ymm12
- vpor ymm4, ymm10, ymm4
- vpand ymm6, ymm11, ymm6
- vpandn ymm10, ymm11, ymm13
- vpor ymm6, ymm10, ymm6
+ vpand ymm15, ymm1, ymm13
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm2, ymm10
+ vpand ymm12, ymm3, ymm12
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
+ vpand ymm11, ymm8, ymm11
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm4, ymm10, ymm4
vpcmpgtq ymm5, ymm10, ymm5
- vpcmpgtq ymm7, ymm10, ymm7
- vxorps ymm10, ymm10, ymm10
- vpcmpgtq ymm8, ymm10, ymm8
- vpcmpgtq ymm9, ymm10, ymm9
- vpand ymm2, ymm2, ymm8
- vpandn ymm4, ymm8, ymm4
- vpor ymm2, ymm4, ymm2
- vpand ymm3, ymm3, ymm9
- vpandn ymm4, ymm9, ymm6
- vpor ymm3, ymm4, ymm3
- vpand ymm0, ymm0, ymm5
- ;; size=268 bbWeight=1 PerfScore 38.00
+ ;; size=286 bbWeight=1 PerfScore 42.33
G_M46802_IG03:
- vpandn ymm2, ymm5, ymm2
- vpor ymm0, ymm2, ymm0
- vpand ymm1, ymm1, ymm7
- vpandn ymm2, ymm7, ymm3
- vpor ymm1, ymm2, ymm1
+ vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm6, ymm10, ymm6
+ vpcmpgtq ymm7, ymm10, ymm7
+ vpand ymm2, ymm6, ymm2
+ vpand ymm3, ymm7, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
+ vpand ymm0, ymm0, ymm4
+ vpand ymm1, ymm1, ymm5
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=32 bbWeight=1 PerfScore 5.92
+ ;; size=91 bbWeight=1 PerfScore 13.92
G_M46802_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 329, prolog size 4, PerfScore 63.67, instruction count 76, allocated bytes for code 329 (MethodHash=7fae492d) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
+; Total bytes of code 416, prolog size 10, PerfScore 76.75, instruction count 92, allocated bytes for code 416 (MethodHash=7fae492d) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)87 (32.95 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 52 single block inlinees; 18 inlinees without PGO data
+; 0 inlinees with PGO data; 115 single block inlinees; 35 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[double]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[double]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[double]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[double]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
-;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V16 tmp11 [V16,T05] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V17 tmp12 [V17,T06] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V19 tmp14 [V19,T07] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V20 tmp15 [V20,T08] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V21 tmp16 [V21 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V22 tmp17 [V22,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V23 tmp18 [V23,T10] ( 3, 6 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V24 tmp19 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V25 tmp20 [V25,T11] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V26 tmp21 [V26,T12] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V27 tmp22 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V28 tmp23 [V28,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V29 tmp24 [V29,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V36 tmp31 [V36,T15] ( 3, 6 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V37 tmp32 [V37,T16] ( 3, 6 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V39 tmp34 [V39,T20] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V40 tmp35 [V40,T21] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V42 tmp37 [V42,T17] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V43 tmp38 [V43,T18] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V44 tmp39 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V45 tmp40 [V45,T22] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V46 tmp41 [V46,T23] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V48 tmp43 [V48,T24] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V49 tmp44 [V49,T25] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V51 tmp46 [V51,T26] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V52 tmp47 [V52,T27] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V53 tmp48 [V53 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V54 tmp49 [V54,T28] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V55 tmp50 [V55,T29] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V56 tmp51 [V56,T01] ( 7, 7 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V57 tmp52 [V57,T02] ( 7, 7 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V58 tmp53 [V58,T03] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V59 tmp54 [V59,T04] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V60 tmp55 [V60 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V61 tmp56 [V61 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V62 tmp57 [V62 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V63 tmp58 [V63 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp59 [V64 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp60 [V65 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp61 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp62 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V85 tmp80 [V85 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
-;* V89 tmp84 [V89 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp88 [V93 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96,T33] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-; V97 tmp92 [V97,T30] ( 3, 3 ) simd32 -> mm14 single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref "field V33._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref "field V33._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp98 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-; V114 tmp109 [V114,T31] ( 2, 2 ) simd32 -> mm0 single-def "field V53._lower (fldOffset=0x0)" P-INDEP
-; V115 tmp110 [V115,T32] ( 2, 2 ) simd32 -> mm1 single-def "field V53._upper (fldOffset=0x20)" P-INDEP
-; V116 cse0 [V116,T19] ( 5, 5 ) simd32 -> mm4 "CSE #01: moderate"
+;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V17 tmp12 [V17,T05] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V18 tmp13 [V18,T06] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V20 tmp15 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V21 tmp16 [V21,T07] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V22 tmp17 [V22,T08] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V23 tmp18 [V23 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V24 tmp19 [V24,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V25 tmp20 [V25,T10] ( 3, 6 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V26 tmp21 [V26 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V27 tmp22 [V27,T11] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V28 tmp23 [V28,T12] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V30 tmp25 [V30,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V31 tmp26 [V31,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V38 tmp33 [V38,T15] ( 3, 6 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V39 tmp34 [V39,T16] ( 3, 6 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V44 tmp39 [V44,T20] ( 2, 4 ) simd32 -> [rbp-0x50] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V45 tmp40 [V45,T21] ( 2, 4 ) simd32 -> [rbp-0x70] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V47 tmp42 [V47,T22] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V48 tmp43 [V48,T23] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V49 tmp44 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V50 tmp45 [V50,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V51 tmp46 [V51,T25] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V52 tmp47 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V53 tmp48 [V53,T26] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V54 tmp49 [V54,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V56 tmp51 [V56,T17] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V57 tmp52 [V57,T18] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V58 tmp53 [V58 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V59 tmp54 [V59 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V61 tmp56 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V62 tmp57 [V62,T28] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V63 tmp58 [V63,T29] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V64 tmp59 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V65 tmp60 [V65,T30] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V66 tmp61 [V66,T31] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V67 tmp62 [V67 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V68 tmp63 [V68,T32] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V69 tmp64 [V69,T33] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V71 tmp66 [V71,T34] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V72 tmp67 [V72,T35] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V73 tmp68 [V73 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V74 tmp69 [V74 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V76 tmp71 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V77 tmp72 [V77,T36] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V78 tmp73 [V78,T37] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V79 tmp74 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V80 tmp75 [V80,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V81 tmp76 [V81,T39] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V82 tmp77 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V83 tmp78 [V83,T40] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V84 tmp79 [V84,T41] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V86 tmp81 [V86,T42] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V87 tmp82 [V87,T43] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V90 tmp85 [V90 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V91 tmp86 [V91 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V92 tmp87 [V92,T44] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V93 tmp88 [V93,T45] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V94 tmp89 [V94 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V95 tmp90 [V95,T46] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V96 tmp91 [V96,T47] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V97 tmp92 [V97 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V98 tmp93 [V98,T48] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V99 tmp94 [V99,T49] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V100 tmp95 [V100 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V101 tmp96 [V101,T50] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V102 tmp97 [V102,T51] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V103 tmp98 [V103 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V104 tmp99 [V104 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V105 tmp100 [V105 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V106 tmp101 [V106 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V107 tmp102 [V107,T52] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V108 tmp103 [V108,T53] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V109 tmp104 [V109 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V110 tmp105 [V110,T54] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V111 tmp106 [V111,T55] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V112 tmp107 [V112 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V113 tmp108 [V113,T56] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V114 tmp109 [V114,T57] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V115 tmp110 [V115 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V116 tmp111 [V116,T58] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V117 tmp112 [V117,T59] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V118 tmp113 [V118,T01] ( 7, 7 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V119 tmp114 [V119,T02] ( 7, 7 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V120 tmp115 [V120,T03] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V121 tmp116 [V121,T04] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V147 tmp142 [V147 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V151 tmp146 [V151 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp150 [V155 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162,T63] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+; V163 tmp158 [V163,T60] ( 3, 3 ) simd32 -> mm14 single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp164 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp168 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._upper (fldOffset=0x20)" P-INDEP
+; V240 tmp235 [V240,T61] ( 2, 2 ) simd32 -> mm0 single-def "field V115._lower (fldOffset=0x0)" P-INDEP
+; V241 tmp236 [V241,T62] ( 2, 2 ) simd32 -> mm1 single-def "field V115._upper (fldOffset=0x20)" P-INDEP
+; V242 cse0 [V242,T19] ( 5, 5 ) simd32 -> mm4 "CSE #01: conservative"
;
-; Lcl frame size = 48
+; Lcl frame size = 112
G_M18520_IG01:
push rbp
- sub rsp, 48
- lea rbp, [rsp+0x30]
+ sub rsp, 112
+ lea rbp, [rsp+0x70]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
;; size=30 bbWeight=1 PerfScore 17.75
G_M18520_IG02:
vmovups ymm4, ymmword ptr [reloc @RWD00]
vandnpd ymm5, ymm4, ymm0
vandnpd ymm6, ymm4, ymm1
vandnpd ymm7, ymm4, ymm2
vandnpd ymm4, ymm4, ymm3
vcmppd ymm8, ymm0, ymm0, 0
vcmppd ymm9, ymm1, ymm1, 0
vmovups ymmword ptr [rbp-0x30], ymm9
vcmppd ymm10, ymm2, ymm2, 0
vcmppd ymm11, ymm3, ymm3, 0
vcmppd ymm12, ymm5, ymm7, 0
vcmppd ymm13, ymm6, ymm4, 0
vxorps ymm14, ymm14, ymm14
vpcmpgtq ymm15, ymm14, ymm0
vpcmpgtq ymm14, ymm14, ymm1
vandpd ymm9, ymm15, ymm2
- vandnpd ymm15, ymm15, ymm0
+ vmovups ymmword ptr [rbp-0x50], ymm9
+ vandpd ymm9, ymm14, ymm3
+ vmovups ymmword ptr [rbp-0x70], ymm9
+ vpcmpeqd ymm9, ymm9, ymm9
+ vxorpd ymm9, ymm9, ymm15
+ vpcmpeqd ymm15, ymm15, ymm15
+ vxorpd ymm14, ymm15, ymm14
+ vandpd ymm9, ymm0, ymm9
+ vandpd ymm14, ymm1, ymm14
+ vmovups ymm15, ymmword ptr [rbp-0x50]
vorpd ymm9, ymm15, ymm9
- vandpd ymm15, ymm14, ymm3
- vandnpd ymm14, ymm14, ymm1
- vorpd ymm14, ymm14, ymm15
+ vmovups ymm15, ymmword ptr [rbp-0x70]
+ vorpd ymm14, ymm15, ymm14
vcmppd ymm5, ymm5, ymm7, 14
vcmppd ymm4, ymm6, ymm4, 14
vandpd ymm6, ymm0, ymm5
- vandnpd ymm5, ymm5, ymm2
- vorpd ymm5, ymm5, ymm6
- vandpd ymm6, ymm1, ymm4
- vandnpd ymm4, ymm4, ymm3
- vorpd ymm4, ymm4, ymm6
+ vandpd ymm7, ymm1, ymm4
+ vpcmpeqd ymm15, ymm15, ymm15
+ vxorpd ymm5, ymm15, ymm5
+ vxorpd ymm4, ymm15, ymm4
+ vandpd ymm5, ymm2, ymm5
+ vandpd ymm4, ymm3, ymm4
+ vorpd ymm5, ymm6, ymm5
+ vorpd ymm4, ymm7, ymm4
vandpd ymm6, ymm12, ymm9
- vandnpd ymm5, ymm12, ymm5
- vorpd ymm5, ymm5, ymm6
- vandpd ymm6, ymm13, ymm14
- vandnpd ymm4, ymm13, ymm4
- vorpd ymm4, ymm4, ymm6
+ vandpd ymm7, ymm13, ymm14
+ vxorpd ymm9, ymm15, ymm12
+ vxorpd ymm12, ymm15, ymm13
+ vandpd ymm5, ymm5, ymm9
+ vandpd ymm4, ymm4, ymm12
+ vorpd ymm5, ymm6, ymm5
+ vorpd ymm4, ymm7, ymm4
vandpd ymm5, ymm10, ymm5
- vandnpd ymm2, ymm10, ymm2
- vorpd ymm2, ymm2, ymm5
vandpd ymm4, ymm11, ymm4
- vandnpd ymm3, ymm11, ymm3
- vorpd ymm3, ymm3, ymm4
+ vxorpd ymm6, ymm15, ymm10
+ vxorpd ymm7, ymm15, ymm11
+ vandpd ymm2, ymm2, ymm6
+ vandpd ymm3, ymm3, ymm7
+ vorpd ymm2, ymm5, ymm2
+ vorpd ymm3, ymm4, ymm3
vandpd ymm2, ymm8, ymm2
- vandnpd ymm0, ymm8, ymm0
- vorpd ymm0, ymm0, ymm2
vmovups ymm9, ymmword ptr [rbp-0x30]
- vandpd ymm2, ymm9, ymm3
- vandnpd ymm1, ymm9, ymm1
- vorpd ymm1, ymm1, ymm2
+ vandpd ymm3, ymm9, ymm3
+ ;; size=274 bbWeight=1 PerfScore 61.50
+G_M18520_IG03:
+ vxorpd ymm4, ymm15, ymm8
+ vxorpd ymm5, ymm15, ymm9
+ vandpd ymm0, ymm0, ymm4
+ vandpd ymm1, ymm1, ymm5
+ vorpd ymm0, ymm2, ymm0
+ vorpd ymm1, ymm3, ymm1
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=225 bbWeight=1 PerfScore 52.92
-G_M18520_IG03:
+ ;; size=38 bbWeight=1 PerfScore 6.25
+G_M18520_IG04:
vzeroupper
- add rsp, 48
+ add rsp, 112
pop rbp
ret
;; size=9 bbWeight=1 PerfScore 2.75
RWD00 dq 8000000000000000h, 8000000000000000h, 8000000000000000h, 8000000000000000h
-; Total bytes of code 264, prolog size 10, PerfScore 73.42, instruction count 62, allocated bytes for code 264 (MethodHash=3413b7a7) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double] (FullOpts)
+; Total bytes of code 351, prolog size 10, PerfScore 88.25, instruction count 79, allocated bytes for code 351 (MethodHash=3413b7a7) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double] (FullOpts)87 (26.44 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 17 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 34 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V17 tmp12 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V19 tmp14 [V19 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V20 tmp15 [V20 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V21 tmp16 [V21 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V22 tmp17 [V22,T01] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V23 tmp18 [V23,T02] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V24 tmp19 [V24 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V25 tmp20 [V25 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V26 tmp21 [V26 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V27 tmp22 [V27,T03] ( 4, 8 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V28 tmp23 [V28,T04] ( 4, 8 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V30 tmp25 [V30,T09] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V31 tmp26 [V31,T10] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V36 tmp31 [V36,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V37 tmp32 [V37,T12] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V39 tmp34 [V39,T21] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V40 tmp35 [V40,T22] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V42 tmp37 [V42,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V43 tmp38 [V43,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V44 tmp39 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V45 tmp40 [V45,T23] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V46 tmp41 [V46,T24] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V48 tmp43 [V48,T25] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V49 tmp44 [V49,T26] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V51 tmp46 [V51 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V52 tmp47 [V52,T15] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V53 tmp48 [V53,T16] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V21 tmp16 [V21 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V22 tmp17 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V23 tmp18 [V23,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V24 tmp19 [V24,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V25 tmp20 [V25 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V26 tmp21 [V26 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V27 tmp22 [V27 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V28 tmp23 [V28 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V29 tmp24 [V29,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V30 tmp25 [V30,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V32 tmp27 [V32,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V33 tmp28 [V33,T10] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V38 tmp33 [V38,T11] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V39 tmp34 [V39,T12] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V44 tmp39 [V44,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V45 tmp40 [V45,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V47 tmp42 [V47,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V48 tmp43 [V48,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V49 tmp44 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V50 tmp45 [V50,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V51 tmp46 [V51,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V52 tmp47 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V53 tmp48 [V53,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V54 tmp49 [V54,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V56 tmp51 [V56,T17] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V57 tmp52 [V57,T18] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V58 tmp53 [V58 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V59 tmp54 [V59,T27] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V60 tmp55 [V60,T28] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V56 tmp51 [V56,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V57 tmp52 [V57,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V58 tmp53 [V58 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V59 tmp54 [V59 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V61 tmp56 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V62 tmp57 [V62,T29] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V63 tmp58 [V63,T30] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V64 tmp59 [V64,T05] ( 6, 6 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V65 tmp60 [V65,T06] ( 6, 6 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V66 tmp61 [V66,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V67 tmp62 [V67,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V85 tmp80 [V85 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp84 [V89,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-; V93 tmp88 [V93,T32] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp92 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp98 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106,T37] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107,T38] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp109 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp110 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp111 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp112 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp113 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp114 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp115 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp116 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
-;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
-;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
-;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
-;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
-;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
-;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
-; V130 tmp125 [V130,T33] ( 2, 2 ) simd32 -> mm0 single-def "field V61._lower (fldOffset=0x0)" P-INDEP
-; V131 tmp126 [V131,T34] ( 2, 2 ) simd32 -> mm1 single-def "field V61._upper (fldOffset=0x20)" P-INDEP
-; V132 cse0 [V132,T19] ( 4, 4 ) simd32 -> mm4 "CSE #01: moderate"
-; V133 cse1 [V133,T20] ( 4, 4 ) simd32 -> mm6 "CSE #02: moderate"
+; V62 tmp57 [V62,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V63 tmp58 [V63,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V64 tmp59 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V65 tmp60 [V65,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V66 tmp61 [V66,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V67 tmp62 [V67 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V68 tmp63 [V68,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V69 tmp64 [V69,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V71 tmp66 [V71,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V72 tmp67 [V72,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V73 tmp68 [V73 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V74 tmp69 [V74 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V76 tmp71 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V77 tmp72 [V77,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V78 tmp73 [V78,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V79 tmp74 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V80 tmp75 [V80,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V81 tmp76 [V81,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V82 tmp77 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V83 tmp78 [V83,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V84 tmp79 [V84,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V86 tmp81 [V86,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V87 tmp82 [V87,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V90 tmp85 [V90,T15] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V91 tmp86 [V91,T16] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V92 tmp87 [V92 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V93 tmp88 [V93 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V94 tmp89 [V94,T17] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V95 tmp90 [V95,T18] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V96 tmp91 [V96 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V97 tmp92 [V97 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V98 tmp93 [V98 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V99 tmp94 [V99 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V100 tmp95 [V100,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V101 tmp96 [V101,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V102 tmp97 [V102 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V103 tmp98 [V103,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V104 tmp99 [V104,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V105 tmp100 [V105 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V106 tmp101 [V106,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V107 tmp102 [V107,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V108 tmp103 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V109 tmp104 [V109,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V110 tmp105 [V110,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V111 tmp106 [V111 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V112 tmp107 [V112 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V113 tmp108 [V113 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V114 tmp109 [V114 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V115 tmp110 [V115,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V116 tmp111 [V116,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V117 tmp112 [V117 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V118 tmp113 [V118,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V119 tmp114 [V119,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V120 tmp115 [V120 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V121 tmp116 [V121,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V122 tmp117 [V122,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V123 tmp118 [V123 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V124 tmp119 [V124,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V125 tmp120 [V125,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V126 tmp121 [V126,T05] ( 7, 7 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V127 tmp122 [V127,T06] ( 7, 7 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V128 tmp123 [V128,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V129 tmp124 [V129,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V147 tmp142 [V147 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp146 [V151,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+; V155 tmp150 [V155,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp158 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref "field V25._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp164 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+; V173 tmp168 [V173,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp235 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp236 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp237 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp238 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp239 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp240 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp241 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp242 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp243 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp244 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._upper (fldOffset=0x20)" P-INDEP
+;* V250 tmp245 [V250 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._lower (fldOffset=0x0)" P-INDEP
+;* V251 tmp246 [V251 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._upper (fldOffset=0x20)" P-INDEP
+;* V252 tmp247 [V252 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V117._lower (fldOffset=0x0)" P-INDEP
+;* V253 tmp248 [V253 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V117._upper (fldOffset=0x20)" P-INDEP
+;* V254 tmp249 [V254 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V120._lower (fldOffset=0x0)" P-INDEP
+;* V255 tmp250 [V255 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V120._upper (fldOffset=0x20)" P-INDEP
+; V256 tmp251 [V256,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V123._lower (fldOffset=0x0)" P-INDEP
+; V257 tmp252 [V257,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V123._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M18264_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M18264_IG02:
vxorps ymm4, ymm4, ymm4
vpcmpgtq ymm4, ymm4, ymm0
vxorps ymm5, ymm5, ymm5
vpsubq ymm5, ymm5, ymm0
- vpand ymm5, ymm5, ymm4
- vpandn ymm6, ymm4, ymm0
- vpor ymm5, ymm6, ymm5
+ vpblendvb ymm4, ymm0, ymm5, ymm4
+ vxorps ymm5, ymm5, ymm5
+ vpcmpgtq ymm5, ymm5, ymm1
+ vxorps ymm6, ymm6, ymm6
+ vpsubq ymm6, ymm6, ymm1
+ vpblendvb ymm5, ymm1, ymm6, ymm5
vxorps ymm6, ymm6, ymm6
- vpcmpgtq ymm6, ymm6, ymm1
+ vpcmpgtq ymm6, ymm6, ymm2
vxorps ymm7, ymm7, ymm7
- vpsubq ymm7, ymm7, ymm1
- vpand ymm7, ymm7, ymm6
- vpandn ymm8, ymm6, ymm1
- vpor ymm7, ymm8, ymm7
+ vpsubq ymm7, ymm7, ymm2
+ vpblendvb ymm6, ymm2, ymm7, ymm6
+ vxorps ymm7, ymm7, ymm7
+ vpcmpgtq ymm7, ymm7, ymm3
vxorps ymm8, ymm8, ymm8
- vpcmpgtq ymm8, ymm8, ymm2
- vxorps ymm9, ymm9, ymm9
- vpsubq ymm9, ymm9, ymm2
- vpblendvb ymm8, ymm2, ymm9, ymm8
- vxorps ymm9, ymm9, ymm9
- vpcmpgtq ymm9, ymm9, ymm3
+ vpsubq ymm8, ymm8, ymm3
+ vpblendvb ymm7, ymm3, ymm8, ymm7
+ vpcmpeqq ymm8, ymm4, ymm6
+ vpcmpeqq ymm9, ymm5, ymm7
vxorps ymm10, ymm10, ymm10
- vpsubq ymm10, ymm10, ymm3
- vpblendvb ymm9, ymm3, ymm10, ymm9
- vpcmpeqq ymm10, ymm5, ymm8
- vpcmpeqq ymm11, ymm7, ymm9
- vpand ymm12, ymm2, ymm4
- vpandn ymm4, ymm4, ymm0
- vpor ymm4, ymm4, ymm12
- vpand ymm12, ymm3, ymm6
- vpandn ymm6, ymm6, ymm1
- vpor ymm6, ymm6, ymm12
- vpcmpgtq ymm12, ymm5, ymm8
- vpcmpgtq ymm13, ymm7, ymm9
+ vpcmpgtq ymm11, ymm10, ymm0
+ vpcmpgtq ymm10, ymm10, ymm1
+ vpand ymm12, ymm11, ymm2
+ vpand ymm13, ymm10, ymm3
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm0, ymm11
+ vpand ymm10, ymm1, ymm10
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
+ vpcmpgtq ymm12, ymm4, ymm6
+ vpcmpgtq ymm13, ymm5, ymm7
vpand ymm14, ymm0, ymm12
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm1, ymm13
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
- vpand ymm4, ymm10, ymm4
- vpandn ymm10, ymm10, ymm12
- vpor ymm4, ymm10, ymm4
- vpand ymm6, ymm11, ymm6
- vpandn ymm10, ymm11, ymm13
- vpor ymm6, ymm10, ymm6
+ vpand ymm15, ymm1, ymm13
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm2, ymm10
+ vpand ymm12, ymm3, ymm12
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
+ vpand ymm11, ymm8, ymm11
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm4, ymm10, ymm4
vpcmpgtq ymm5, ymm10, ymm5
- vpcmpgtq ymm7, ymm10, ymm7
- vxorps ymm10, ymm10, ymm10
- vpcmpgtq ymm8, ymm10, ymm8
- vpcmpgtq ymm9, ymm10, ymm9
- vpand ymm2, ymm2, ymm8
- vpandn ymm4, ymm8, ymm4
- vpor ymm2, ymm4, ymm2
- vpand ymm3, ymm3, ymm9
- vpandn ymm4, ymm9, ymm6
- vpor ymm3, ymm4, ymm3
- vpand ymm0, ymm0, ymm5
- ;; size=268 bbWeight=1 PerfScore 38.00
+ ;; size=286 bbWeight=1 PerfScore 42.33
G_M18264_IG03:
- vpandn ymm2, ymm5, ymm2
- vpor ymm0, ymm2, ymm0
- vpand ymm1, ymm1, ymm7
- vpandn ymm2, ymm7, ymm3
- vpor ymm1, ymm2, ymm1
+ vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm6, ymm10, ymm6
+ vpcmpgtq ymm7, ymm10, ymm7
+ vpand ymm2, ymm6, ymm2
+ vpand ymm3, ymm7, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
+ vpand ymm0, ymm0, ymm4
+ vpand ymm1, ymm1, ymm5
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=32 bbWeight=1 PerfScore 5.92
+ ;; size=91 bbWeight=1 PerfScore 13.92
G_M18264_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 329, prolog size 4, PerfScore 63.67, instruction count 76, allocated bytes for code 329 (MethodHash=8ba2b8a7) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
+; Total bytes of code 416, prolog size 10, PerfScore 76.75, instruction count 92, allocated bytes for code 416 (MethodHash=8ba2b8a7) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)87 (32.71 % of base) - System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 52 single block inlinees; 18 inlinees without PGO data
+; 0 inlinees with PGO data; 115 single block inlinees; 35 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[double]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[double]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[double]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[double]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
-;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V16 tmp11 [V16,T05] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V17 tmp12 [V17,T06] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V19 tmp14 [V19,T07] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V20 tmp15 [V20,T08] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V21 tmp16 [V21 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V22 tmp17 [V22,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V23 tmp18 [V23,T10] ( 3, 6 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V24 tmp19 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V25 tmp20 [V25,T11] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V26 tmp21 [V26,T12] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V27 tmp22 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V28 tmp23 [V28,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V29 tmp24 [V29,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V36 tmp31 [V36,T15] ( 3, 6 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V37 tmp32 [V37,T16] ( 3, 6 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V39 tmp34 [V39,T20] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V40 tmp35 [V40,T21] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V42 tmp37 [V42,T17] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V43 tmp38 [V43,T18] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V44 tmp39 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V45 tmp40 [V45,T22] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V46 tmp41 [V46,T23] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V48 tmp43 [V48,T24] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V49 tmp44 [V49,T25] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V51 tmp46 [V51,T26] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V52 tmp47 [V52,T27] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-;* V53 tmp48 [V53 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
-; V54 tmp49 [V54,T28] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V55 tmp50 [V55,T29] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
-; V56 tmp51 [V56,T01] ( 7, 7 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V57 tmp52 [V57,T02] ( 7, 7 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V58 tmp53 [V58,T03] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V59 tmp54 [V59,T04] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V60 tmp55 [V60 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V61 tmp56 [V61 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V62 tmp57 [V62 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V63 tmp58 [V63 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp59 [V64 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp60 [V65 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp61 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp62 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V85 tmp80 [V85 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
-;* V89 tmp84 [V89 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp88 [V93 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96,T33] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-; V97 tmp92 [V97,T30] ( 3, 3 ) simd32 -> mm14 single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref "field V33._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref "field V33._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp98 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-; V114 tmp109 [V114,T31] ( 2, 2 ) simd32 -> mm0 single-def "field V53._lower (fldOffset=0x0)" P-INDEP
-; V115 tmp110 [V115,T32] ( 2, 2 ) simd32 -> mm1 single-def "field V53._upper (fldOffset=0x20)" P-INDEP
-; V116 cse0 [V116,T19] ( 5, 5 ) simd32 -> mm4 "CSE #01: moderate"
+;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V17 tmp12 [V17,T05] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V18 tmp13 [V18,T06] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V20 tmp15 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V21 tmp16 [V21,T07] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V22 tmp17 [V22,T08] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V23 tmp18 [V23 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V24 tmp19 [V24,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V25 tmp20 [V25,T10] ( 3, 6 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V26 tmp21 [V26 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V27 tmp22 [V27,T11] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V28 tmp23 [V28,T12] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V30 tmp25 [V30,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V31 tmp26 [V31,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V38 tmp33 [V38,T15] ( 3, 6 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V39 tmp34 [V39,T16] ( 3, 6 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V44 tmp39 [V44,T20] ( 2, 4 ) simd32 -> [rbp-0x50] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V45 tmp40 [V45,T21] ( 2, 4 ) simd32 -> [rbp-0x70] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V47 tmp42 [V47,T22] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V48 tmp43 [V48,T23] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V49 tmp44 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V50 tmp45 [V50,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V51 tmp46 [V51,T25] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V52 tmp47 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V53 tmp48 [V53,T26] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V54 tmp49 [V54,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V56 tmp51 [V56,T17] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V57 tmp52 [V57,T18] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V58 tmp53 [V58 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V59 tmp54 [V59 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V61 tmp56 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V62 tmp57 [V62,T28] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V63 tmp58 [V63,T29] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V64 tmp59 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V65 tmp60 [V65,T30] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V66 tmp61 [V66,T31] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V67 tmp62 [V67 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V68 tmp63 [V68,T32] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V69 tmp64 [V69,T33] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V71 tmp66 [V71,T34] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V72 tmp67 [V72,T35] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V73 tmp68 [V73 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V74 tmp69 [V74 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V76 tmp71 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V77 tmp72 [V77,T36] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V78 tmp73 [V78,T37] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V79 tmp74 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V80 tmp75 [V80,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V81 tmp76 [V81,T39] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V82 tmp77 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V83 tmp78 [V83,T40] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V84 tmp79 [V84,T41] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V86 tmp81 [V86,T42] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V87 tmp82 [V87,T43] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V90 tmp85 [V90 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V91 tmp86 [V91 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V92 tmp87 [V92,T44] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V93 tmp88 [V93,T45] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V94 tmp89 [V94 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V95 tmp90 [V95,T46] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V96 tmp91 [V96,T47] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V97 tmp92 [V97 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V98 tmp93 [V98,T48] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V99 tmp94 [V99,T49] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V100 tmp95 [V100 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V101 tmp96 [V101,T50] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V102 tmp97 [V102,T51] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V103 tmp98 [V103 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V104 tmp99 [V104 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V105 tmp100 [V105 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[double]>
+;* V106 tmp101 [V106 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V107 tmp102 [V107,T52] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V108 tmp103 [V108,T53] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V109 tmp104 [V109 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V110 tmp105 [V110,T54] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V111 tmp106 [V111,T55] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V112 tmp107 [V112 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V113 tmp108 [V113,T56] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V114 tmp109 [V114,T57] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+;* V115 tmp110 [V115 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[double]>
+; V116 tmp111 [V116,T58] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V117 tmp112 [V117,T59] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[double]>
+; V118 tmp113 [V118,T01] ( 7, 7 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V119 tmp114 [V119,T02] ( 7, 7 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V120 tmp115 [V120,T03] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V121 tmp116 [V121,T04] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V147 tmp142 [V147 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V151 tmp146 [V151 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp150 [V155 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162,T63] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+; V163 tmp158 [V163,T60] ( 3, 3 ) simd32 -> mm14 single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp164 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp168 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._upper (fldOffset=0x20)" P-INDEP
+; V240 tmp235 [V240,T61] ( 2, 2 ) simd32 -> mm0 single-def "field V115._lower (fldOffset=0x0)" P-INDEP
+; V241 tmp236 [V241,T62] ( 2, 2 ) simd32 -> mm1 single-def "field V115._upper (fldOffset=0x20)" P-INDEP
+; V242 cse0 [V242,T19] ( 5, 5 ) simd32 -> mm4 "CSE #01: conservative"
;
-; Lcl frame size = 48
+; Lcl frame size = 112
G_M29830_IG01:
push rbp
- sub rsp, 48
- lea rbp, [rsp+0x30]
+ sub rsp, 112
+ lea rbp, [rsp+0x70]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
;; size=30 bbWeight=1 PerfScore 17.75
G_M29830_IG02:
vmovups ymm4, ymmword ptr [reloc @RWD00]
vandnpd ymm5, ymm4, ymm0
vandnpd ymm6, ymm4, ymm1
vandnpd ymm7, ymm4, ymm2
vandnpd ymm4, ymm4, ymm3
vcmppd ymm8, ymm0, ymm0, 0
vcmppd ymm9, ymm1, ymm1, 0
vmovups ymmword ptr [rbp-0x30], ymm9
vcmppd ymm10, ymm2, ymm2, 0
vcmppd ymm11, ymm3, ymm3, 0
vcmppd ymm12, ymm7, ymm5, 0
vcmppd ymm13, ymm4, ymm6, 0
vxorps ymm14, ymm14, ymm14
vpcmpgtq ymm15, ymm14, ymm0
vpcmpgtq ymm14, ymm14, ymm1
vandpd ymm9, ymm0, ymm15
- vandnpd ymm15, ymm15, ymm2
+ vmovups ymmword ptr [rbp-0x50], ymm9
+ vandpd ymm9, ymm1, ymm14
+ vmovups ymmword ptr [rbp-0x70], ymm9
+ vpcmpeqd ymm9, ymm9, ymm9
+ vxorpd ymm9, ymm9, ymm15
+ vpcmpeqd ymm15, ymm15, ymm15
+ vxorpd ymm14, ymm15, ymm14
+ vandpd ymm9, ymm2, ymm9
+ vandpd ymm14, ymm3, ymm14
+ vmovups ymm15, ymmword ptr [rbp-0x50]
vorpd ymm9, ymm15, ymm9
- vandpd ymm15, ymm1, ymm14
- vandnpd ymm14, ymm14, ymm3
- vorpd ymm14, ymm14, ymm15
+ vmovups ymm15, ymmword ptr [rbp-0x70]
+ vorpd ymm14, ymm15, ymm14
vcmppd ymm5, ymm5, ymm7, 1
vcmppd ymm4, ymm6, ymm4, 1
vandpd ymm6, ymm0, ymm5
- vandnpd ymm5, ymm5, ymm2
- vorpd ymm5, ymm5, ymm6
- vandpd ymm6, ymm1, ymm4
- vandnpd ymm4, ymm4, ymm3
- vorpd ymm4, ymm4, ymm6
+ vandpd ymm7, ymm1, ymm4
+ vpcmpeqd ymm15, ymm15, ymm15
+ vxorpd ymm5, ymm15, ymm5
+ vxorpd ymm4, ymm15, ymm4
+ vandpd ymm5, ymm2, ymm5
+ vandpd ymm4, ymm3, ymm4
+ vorpd ymm5, ymm6, ymm5
+ vorpd ymm4, ymm7, ymm4
vandpd ymm6, ymm12, ymm9
- vandnpd ymm5, ymm12, ymm5
- vorpd ymm5, ymm5, ymm6
- vandpd ymm6, ymm13, ymm14
- vandnpd ymm4, ymm13, ymm4
- vorpd ymm4, ymm4, ymm6
+ vandpd ymm7, ymm13, ymm14
+ vxorpd ymm9, ymm15, ymm12
+ vxorpd ymm12, ymm15, ymm13
+ vandpd ymm5, ymm5, ymm9
+ vandpd ymm4, ymm4, ymm12
+ vorpd ymm5, ymm6, ymm5
+ vorpd ymm4, ymm7, ymm4
vandpd ymm5, ymm10, ymm5
- vandnpd ymm2, ymm10, ymm2
- vorpd ymm2, ymm2, ymm5
vandpd ymm4, ymm11, ymm4
- vandnpd ymm3, ymm11, ymm3
- vorpd ymm3, ymm3, ymm4
+ vxorpd ymm6, ymm15, ymm10
+ vxorpd ymm7, ymm15, ymm11
+ vandpd ymm2, ymm2, ymm6
+ vandpd ymm3, ymm3, ymm7
+ vorpd ymm2, ymm5, ymm2
+ vorpd ymm3, ymm4, ymm3
vandpd ymm2, ymm8, ymm2
- vandnpd ymm0, ymm8, ymm0
- vorpd ymm0, ymm0, ymm2
vmovups ymm9, ymmword ptr [rbp-0x30]
- vandpd ymm2, ymm9, ymm3
- vandnpd ymm1, ymm9, ymm1
- vorpd ymm1, ymm1, ymm2
+ vandpd ymm3, ymm9, ymm3
+ ;; size=276 bbWeight=1 PerfScore 61.50
+G_M29830_IG03:
+ vxorpd ymm4, ymm15, ymm8
+ vxorpd ymm5, ymm15, ymm9
+ vandpd ymm0, ymm0, ymm4
+ vandpd ymm1, ymm1, ymm5
+ vorpd ymm0, ymm2, ymm0
+ vorpd ymm1, ymm3, ymm1
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=227 bbWeight=1 PerfScore 52.92
-G_M29830_IG03:
+ ;; size=38 bbWeight=1 PerfScore 6.25
+G_M29830_IG04:
vzeroupper
- add rsp, 48
+ add rsp, 112
pop rbp
ret
;; size=9 bbWeight=1 PerfScore 2.75
RWD00 dq 8000000000000000h, 8000000000000000h, 8000000000000000h, 8000000000000000h
-; Total bytes of code 266, prolog size 10, PerfScore 73.42, instruction count 62, allocated bytes for code 266 (MethodHash=34218b79) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double] (FullOpts)
+; Total bytes of code 353, prolog size 10, PerfScore 88.25, instruction count 79, allocated bytes for code 353 (MethodHash=34218b79) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[double]:Invoke(System.Runtime.Intrinsics.Vector512`1[double],System.Runtime.Intrinsics.Vector512`1[double]):System.Runtime.Intrinsics.Vector512`1[double] (FullOpts)86 (25.90 % of base) - System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 16 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 33 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V05 loc2 [V05 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V06 loc3 [V06 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;# V07 OutArgs [V07 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V08 tmp1 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V09 tmp2 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V10 tmp3 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V11 tmp4 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V12 tmp5 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V13 tmp6 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V14 tmp7 [V14 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V15 tmp8 [V15 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V16 tmp9 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V17 tmp10 [V17 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V18 tmp11 [V18 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V19 tmp12 [V19 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V20 tmp13 [V20,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V21 tmp14 [V21,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V22 tmp15 [V22 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V23 tmp16 [V23 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V24 tmp17 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V25 tmp18 [V25,T03] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V26 tmp19 [V26,T04] ( 4, 8 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V27 tmp20 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V28 tmp21 [V28,T09] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V29 tmp22 [V29,T10] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V30 tmp23 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V31 tmp24 [V31 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V33 tmp26 [V33 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V34 tmp27 [V34,T11] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V35 tmp28 [V35,T12] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V36 tmp29 [V36 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V37 tmp30 [V37,T21] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V38 tmp31 [V38,T22] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V39 tmp32 [V39 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V40 tmp33 [V40,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V41 tmp34 [V41,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V42 tmp35 [V42 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V43 tmp36 [V43,T23] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V44 tmp37 [V44,T24] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V45 tmp38 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V46 tmp39 [V46,T25] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V47 tmp40 [V47,T26] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V48 tmp41 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V49 tmp42 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V50 tmp43 [V50,T15] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V51 tmp44 [V51,T16] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V19 tmp12 [V19 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V20 tmp13 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V21 tmp14 [V21,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V22 tmp15 [V22,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V23 tmp16 [V23 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V24 tmp17 [V24 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V25 tmp18 [V25 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V26 tmp19 [V26 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V27 tmp20 [V27,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V28 tmp21 [V28,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V30 tmp23 [V30,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V31 tmp24 [V31,T10] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V33 tmp26 [V33 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V34 tmp27 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V36 tmp29 [V36,T11] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V37 tmp30 [V37,T12] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V38 tmp31 [V38 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V39 tmp32 [V39 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V40 tmp33 [V40 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V41 tmp34 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V42 tmp35 [V42,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V43 tmp36 [V43,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V44 tmp37 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V45 tmp38 [V45,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V46 tmp39 [V46,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V47 tmp40 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V48 tmp41 [V48,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V49 tmp42 [V49,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V50 tmp43 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V51 tmp44 [V51,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V52 tmp45 [V52,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
;* V53 tmp46 [V53 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V54 tmp47 [V54,T17] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V55 tmp48 [V55,T18] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V56 tmp49 [V56 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V57 tmp50 [V57,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V58 tmp51 [V58,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V54 tmp47 [V54,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V55 tmp48 [V55,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V56 tmp49 [V56 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V57 tmp50 [V57 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V58 tmp51 [V58 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V59 tmp52 [V59 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V60 tmp53 [V60,T29] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V61 tmp54 [V61,T30] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V62 tmp55 [V62,T05] ( 6, 6 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V63 tmp56 [V63,T06] ( 6, 6 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V64 tmp57 [V64,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V65 tmp58 [V65,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp59 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp60 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp61 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp62 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp63 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp64 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp65 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp66 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp67 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp68 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp69 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp70 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp71 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp72 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp73 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp74 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp75 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp76 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp77 [V84,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp78 [V85,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp79 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp80 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp81 [V88,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp82 [V89,T32] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp83 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp84 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp85 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp86 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp87 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp88 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp89 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp90 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp91 [V98 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp92 [V99 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp93 [V100,T37] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp94 [V101,T38] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp95 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp96 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp97 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp98 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp99 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp100 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp101 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp102 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp103 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp104 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp105 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp106 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp107 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp108 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp109 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp110 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp111 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp112 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp113 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp114 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp115 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp116 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
-; V124 tmp117 [V124,T33] ( 2, 2 ) simd32 -> mm0 single-def "field V59._lower (fldOffset=0x0)" P-INDEP
-; V125 tmp118 [V125,T34] ( 2, 2 ) simd32 -> mm1 single-def "field V59._upper (fldOffset=0x20)" P-INDEP
-; V126 cse0 [V126,T19] ( 4, 4 ) simd32 -> mm6 "CSE #01: moderate"
-; V127 cse1 [V127,T20] ( 4, 4 ) simd32 -> mm8 "CSE #02: moderate"
+; V60 tmp53 [V60,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V61 tmp54 [V61,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V62 tmp55 [V62 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V63 tmp56 [V63,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V64 tmp57 [V64,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V65 tmp58 [V65 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V66 tmp59 [V66,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V67 tmp60 [V67,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V68 tmp61 [V68 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V69 tmp62 [V69,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V70 tmp63 [V70,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V71 tmp64 [V71 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V72 tmp65 [V72 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V73 tmp66 [V73 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V74 tmp67 [V74 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V75 tmp68 [V75,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V76 tmp69 [V76,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V77 tmp70 [V77 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V78 tmp71 [V78,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V79 tmp72 [V79,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V80 tmp73 [V80 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V81 tmp74 [V81,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V82 tmp75 [V82,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V83 tmp76 [V83 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V84 tmp77 [V84,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V85 tmp78 [V85,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V86 tmp79 [V86 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V87 tmp80 [V87 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V88 tmp81 [V88,T15] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V89 tmp82 [V89,T16] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V90 tmp83 [V90 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V91 tmp84 [V91 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V92 tmp85 [V92,T17] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V93 tmp86 [V93,T18] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V94 tmp87 [V94 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V95 tmp88 [V95 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V96 tmp89 [V96 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V97 tmp90 [V97 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V98 tmp91 [V98,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V99 tmp92 [V99,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V100 tmp93 [V100 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V101 tmp94 [V101,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V102 tmp95 [V102,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V103 tmp96 [V103 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V104 tmp97 [V104,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V105 tmp98 [V105,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V106 tmp99 [V106 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V107 tmp100 [V107,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V108 tmp101 [V108,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V109 tmp102 [V109 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V110 tmp103 [V110 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V111 tmp104 [V111 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V112 tmp105 [V112 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V113 tmp106 [V113,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V114 tmp107 [V114,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V115 tmp108 [V115 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V116 tmp109 [V116,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V117 tmp110 [V117,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V118 tmp111 [V118 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V119 tmp112 [V119,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V120 tmp113 [V120,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V121 tmp114 [V121 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V122 tmp115 [V122,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V123 tmp116 [V123,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V124 tmp117 [V124,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V125 tmp118 [V125,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V126 tmp119 [V126,T05] ( 7, 7 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V127 tmp120 [V127,T06] ( 7, 7 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp121 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp122 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp123 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp124 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp125 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp126 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp127 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp128 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp129 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp130 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp131 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp132 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp133 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp134 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp135 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp136 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp137 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp138 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp139 [V146,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp140 [V147,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp141 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp142 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp143 [V150,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp144 [V151,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp145 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp146 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp147 [V154 ] ( 0, 0 ) simd32 -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp148 [V155 ] ( 0, 0 ) simd32 -> zero-ref "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp149 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp150 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp151 [V158 ] ( 0, 0 ) simd32 -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp152 [V159 ] ( 0, 0 ) simd32 -> zero-ref "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp153 [V160 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp154 [V161 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp155 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp156 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp157 [V164 ] ( 0, 0 ) simd32 -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp158 [V165 ] ( 0, 0 ) simd32 -> zero-ref "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp159 [V166,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+; V167 tmp160 [V167,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp161 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp162 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp163 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp164 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp165 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp166 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp167 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp168 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp169 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp170 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp171 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp172 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp173 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp174 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp175 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp176 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp177 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp178 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp179 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp180 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp181 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp182 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp183 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp184 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp185 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp186 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp187 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp188 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp189 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V62._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp190 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V62._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp191 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V65._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp192 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V65._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp193 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp194 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp195 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp196 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp197 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp198 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp199 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp200 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp201 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp202 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp203 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V77._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp204 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V77._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp205 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V80._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp206 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V80._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp207 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp208 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp209 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp210 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp211 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp212 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp213 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp214 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp215 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp216 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp217 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp218 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp219 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp220 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp221 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp222 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp223 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp224 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp225 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp226 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V100._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp227 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp228 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V103._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp229 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp230 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp231 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp232 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp233 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp234 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp235 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp236 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp237 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp238 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp239 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V115._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp240 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V115._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp241 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V118._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp242 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V118._upper (fldOffset=0x20)" P-INDEP
+; V250 tmp243 [V250,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V121._lower (fldOffset=0x0)" P-INDEP
+; V251 tmp244 [V251,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V121._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M24460_IG01:
push rbp
- mov rbp, rsp
- vmovups ymm0, ymmword ptr [rbp+0x10]
- vmovups ymm1, ymmword ptr [rbp+0x30]
- vmovups ymm2, ymmword ptr [rbp+0x50]
- vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
+ vmovups ymm2, ymmword ptr [rbp+0x10]
+ vmovups ymm3, ymmword ptr [rbp+0x30]
+ vmovups ymm0, ymmword ptr [rbp+0x50]
+ vmovups ymm1, ymmword ptr [rbp+0x70]
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M24460_IG02:
vxorps ymm4, ymm4, ymm4
- vpcmpgtq ymm4, ymm4, ymm0
+ vpcmpgtq ymm4, ymm4, ymm2
vxorps ymm5, ymm5, ymm5
- vpsubq ymm5, ymm5, ymm0
- vpblendvb ymm4, ymm0, ymm5, ymm4
+ vpsubq ymm5, ymm5, ymm2
+ vpblendvb ymm4, ymm2, ymm5, ymm4
vxorps ymm5, ymm5, ymm5
- vpcmpgtq ymm5, ymm5, ymm1
+ vpcmpgtq ymm5, ymm5, ymm3
vxorps ymm6, ymm6, ymm6
- vpsubq ymm6, ymm6, ymm1
- vpblendvb ymm5, ymm1, ymm6, ymm5
+ vpsubq ymm6, ymm6, ymm3
+ vpblendvb ymm5, ymm3, ymm6, ymm5
vxorps ymm6, ymm6, ymm6
- vpcmpgtq ymm6, ymm6, ymm2
+ vpcmpgtq ymm6, ymm6, ymm0
vxorps ymm7, ymm7, ymm7
- vpsubq ymm7, ymm7, ymm2
- vpand ymm7, ymm7, ymm6
- vpandn ymm8, ymm6, ymm2
- vpor ymm7, ymm8, ymm7
+ vpsubq ymm7, ymm7, ymm0
+ vpblendvb ymm6, ymm0, ymm7, ymm6
+ vxorps ymm7, ymm7, ymm7
+ vpcmpgtq ymm7, ymm7, ymm1
vxorps ymm8, ymm8, ymm8
- vpcmpgtq ymm8, ymm8, ymm3
- vxorps ymm9, ymm9, ymm9
- vpsubq ymm9, ymm9, ymm3
- vpand ymm9, ymm9, ymm8
- vpandn ymm10, ymm8, ymm3
- vpor ymm9, ymm10, ymm9
- vpcmpeqq ymm10, ymm7, ymm4
- vpcmpeqq ymm11, ymm9, ymm5
- vpand ymm12, ymm2, ymm6
- vpandn ymm6, ymm6, ymm0
- vpor ymm6, ymm6, ymm12
- vpand ymm12, ymm3, ymm8
- vpandn ymm8, ymm8, ymm1
- vpor ymm8, ymm8, ymm12
- vpcmpgtq ymm12, ymm4, ymm7
- vpcmpgtq ymm13, ymm5, ymm9
- vpand ymm14, ymm2, ymm12
- vpandn ymm12, ymm12, ymm0
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm3, ymm13
- vpandn ymm13, ymm13, ymm1
- vpor ymm13, ymm13, ymm14
- vpand ymm6, ymm10, ymm6
- vpandn ymm10, ymm10, ymm12
- vpor ymm6, ymm10, ymm6
- vpand ymm8, ymm11, ymm8
- vpandn ymm10, ymm11, ymm13
- vpor ymm8, ymm10, ymm8
+ vpsubq ymm8, ymm8, ymm1
+ vpblendvb ymm7, ymm1, ymm8, ymm7
+ vpcmpeqq ymm8, ymm6, ymm4
+ vpcmpeqq ymm9, ymm7, ymm5
+ vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm11, ymm10, ymm0
+ vpcmpgtq ymm10, ymm10, ymm1
+ vpand ymm12, ymm0, ymm11
+ vpand ymm13, ymm1, ymm10
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm2, ymm11
+ vpand ymm10, ymm3, ymm10
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
+ vpcmpgtq ymm12, ymm4, ymm6
+ vpcmpgtq ymm13, ymm5, ymm7
+ vpand ymm14, ymm0, ymm12
+ vpand ymm15, ymm1, ymm13
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm2, ymm10
+ vpand ymm12, ymm3, ymm12
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
+ vpand ymm11, ymm8, ymm11
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtq ymm4, ymm10, ymm4
vpcmpgtq ymm5, ymm10, ymm5
+ ;; size=288 bbWeight=1 PerfScore 42.33
+G_M24460_IG03:
vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm6, ymm10, ymm6
vpcmpgtq ymm7, ymm10, ymm7
- vpcmpgtq ymm9, ymm10, ymm9
- vpand ymm0, ymm0, ymm7
- vpandn ymm6, ymm7, ymm6
- vpor ymm0, ymm6, ymm0
- vpand ymm1, ymm1, ymm9
- vpandn ymm6, ymm9, ymm8
- vpor ymm1, ymm6, ymm1
+ vpand ymm2, ymm6, ymm2
+ vpand ymm3, ymm7, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
+ vpand ymm0, ymm0, ymm4
+ vpand ymm1, ymm1, ymm5
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
vpand ymm2, ymm2, ymm4
- ;; size=271 bbWeight=1 PerfScore 38.00
-G_M24460_IG03:
- vpandn ymm0, ymm4, ymm0
+ vpand ymm3, ymm3, ymm5
vpor ymm0, ymm0, ymm2
- vpand ymm2, ymm3, ymm5
- vpandn ymm1, ymm5, ymm1
- vpor ymm1, ymm1, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=32 bbWeight=1 PerfScore 5.92
+ ;; size=91 bbWeight=1 PerfScore 13.92
G_M24460_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 332, prolog size 4, PerfScore 63.67, instruction count 76, allocated bytes for code 332 (MethodHash=abcfa073) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
+; Total bytes of code 418, prolog size 10, PerfScore 76.75, instruction count 92, allocated bytes for code 418 (MethodHash=abcfa073) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)86 (25.90 % of base) - System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 17 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 34 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[long]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[long]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V17 tmp12 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V19 tmp14 [V19 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V20 tmp15 [V20 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V21 tmp16 [V21 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V22 tmp17 [V22,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V23 tmp18 [V23,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V24 tmp19 [V24 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V25 tmp20 [V25 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
-;* V26 tmp21 [V26 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V27 tmp22 [V27,T03] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V28 tmp23 [V28,T04] ( 4, 8 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V30 tmp25 [V30,T09] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V31 tmp26 [V31,T10] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V36 tmp31 [V36,T11] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V37 tmp32 [V37,T12] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V39 tmp34 [V39,T21] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V40 tmp35 [V40,T22] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V42 tmp37 [V42,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V43 tmp38 [V43,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V44 tmp39 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V45 tmp40 [V45,T23] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V46 tmp41 [V46,T24] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V48 tmp43 [V48,T25] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V49 tmp44 [V49,T26] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-;* V51 tmp46 [V51 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V52 tmp47 [V52,T15] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V53 tmp48 [V53,T16] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V21 tmp16 [V21 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V22 tmp17 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V23 tmp18 [V23,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V24 tmp19 [V24,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V25 tmp20 [V25 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V26 tmp21 [V26 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V27 tmp22 [V27 ] ( 0, 0 ) simd32 -> zero-ref "fgMakeTemp is creating a new local variable"
+;* V28 tmp23 [V28 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V29 tmp24 [V29,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V30 tmp25 [V30,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V32 tmp27 [V32,T09] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V33 tmp28 [V33,T10] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V35 tmp30 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V38 tmp33 [V38,T11] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V39 tmp34 [V39,T12] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V41 tmp36 [V41 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V44 tmp39 [V44,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V45 tmp40 [V45,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V47 tmp42 [V47,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V48 tmp43 [V48,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V49 tmp44 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V50 tmp45 [V50,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V51 tmp46 [V51,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V52 tmp47 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V53 tmp48 [V53,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V54 tmp49 [V54,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V56 tmp51 [V56,T17] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V57 tmp52 [V57,T18] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-;* V58 tmp53 [V58 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V59 tmp54 [V59,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V60 tmp55 [V60,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V56 tmp51 [V56,T13] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V57 tmp52 [V57,T14] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V58 tmp53 [V58 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V59 tmp54 [V59 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
;* V61 tmp56 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
-; V62 tmp57 [V62,T29] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V63 tmp58 [V63,T30] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
-; V64 tmp59 [V64,T05] ( 6, 6 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V65 tmp60 [V65,T06] ( 6, 6 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V66 tmp61 [V66,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V67 tmp62 [V67,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V85 tmp80 [V85 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp84 [V89,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-; V93 tmp88 [V93,T32] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp92 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V21._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V26._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp98 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106,T37] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107,T38] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp109 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp110 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp111 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp112 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp113 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp114 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp115 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp116 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
-;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
-;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
-;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
-;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
-;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
-;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
-; V130 tmp125 [V130,T33] ( 2, 2 ) simd32 -> mm0 single-def "field V61._lower (fldOffset=0x0)" P-INDEP
-; V131 tmp126 [V131,T34] ( 2, 2 ) simd32 -> mm1 single-def "field V61._upper (fldOffset=0x20)" P-INDEP
-; V132 cse0 [V132,T19] ( 4, 4 ) simd32 -> mm6 "CSE #01: moderate"
-; V133 cse1 [V133,T20] ( 4, 4 ) simd32 -> mm8 "CSE #02: moderate"
+; V62 tmp57 [V62,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V63 tmp58 [V63,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V64 tmp59 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V65 tmp60 [V65,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V66 tmp61 [V66,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V67 tmp62 [V67 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V68 tmp63 [V68,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V69 tmp64 [V69,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V71 tmp66 [V71,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V72 tmp67 [V72,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V73 tmp68 [V73 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V74 tmp69 [V74 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V76 tmp71 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V77 tmp72 [V77,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V78 tmp73 [V78,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V79 tmp74 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V80 tmp75 [V80,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V81 tmp76 [V81,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V82 tmp77 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V83 tmp78 [V83,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V84 tmp79 [V84,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V86 tmp81 [V86,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V87 tmp82 [V87,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V90 tmp85 [V90,T15] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V91 tmp86 [V91,T16] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V92 tmp87 [V92 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V93 tmp88 [V93 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V94 tmp89 [V94,T17] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V95 tmp90 [V95,T18] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V96 tmp91 [V96 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V97 tmp92 [V97 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V98 tmp93 [V98 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V99 tmp94 [V99 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V100 tmp95 [V100,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V101 tmp96 [V101,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V102 tmp97 [V102 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V103 tmp98 [V103,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V104 tmp99 [V104,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V105 tmp100 [V105 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V106 tmp101 [V106,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V107 tmp102 [V107,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V108 tmp103 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V109 tmp104 [V109,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V110 tmp105 [V110,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V111 tmp106 [V111 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V112 tmp107 [V112 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V113 tmp108 [V113 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[long]>
+;* V114 tmp109 [V114 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V115 tmp110 [V115,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V116 tmp111 [V116,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V117 tmp112 [V117 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V118 tmp113 [V118,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V119 tmp114 [V119,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V120 tmp115 [V120 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V121 tmp116 [V121,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V122 tmp117 [V122,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+;* V123 tmp118 [V123 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[long]>
+; V124 tmp119 [V124,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V125 tmp120 [V125,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[long]>
+; V126 tmp121 [V126,T07] ( 6, 6 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V127 tmp122 [V127,T08] ( 6, 6 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V128 tmp123 [V128,T05] ( 7, 7 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V129 tmp124 [V129,T06] ( 7, 7 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V147 tmp142 [V147 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp146 [V151,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+; V155 tmp150 [V155,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp158 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref "field V25._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp164 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+; V173 tmp168 [V173,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V59._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V74._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V97._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp235 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp236 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp237 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp238 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp239 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp240 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp241 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp242 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V112._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp243 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp244 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._upper (fldOffset=0x20)" P-INDEP
+;* V250 tmp245 [V250 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._lower (fldOffset=0x0)" P-INDEP
+;* V251 tmp246 [V251 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._upper (fldOffset=0x20)" P-INDEP
+;* V252 tmp247 [V252 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V117._lower (fldOffset=0x0)" P-INDEP
+;* V253 tmp248 [V253 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V117._upper (fldOffset=0x20)" P-INDEP
+;* V254 tmp249 [V254 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V120._lower (fldOffset=0x0)" P-INDEP
+;* V255 tmp250 [V255 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V120._upper (fldOffset=0x20)" P-INDEP
+; V256 tmp251 [V256,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V123._lower (fldOffset=0x0)" P-INDEP
+; V257 tmp252 [V257,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V123._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M36742_IG01:
push rbp
- mov rbp, rsp
- vmovups ymm0, ymmword ptr [rbp+0x10]
- vmovups ymm1, ymmword ptr [rbp+0x30]
- vmovups ymm2, ymmword ptr [rbp+0x50]
- vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
+ vmovups ymm2, ymmword ptr [rbp+0x10]
+ vmovups ymm3, ymmword ptr [rbp+0x30]
+ vmovups ymm0, ymmword ptr [rbp+0x50]
+ vmovups ymm1, ymmword ptr [rbp+0x70]
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M36742_IG02:
vxorps ymm4, ymm4, ymm4
- vpcmpgtq ymm4, ymm4, ymm0
+ vpcmpgtq ymm4, ymm4, ymm2
vxorps ymm5, ymm5, ymm5
- vpsubq ymm5, ymm5, ymm0
- vpblendvb ymm4, ymm0, ymm5, ymm4
+ vpsubq ymm5, ymm5, ymm2
+ vpblendvb ymm4, ymm2, ymm5, ymm4
vxorps ymm5, ymm5, ymm5
- vpcmpgtq ymm5, ymm5, ymm1
+ vpcmpgtq ymm5, ymm5, ymm3
vxorps ymm6, ymm6, ymm6
- vpsubq ymm6, ymm6, ymm1
- vpblendvb ymm5, ymm1, ymm6, ymm5
+ vpsubq ymm6, ymm6, ymm3
+ vpblendvb ymm5, ymm3, ymm6, ymm5
vxorps ymm6, ymm6, ymm6
- vpcmpgtq ymm6, ymm6, ymm2
+ vpcmpgtq ymm6, ymm6, ymm0
vxorps ymm7, ymm7, ymm7
- vpsubq ymm7, ymm7, ymm2
- vpand ymm7, ymm7, ymm6
- vpandn ymm8, ymm6, ymm2
- vpor ymm7, ymm8, ymm7
+ vpsubq ymm7, ymm7, ymm0
+ vpblendvb ymm6, ymm0, ymm7, ymm6
+ vxorps ymm7, ymm7, ymm7
+ vpcmpgtq ymm7, ymm7, ymm1
vxorps ymm8, ymm8, ymm8
- vpcmpgtq ymm8, ymm8, ymm3
- vxorps ymm9, ymm9, ymm9
- vpsubq ymm9, ymm9, ymm3
- vpand ymm9, ymm9, ymm8
- vpandn ymm10, ymm8, ymm3
- vpor ymm9, ymm10, ymm9
- vpcmpeqq ymm10, ymm7, ymm4
- vpcmpeqq ymm11, ymm9, ymm5
- vpand ymm12, ymm2, ymm6
- vpandn ymm6, ymm6, ymm0
- vpor ymm6, ymm6, ymm12
- vpand ymm12, ymm3, ymm8
- vpandn ymm8, ymm8, ymm1
- vpor ymm8, ymm8, ymm12
- vpcmpgtq ymm12, ymm4, ymm7
- vpcmpgtq ymm13, ymm5, ymm9
- vpand ymm14, ymm2, ymm12
- vpandn ymm12, ymm12, ymm0
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm3, ymm13
- vpandn ymm13, ymm13, ymm1
- vpor ymm13, ymm13, ymm14
- vpand ymm6, ymm10, ymm6
- vpandn ymm10, ymm10, ymm12
- vpor ymm6, ymm10, ymm6
- vpand ymm8, ymm11, ymm8
- vpandn ymm10, ymm11, ymm13
- vpor ymm8, ymm10, ymm8
+ vpsubq ymm8, ymm8, ymm1
+ vpblendvb ymm7, ymm1, ymm8, ymm7
+ vpcmpeqq ymm8, ymm6, ymm4
+ vpcmpeqq ymm9, ymm7, ymm5
+ vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm11, ymm10, ymm0
+ vpcmpgtq ymm10, ymm10, ymm1
+ vpand ymm12, ymm0, ymm11
+ vpand ymm13, ymm1, ymm10
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm2, ymm11
+ vpand ymm10, ymm3, ymm10
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
+ vpcmpgtq ymm12, ymm4, ymm6
+ vpcmpgtq ymm13, ymm5, ymm7
+ vpand ymm14, ymm0, ymm12
+ vpand ymm15, ymm1, ymm13
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm2, ymm10
+ vpand ymm12, ymm3, ymm12
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
+ vpand ymm11, ymm8, ymm11
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtq ymm4, ymm10, ymm4
vpcmpgtq ymm5, ymm10, ymm5
+ ;; size=288 bbWeight=1 PerfScore 42.33
+G_M36742_IG03:
vxorps ymm10, ymm10, ymm10
+ vpcmpgtq ymm6, ymm10, ymm6
vpcmpgtq ymm7, ymm10, ymm7
- vpcmpgtq ymm9, ymm10, ymm9
- vpand ymm0, ymm0, ymm7
- vpandn ymm6, ymm7, ymm6
- vpor ymm0, ymm6, ymm0
- vpand ymm1, ymm1, ymm9
- vpandn ymm6, ymm9, ymm8
- vpor ymm1, ymm6, ymm1
+ vpand ymm2, ymm6, ymm2
+ vpand ymm3, ymm7, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
+ vpand ymm0, ymm0, ymm4
+ vpand ymm1, ymm1, ymm5
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
vpand ymm2, ymm2, ymm4
- ;; size=271 bbWeight=1 PerfScore 38.00
-G_M36742_IG03:
- vpandn ymm0, ymm4, ymm0
+ vpand ymm3, ymm3, ymm5
vpor ymm0, ymm0, ymm2
- vpand ymm2, ymm3, ymm5
- vpandn ymm1, ymm5, ymm1
- vpor ymm1, ymm1, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=32 bbWeight=1 PerfScore 5.92
+ ;; size=91 bbWeight=1 PerfScore 13.92
G_M36742_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 332, prolog size 4, PerfScore 63.67, instruction count 76, allocated bytes for code 332 (MethodHash=bdfd7079) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)
+; Total bytes of code 418, prolog size 10, PerfScore 76.75, instruction count 92, allocated bytes for code 418 (MethodHash=bdfd7079) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[long]:Invoke(System.Runtime.Intrinsics.Vector512`1[long],System.Runtime.Intrinsics.Vector512`1[long]):System.Runtime.Intrinsics.Vector512`1[long] (FullOpts)81 (19.71 % of base) - System.Runtime.Intrinsics.Vector256`1[ubyte]:System.Runtime.Intrinsics.ISimdVector,T>.Divide(System.Runtime.Intrinsics.Vector256`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector256`1[ubyte]
; Assembly listing for method System.Runtime.Intrinsics.Vector256`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector256<T>,T>.Divide(System.Runtime.Intrinsics.Vector256`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector256`1[ubyte] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 16 single block inlinees; 9 inlinees without PGO data
+; 0 inlinees with PGO data; 15 single block inlinees; 13 inlinees without PGO data
; Final local variable assignments
;
-; V00 RetBuf [V00,T09] ( 4, 4 ) byref -> rbx single-def
-; V01 arg0 [V01,T20] ( 2, 2 ) simd32 -> [rbp+0x10] single-def <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V02 arg1 [V02,T10] ( 3, 3 ) ubyte -> rsi single-def
+; V00 RetBuf [V00,T01] ( 4, 4 ) byref -> rdi single-def
+; V01 arg0 [V01,T16] ( 2, 2 ) simd32 -> mm0 single-def <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V02 arg1 [V02,T02] ( 3, 3 ) ubyte -> rsi single-def
;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
-; V04 tmp1 [V04,T17] ( 2, 4 ) simd16 -> [rbp-0x40] spill-single-def "impAppendStmt"
+; V04 tmp1 [V04,T13] ( 2, 4 ) simd16 -> mm1 "impAppendStmt"
;* V05 tmp2 [V05 ] ( 0, 0 ) simd16 -> zero-ref "spilled call-like call argument"
-; V06 tmp3 [V06,T15] ( 3, 6 ) simd16 -> [rbp-0x50] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V06 tmp3 [V06,T11] ( 3, 6 ) simd16 -> [rbp-0x10] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V07 tmp4 [V07 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V08 tmp5 [V08 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V09 tmp6 [V09 ] ( 2, 5 ) struct ( 8) [rbp-0x58] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V10 tmp7 [V10,T00] ( 5, 17 ) int -> r15 "Inline stloc first use temp"
-; V11 tmp8 [V11 ] ( 2, 10 ) struct ( 8) [rbp-0x60] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V09 tmp6 [V09 ] ( 9, 9 ) struct ( 8) [rbp-0x18] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V10 tmp7 [V10,T07] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V11 tmp8 [V11 ] ( 9, 18 ) struct ( 8) [rbp-0x20] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V12 tmp9 [V12 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V13 tmp10 [V13 ] ( 2, 5 ) struct ( 8) [rbp-0x68] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V14 tmp11 [V14,T01] ( 5, 17 ) int -> r13 "Inline stloc first use temp"
-; V15 tmp12 [V15 ] ( 2, 10 ) struct ( 8) [rbp-0x70] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V16 tmp13 [V16 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V17 tmp14 [V17,T18] ( 3, 3 ) simd16 -> [rbp-0x80] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-; V18 tmp15 [V18,T16] ( 3, 6 ) simd16 -> [rbp-0x90] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-;* V19 tmp16 [V19 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V20 tmp17 [V20 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V21 tmp18 [V21 ] ( 2, 5 ) struct ( 8) [rbp-0x98] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V22 tmp19 [V22,T02] ( 5, 17 ) int -> r15 "Inline stloc first use temp"
-; V23 tmp20 [V23 ] ( 2, 10 ) struct ( 8) [rbp-0xA0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-;* V24 tmp21 [V24 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V25 tmp22 [V25 ] ( 2, 5 ) struct ( 8) [rbp-0xA8] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
-; V26 tmp23 [V26,T03] ( 5, 17 ) int -> r13 "Inline stloc first use temp"
-; V27 tmp24 [V27 ] ( 2, 10 ) struct ( 8) [rbp-0xB0] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V13 tmp10 [V13 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V14 tmp11 [V14 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V15 tmp12 [V15 ] ( 9, 9 ) struct ( 8) [rbp-0x28] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V16 tmp13 [V16,T08] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V17 tmp14 [V17 ] ( 9, 18 ) struct ( 8) [rbp-0x30] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V18 tmp15 [V18 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V19 tmp16 [V19 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V20 tmp17 [V20 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V21 tmp18 [V21,T14] ( 3, 3 ) simd16 -> [rbp-0x40] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+; V22 tmp19 [V22,T12] ( 3, 6 ) simd16 -> [rbp-0x50] do-not-enreg[SF] "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V23 tmp20 [V23 ] ( 0, 0 ) struct ( 8) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V24 tmp21 [V24 ] ( 0, 0 ) struct ( 8) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+; V25 tmp22 [V25 ] ( 9, 9 ) struct ( 8) [rbp-0x58] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V26 tmp23 [V26,T09] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V27 tmp24 [V27 ] ( 9, 18 ) struct ( 8) [rbp-0x60] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
;* V28 tmp25 [V28 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
-; V29 tmp26 [V29,T19] ( 3, 3 ) simd16 -> [rbp-0xC0] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
-;* V30 tmp27 [V30 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
-; V31 tmp28 [V31,T11] ( 2, 2 ) long -> r15 "field V07._00 (fldOffset=0x0)" P-INDEP
-; V32 tmp29 [V32,T12] ( 2, 2 ) long -> rdi "field V08._00 (fldOffset=0x0)" P-INDEP
-; V33 tmp30 [V33 ] ( 2, 5 ) long -> [rbp-0x58] do-not-enreg[X] addr-exposed "field V09._00 (fldOffset=0x0)" P-DEP
-; V34 tmp31 [V34 ] ( 2, 9 ) long -> [rbp-0x60] do-not-enreg[X] addr-exposed "field V11._00 (fldOffset=0x0)" P-DEP
-; V35 tmp32 [V35 ] ( 2, 5 ) long -> [rbp-0x68] do-not-enreg[X] addr-exposed "field V13._00 (fldOffset=0x0)" P-DEP
-; V36 tmp33 [V36 ] ( 2, 9 ) long -> [rbp-0x70] do-not-enreg[X] addr-exposed "field V15._00 (fldOffset=0x0)" P-DEP
-; V37 tmp34 [V37,T13] ( 2, 2 ) long -> r15 "field V19._00 (fldOffset=0x0)" P-INDEP
-; V38 tmp35 [V38,T14] ( 2, 2 ) long -> rax "field V20._00 (fldOffset=0x0)" P-INDEP
-; V39 tmp36 [V39 ] ( 2, 5 ) long -> [rbp-0x98] do-not-enreg[X] addr-exposed "field V21._00 (fldOffset=0x0)" P-DEP
-; V40 tmp37 [V40 ] ( 2, 9 ) long -> [rbp-0xA0] do-not-enreg[X] addr-exposed "field V23._00 (fldOffset=0x0)" P-DEP
-; V41 tmp38 [V41 ] ( 2, 5 ) long -> [rbp-0xA8] do-not-enreg[X] addr-exposed "field V25._00 (fldOffset=0x0)" P-DEP
-; V42 tmp39 [V42 ] ( 2, 9 ) long -> [rbp-0xB0] do-not-enreg[X] addr-exposed "field V27._00 (fldOffset=0x0)" P-DEP
-; V43 cse0 [V43,T04] ( 5, 17 ) int -> r14 hoist "CSE #01: aggressive"
-; V44 cse1 [V44,T05] ( 3, 12 ) long -> r13 "CSE #02: aggressive"
-; V45 cse2 [V45,T06] ( 3, 12 ) long -> r12 "CSE #03: aggressive"
-; V46 cse3 [V46,T07] ( 3, 12 ) long -> r13 "CSE #04: aggressive"
-; V47 cse4 [V47,T08] ( 3, 12 ) long -> r12 "CSE #05: aggressive"
+;* V29 tmp26 [V29 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V30 tmp27 [V30 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V31 tmp28 [V31 ] ( 9, 9 ) struct ( 8) [rbp-0x68] do-not-enreg[XS] addr-exposed ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V32 tmp29 [V32,T10] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp"
+; V33 tmp30 [V33 ] ( 9, 18 ) struct ( 8) [rbp-0x70] do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" <System.Runtime.Intrinsics.Vector64`1[ubyte]>
+;* V34 tmp31 [V34 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp"
+;* V35 tmp32 [V35 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp"
+;* V36 tmp33 [V36 ] ( 0, 0 ) ubyte -> zero-ref "Inlining Arg"
+; V37 tmp34 [V37,T15] ( 3, 3 ) simd16 -> [rbp-0x80] do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
+;* V38 tmp35 [V38 ] ( 0, 0 ) simd32 -> zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector256`1[ubyte]>
+; V39 tmp36 [V39,T03] ( 2, 2 ) long -> rsi "field V07._00 (fldOffset=0x0)" P-INDEP
+; V40 tmp37 [V40,T04] ( 2, 2 ) long -> rax "field V08._00 (fldOffset=0x0)" P-INDEP
+; V41 tmp38 [V41 ] ( 9, 9 ) long -> [rbp-0x18] do-not-enreg[X] addr-exposed "field V09._00 (fldOffset=0x0)" P-DEP
+; V42 tmp39 [V42 ] ( 9, 17 ) long -> [rbp-0x20] do-not-enreg[X] addr-exposed "field V11._00 (fldOffset=0x0)" P-DEP
+; V43 tmp40 [V43 ] ( 9, 9 ) long -> [rbp-0x28] do-not-enreg[X] addr-exposed "field V15._00 (fldOffset=0x0)" P-DEP
+; V44 tmp41 [V44 ] ( 9, 17 ) long -> [rbp-0x30] do-not-enreg[X] addr-exposed "field V17._00 (fldOffset=0x0)" P-DEP
+; V45 tmp42 [V45,T05] ( 2, 2 ) long -> rsi "field V23._00 (fldOffset=0x0)" P-INDEP
+; V46 tmp43 [V46,T06] ( 2, 2 ) long -> rax "field V24._00 (fldOffset=0x0)" P-INDEP
+; V47 tmp44 [V47 ] ( 9, 9 ) long -> [rbp-0x58] do-not-enreg[X] addr-exposed "field V25._00 (fldOffset=0x0)" P-DEP
+; V48 tmp45 [V48 ] ( 9, 17 ) long -> [rbp-0x60] do-not-enreg[X] addr-exposed "field V27._00 (fldOffset=0x0)" P-DEP
+; V49 tmp46 [V49 ] ( 9, 9 ) long -> [rbp-0x68] do-not-enreg[X] addr-exposed "field V31._00 (fldOffset=0x0)" P-DEP
+; V50 tmp47 [V50 ] ( 9, 17 ) long -> [rbp-0x70] do-not-enreg[X] addr-exposed "field V33._00 (fldOffset=0x0)" P-DEP
+; V51 cse0 [V51,T00] ( 33, 33 ) int -> rcx "CSE #01: aggressive"
;
-; Lcl frame size = 152
+; Lcl frame size = 128
G_M26985_IG01:
push rbp
- push r15
- push r14
- push r13
- push r12
- push rbx
- sub rsp, 152
- lea rbp, [rsp+0xC0]
- mov rbx, rdi
+ sub rsp, 128
+ lea rbp, [rsp+0x80]
vmovups ymm0, ymmword ptr [rbp+0x10]
- ;; size=33 bbWeight=1 PerfScore 11.00
+ ;; size=21 bbWeight=1 PerfScore 5.75
G_M26985_IG02:
- vmovups ymmword ptr [rbp+0x10], ymm0
vmovaps ymm1, ymm0
- vmovaps xmmword ptr [rbp-0x50], xmm1
- mov rdi, qword ptr [rbp-0x50]
- mov qword ptr [rbp-0x60], rdi
- xor r15d, r15d
- movzx r14, sil
- ;; size=29 bbWeight=1 PerfScore 4.75
+ vmovaps xmmword ptr [rbp-0x10], xmm1
+ mov rax, qword ptr [rbp-0x10]
+ mov qword ptr [rbp-0x20], rax
+ movzx rax, byte ptr [rbp-0x20]
+ movzx rcx, sil
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x18], al
+ movzx rax, byte ptr [rbp-0x1F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x17], al
+ movzx rax, byte ptr [rbp-0x1E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x16], al
+ movzx rax, byte ptr [rbp-0x1D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x15], al
+ movzx rax, byte ptr [rbp-0x1C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x14], al
+ movzx rax, byte ptr [rbp-0x1B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x13], al
+ movzx rax, byte ptr [rbp-0x1A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x12], al
+ movzx rax, byte ptr [rbp-0x19]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x11], al
+ mov rsi, qword ptr [rbp-0x18]
+ mov rax, qword ptr [rbp-0x08]
+ mov qword ptr [rbp-0x30], rax
+ movzx rax, byte ptr [rbp-0x30]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x28], al
+ movzx rax, byte ptr [rbp-0x2F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x27], al
+ movzx rax, byte ptr [rbp-0x2E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x26], al
+ movzx rax, byte ptr [rbp-0x2D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x25], al
+ movzx rax, byte ptr [rbp-0x2C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x24], al
+ movzx rax, byte ptr [rbp-0x2B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x23], al
+ movzx rax, byte ptr [rbp-0x2A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x22], al
+ movzx rax, byte ptr [rbp-0x29]
+ xor edx, edx
+ ;; size=204 bbWeight=1 PerfScore 416.50
G_M26985_IG03:
- lea rdi, [rbp-0x60]
- movsxd r13, r15d
- movzx rdi, byte ptr [rdi+r13]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0x58]
- mov byte ptr [rdi+r13], al
- inc r15d
- cmp r15d, 8
- jl SHORT G_M26985_IG03
- ;; size=44 bbWeight=4 PerfScore 37.00
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x21], al
+ mov rax, qword ptr [rbp-0x28]
+ mov qword ptr [rbp-0x40], rsi
+ mov qword ptr [rbp-0x38], rax
+ vmovaps xmm1, xmmword ptr [rbp-0x40]
+ vextractf128 xmm0, ymm0, 1
+ vmovaps xmmword ptr [rbp-0x50], xmm0
+ mov rax, qword ptr [rbp-0x50]
+ mov qword ptr [rbp-0x60], rax
+ movzx rax, byte ptr [rbp-0x60]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x58], al
+ movzx rax, byte ptr [rbp-0x5F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x57], al
+ movzx rax, byte ptr [rbp-0x5E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x56], al
+ movzx rax, byte ptr [rbp-0x5D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x55], al
+ movzx rax, byte ptr [rbp-0x5C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x54], al
+ movzx rax, byte ptr [rbp-0x5B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x53], al
+ movzx rax, byte ptr [rbp-0x5A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x52], al
+ movzx rax, byte ptr [rbp-0x59]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x51], al
+ mov rsi, qword ptr [rbp-0x58]
+ mov rax, qword ptr [rbp-0x48]
+ mov qword ptr [rbp-0x70], rax
+ movzx rax, byte ptr [rbp-0x70]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x68], al
+ movzx rax, byte ptr [rbp-0x6F]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x67], al
+ movzx rax, byte ptr [rbp-0x6E]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x66], al
+ movzx rax, byte ptr [rbp-0x6D]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x65], al
+ movzx rax, byte ptr [rbp-0x6C]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x64], al
+ movzx rax, byte ptr [rbp-0x6B]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x63], al
+ ;; size=207 bbWeight=1 PerfScore 421.50
G_M26985_IG04:
- mov r15, qword ptr [rbp-0x58]
- mov rdi, qword ptr [rbp-0x48]
- mov qword ptr [rbp-0x70], rdi
- xor r13d, r13d
- ;; size=15 bbWeight=1 PerfScore 3.25
+ movzx rax, byte ptr [rbp-0x6A]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x62], al
+ movzx rax, byte ptr [rbp-0x69]
+ xor edx, edx
+ div edx:eax, ecx
+ mov byte ptr [rbp-0x61], al
+ mov rax, qword ptr [rbp-0x68]
+ mov qword ptr [rbp-0x80], rsi
+ mov qword ptr [rbp-0x78], rax
+ vinserti128 ymm0, ymm1, xmmword ptr [rbp-0x80], 1
+ vmovups ymmword ptr [rdi], ymm0
+ mov rax, rdi
+ ;; size=48 bbWeight=1 PerfScore 63.75
G_M26985_IG05:
- lea rdi, [rbp-0x70]
- movsxd r12, r13d
- movzx rdi, byte ptr [rdi+r12]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0x68]
- mov byte ptr [rdi+r12], al
- inc r13d
- cmp r13d, 8
- jl SHORT G_M26985_IG05
- ;; size=44 bbWeight=4 PerfScore 37.00
-G_M26985_IG06:
- mov rdi, qword ptr [rbp-0x68]
- mov qword ptr [rbp-0x80], r15
- mov qword ptr [rbp-0x78], rdi
- vmovaps xmm1, xmmword ptr [rbp-0x80]
- vmovaps xmmword ptr [rbp-0x40], xmm1
- vmovups ymm0, ymmword ptr [rbp+0x10]
- vextractf128 xmm0, ymm0, 1
- vmovaps xmmword ptr [rbp-0x90], xmm0
- mov rdi, qword ptr [rbp-0x90]
- mov qword ptr [rbp-0xA0], rdi
- xor r15d, r15d
- ;; size=58 bbWeight=1 PerfScore 16.25
-G_M26985_IG07:
- lea rdi, [rbp-0xA0]
- movsxd r13, r15d
- movzx rdi, byte ptr [rdi+r13]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rdi, [rbp-0x98]
- mov byte ptr [rdi+r13], al
- inc r15d
- cmp r15d, 8
- jl SHORT G_M26985_IG07
- ;; size=50 bbWeight=4 PerfScore 37.00
-G_M26985_IG08:
- mov r15, qword ptr [rbp-0x98]
- mov rdi, qword ptr [rbp-0x88]
- mov qword ptr [rbp-0xB0], rdi
- xor r13d, r13d
- ;; size=24 bbWeight=1 PerfScore 3.25
-G_M26985_IG09:
- lea rdi, [rbp-0xB0]
- movsxd r12, r13d
- movzx rdi, byte ptr [rdi+r12]
- mov esi, r14d
- mov rax, 0xD1FFAB1E ; code for System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- call [rax]System.Runtime.Intrinsics.Scalar`1[ubyte]:Divide(ubyte,ubyte):ubyte
- lea rcx, [rbp-0xA8]
- mov byte ptr [rcx+r12], al
- inc r13d
- cmp r13d, 8
- jl SHORT G_M26985_IG09
- ;; size=50 bbWeight=4 PerfScore 37.00
-G_M26985_IG10:
- mov rax, qword ptr [rbp-0xA8]
- mov qword ptr [rbp-0xC0], r15
- mov qword ptr [rbp-0xB8], rax
- vmovaps xmm1, xmmword ptr [rbp-0x40]
- vinserti128 ymm0, ymm1, xmmword ptr [rbp-0xC0], 1
- vmovups ymmword ptr [rbx], ymm0
- mov rax, rbx
- ;; size=43 bbWeight=1 PerfScore 12.25
-G_M26985_IG11:
vzeroupper
- add rsp, 152
- pop rbx
- pop r12
- pop r13
- pop r14
- pop r15
+ add rsp, 128
pop rbp
ret
- ;; size=21 bbWeight=1 PerfScore 5.25
+ ;; size=12 bbWeight=1 PerfScore 2.75
-; Total bytes of code 411, prolog size 25, PerfScore 204.00, instruction count 96, allocated bytes for code 411 (MethodHash=413b9696) for method System.Runtime.Intrinsics.Vector256`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector256<T>,T>.Divide(System.Runtime.Intrinsics.Vector256`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector256`1[ubyte] (FullOpts)
+; Total bytes of code 492, prolog size 16, PerfScore 910.25, instruction count 161, allocated bytes for code 492 (MethodHash=413b9696) for method System.Runtime.Intrinsics.Vector256`1[ubyte]:System.Runtime.Intrinsics.ISimdVector<System.Runtime.Intrinsics.Vector256<T>,T>.Divide(System.Runtime.Intrinsics.Vector256`1[ubyte],ubyte):System.Runtime.Intrinsics.Vector256`1[ubyte] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 16 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 33 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V05 loc2 [V05 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V06 loc3 [V06 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;# V07 OutArgs [V07 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V08 tmp1 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V09 tmp2 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V10 tmp3 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V11 tmp4 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V12 tmp5 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V13 tmp6 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V14 tmp7 [V14 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V15 tmp8 [V15 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V16 tmp9 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V18 tmp11 [V18,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V19 tmp12 [V19,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V20 tmp13 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V21 tmp14 [V21,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V22 tmp15 [V22,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V23 tmp16 [V23 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V24 tmp17 [V24,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V25 tmp18 [V25,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V26 tmp19 [V26 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V27 tmp20 [V27 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V30 tmp23 [V30,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V31 tmp24 [V31,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V33 tmp26 [V33,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V34 tmp27 [V34,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V36 tmp29 [V36,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V37 tmp30 [V37,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V38 tmp31 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V39 tmp32 [V39,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V40 tmp33 [V40,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V41 tmp34 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V42 tmp35 [V42,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V43 tmp36 [V43,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V44 tmp37 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V45 tmp38 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V46 tmp39 [V46,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V47 tmp40 [V47,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V48 tmp41 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V18 tmp11 [V18 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V19 tmp12 [V19,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V20 tmp13 [V20,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V21 tmp14 [V21 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V22 tmp15 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V23 tmp16 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V24 tmp17 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V25 tmp18 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V26 tmp19 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V27 tmp20 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V30 tmp23 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V31 tmp24 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V32 tmp25 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V33 tmp26 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V34 tmp27 [V34 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V36 tmp29 [V36 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V37 tmp30 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V38 tmp31 [V38,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V39 tmp32 [V39,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V40 tmp33 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V41 tmp34 [V41,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V42 tmp35 [V42,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V43 tmp36 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V44 tmp37 [V44,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V45 tmp38 [V45,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V46 tmp39 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V47 tmp40 [V47,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V48 tmp41 [V48,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
;* V49 tmp42 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V50 tmp43 [V50,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V51 tmp44 [V51,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V53 tmp46 [V53,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V54 tmp47 [V54,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V50 tmp43 [V50,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V51 tmp44 [V51,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V53 tmp46 [V53 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V54 tmp47 [V54 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V55 tmp48 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V58 tmp51 [V58,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V59 tmp52 [V59,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V60 tmp53 [V60,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp54 [V61,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V62 tmp55 [V62 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V63 tmp56 [V63 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp57 [V64 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp58 [V65 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp59 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp60 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp61 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp62 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp63 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp64 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp65 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp66 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp67 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp68 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp69 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp70 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp71 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp72 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp73 [V80,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-; V81 tmp74 [V81,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp75 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp76 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp77 [V84,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp78 [V85,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp79 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp80 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp81 [V88 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V89 tmp82 [V89 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp83 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp84 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp85 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp86 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp87 [V94 ] ( 0, 0 ) simd32 -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp88 [V95 ] ( 0, 0 ) simd32 -> zero-ref "field V26._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp89 [V96,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-; V97 tmp90 [V97,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp91 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp92 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp93 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp94 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp95 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp96 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp97 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp98 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp99 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp100 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp101 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp102 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp103 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp104 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp105 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp106 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp107 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp108 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp109 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp110 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp111 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp112 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
-; V120 tmp113 [V120,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V55._lower (fldOffset=0x0)" P-INDEP
-; V121 tmp114 [V121,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V58 tmp51 [V58 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V59 tmp52 [V59,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V60 tmp53 [V60,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V61 tmp54 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V62 tmp55 [V62,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V63 tmp56 [V63,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V64 tmp57 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V65 tmp58 [V65,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V66 tmp59 [V66,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V67 tmp60 [V67 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V68 tmp61 [V68 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V69 tmp62 [V69 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V70 tmp63 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V71 tmp64 [V71,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V72 tmp65 [V72,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V73 tmp66 [V73 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V74 tmp67 [V74,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V75 tmp68 [V75,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V76 tmp69 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V77 tmp70 [V77,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V78 tmp71 [V78,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V79 tmp72 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V80 tmp73 [V80,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V81 tmp74 [V81,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V82 tmp75 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V83 tmp76 [V83 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V84 tmp77 [V84,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V85 tmp78 [V85,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V86 tmp79 [V86 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V87 tmp80 [V87 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V88 tmp81 [V88,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V89 tmp82 [V89,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V90 tmp83 [V90 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V91 tmp84 [V91 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V92 tmp85 [V92 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V93 tmp86 [V93 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V94 tmp87 [V94,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V95 tmp88 [V95,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V96 tmp89 [V96 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V97 tmp90 [V97,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V98 tmp91 [V98,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V99 tmp92 [V99 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V100 tmp93 [V100,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V101 tmp94 [V101,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V102 tmp95 [V102 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V103 tmp96 [V103,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V104 tmp97 [V104,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V105 tmp98 [V105 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V106 tmp99 [V106 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V107 tmp100 [V107 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V108 tmp101 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V109 tmp102 [V109,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V110 tmp103 [V110,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V111 tmp104 [V111 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V112 tmp105 [V112,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V113 tmp106 [V113,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V114 tmp107 [V114 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V115 tmp108 [V115,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V116 tmp109 [V116,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V117 tmp110 [V117 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V118 tmp111 [V118,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V119 tmp112 [V119,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V120 tmp113 [V120,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V121 tmp114 [V121,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V122 tmp115 [V122,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp116 [V123,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V124 tmp117 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V125 tmp118 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp119 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp120 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp121 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp122 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp123 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp124 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp125 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp126 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp127 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp128 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp129 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp130 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp131 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp132 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp133 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp134 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp135 [V142,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+; V143 tmp136 [V143,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp137 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp138 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp139 [V146,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp140 [V147,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp141 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp142 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp143 [V150 ] ( 0, 0 ) simd32 -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V151 tmp144 [V151 ] ( 0, 0 ) simd32 -> zero-ref "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp145 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp146 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp147 [V154 ] ( 0, 0 ) simd32 -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp148 [V155 ] ( 0, 0 ) simd32 -> zero-ref "field V21._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp149 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp150 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp151 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp152 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp153 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp154 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp155 [V162,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+; V163 tmp156 [V163,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp157 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp158 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp159 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp160 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp161 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp162 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp163 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp164 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp165 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp166 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp167 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp168 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp169 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp170 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp171 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp172 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp173 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp174 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp175 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp176 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp177 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp178 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp179 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp180 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp181 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp182 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp183 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp184 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp185 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp186 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp187 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp188 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp189 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp190 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp191 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp192 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp193 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp194 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp195 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp196 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp197 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp198 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp199 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp200 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp201 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp202 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp203 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp204 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp205 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp206 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp207 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp208 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp209 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp210 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp211 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp212 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp213 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp214 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp215 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp216 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp217 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp218 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp219 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp220 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp221 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp222 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp223 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp224 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp225 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp226 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp227 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp228 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp229 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp230 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp231 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp232 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp233 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp234 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp235 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp236 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp237 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp238 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._upper (fldOffset=0x20)" P-INDEP
+; V246 tmp239 [V246,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V117._lower (fldOffset=0x0)" P-INDEP
+; V247 tmp240 [V247,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V117._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M64306_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M64306_IG02:
vpabsd ymm4, ymm0
vpabsd ymm5, ymm1
vpabsd ymm6, ymm2
vpabsd ymm7, ymm3
vpcmpeqd ymm8, ymm4, ymm6
vpcmpeqd ymm9, ymm5, ymm7
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm11, ymm10, ymm0
vpcmpgtd ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm2
- vpandn ymm11, ymm11, ymm0
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm3
- vpandn ymm10, ymm10, ymm1
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm3
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm0
+ vpand ymm10, ymm10, ymm1
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtd ymm12, ymm4, ymm6
vpcmpgtd ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm4, ymm10, ymm4
vpcmpgtd ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm6, ymm10, ymm6
vpcmpgtd ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M64306_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M64306_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M64306_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=f5ea04cd) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=f5ea04cd) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 16 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 33 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V05 loc2 [V05 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V06 loc3 [V06 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;# V07 OutArgs [V07 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V08 tmp1 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V09 tmp2 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V10 tmp3 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V11 tmp4 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V12 tmp5 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V13 tmp6 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V14 tmp7 [V14 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V15 tmp8 [V15 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V16 tmp9 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V18 tmp11 [V18,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V19 tmp12 [V19,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V20 tmp13 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V21 tmp14 [V21,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V22 tmp15 [V22,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V23 tmp16 [V23 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V24 tmp17 [V24,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V25 tmp18 [V25,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V26 tmp19 [V26 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V27 tmp20 [V27 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V30 tmp23 [V30,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V31 tmp24 [V31,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V33 tmp26 [V33,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V34 tmp27 [V34,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V36 tmp29 [V36,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V37 tmp30 [V37,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V38 tmp31 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V39 tmp32 [V39,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V40 tmp33 [V40,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V41 tmp34 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V42 tmp35 [V42,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V43 tmp36 [V43,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V44 tmp37 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V45 tmp38 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V46 tmp39 [V46,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V47 tmp40 [V47,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V48 tmp41 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V18 tmp11 [V18 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V19 tmp12 [V19,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V20 tmp13 [V20,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V21 tmp14 [V21 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V22 tmp15 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V23 tmp16 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V24 tmp17 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V25 tmp18 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V26 tmp19 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V27 tmp20 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V30 tmp23 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V31 tmp24 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V32 tmp25 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V33 tmp26 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V34 tmp27 [V34 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V36 tmp29 [V36 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V37 tmp30 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V38 tmp31 [V38,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V39 tmp32 [V39,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V40 tmp33 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V41 tmp34 [V41,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V42 tmp35 [V42,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V43 tmp36 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V44 tmp37 [V44,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V45 tmp38 [V45,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V46 tmp39 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V47 tmp40 [V47,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V48 tmp41 [V48,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
;* V49 tmp42 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V50 tmp43 [V50,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V51 tmp44 [V51,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V53 tmp46 [V53,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V54 tmp47 [V54,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V50 tmp43 [V50,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V51 tmp44 [V51,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V53 tmp46 [V53 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V54 tmp47 [V54 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V55 tmp48 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V58 tmp51 [V58,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V59 tmp52 [V59,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V60 tmp53 [V60,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp54 [V61,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V62 tmp55 [V62 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V63 tmp56 [V63 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp57 [V64 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp58 [V65 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp59 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp60 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp61 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp62 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp63 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp64 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp65 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp66 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp67 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp68 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp69 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp70 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp71 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp72 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp73 [V80,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-; V81 tmp74 [V81,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp75 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp76 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp77 [V84,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp78 [V85,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp79 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp80 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp81 [V88 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V89 tmp82 [V89 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp83 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp84 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp85 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp86 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp87 [V94 ] ( 0, 0 ) simd32 -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp88 [V95 ] ( 0, 0 ) simd32 -> zero-ref "field V26._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp89 [V96,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-; V97 tmp90 [V97,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp91 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp92 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp93 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp94 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp95 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp96 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp97 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp98 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp99 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp100 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp101 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp102 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp103 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp104 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp105 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp106 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp107 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp108 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp109 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp110 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp111 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp112 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
-; V120 tmp113 [V120,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V55._lower (fldOffset=0x0)" P-INDEP
-; V121 tmp114 [V121,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V58 tmp51 [V58 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V59 tmp52 [V59,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V60 tmp53 [V60,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V61 tmp54 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V62 tmp55 [V62,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V63 tmp56 [V63,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V64 tmp57 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V65 tmp58 [V65,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V66 tmp59 [V66,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V67 tmp60 [V67 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V68 tmp61 [V68 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V69 tmp62 [V69 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V70 tmp63 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V71 tmp64 [V71,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V72 tmp65 [V72,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V73 tmp66 [V73 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V74 tmp67 [V74,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V75 tmp68 [V75,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V76 tmp69 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V77 tmp70 [V77,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V78 tmp71 [V78,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V79 tmp72 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V80 tmp73 [V80,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V81 tmp74 [V81,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V82 tmp75 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V83 tmp76 [V83 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V84 tmp77 [V84,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V85 tmp78 [V85,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V86 tmp79 [V86 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V87 tmp80 [V87 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V88 tmp81 [V88,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V89 tmp82 [V89,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V90 tmp83 [V90 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V91 tmp84 [V91 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V92 tmp85 [V92 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V93 tmp86 [V93 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V94 tmp87 [V94,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V95 tmp88 [V95,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V96 tmp89 [V96 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V97 tmp90 [V97,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V98 tmp91 [V98,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V99 tmp92 [V99 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V100 tmp93 [V100,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V101 tmp94 [V101,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V102 tmp95 [V102 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V103 tmp96 [V103,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V104 tmp97 [V104,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V105 tmp98 [V105 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V106 tmp99 [V106 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V107 tmp100 [V107 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V108 tmp101 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V109 tmp102 [V109,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V110 tmp103 [V110,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V111 tmp104 [V111 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V112 tmp105 [V112,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V113 tmp106 [V113,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V114 tmp107 [V114 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V115 tmp108 [V115,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V116 tmp109 [V116,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V117 tmp110 [V117 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V118 tmp111 [V118,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V119 tmp112 [V119,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V120 tmp113 [V120,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V121 tmp114 [V121,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V122 tmp115 [V122,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp116 [V123,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V124 tmp117 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V125 tmp118 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp119 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp120 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp121 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp122 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp123 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp124 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp125 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp126 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp127 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp128 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp129 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp130 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp131 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp132 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp133 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp134 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp135 [V142,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+; V143 tmp136 [V143,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp137 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp138 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp139 [V146,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp140 [V147,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp141 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp142 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp143 [V150 ] ( 0, 0 ) simd32 -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V151 tmp144 [V151 ] ( 0, 0 ) simd32 -> zero-ref "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp145 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp146 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp147 [V154 ] ( 0, 0 ) simd32 -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp148 [V155 ] ( 0, 0 ) simd32 -> zero-ref "field V21._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp149 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp150 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp151 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp152 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp153 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp154 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp155 [V162,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+; V163 tmp156 [V163,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp157 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp158 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp159 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp160 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp161 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp162 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp163 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp164 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp165 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp166 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp167 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp168 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp169 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp170 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp171 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp172 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp173 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp174 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp175 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp176 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp177 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp178 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp179 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp180 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp181 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp182 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp183 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp184 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp185 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp186 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp187 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp188 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp189 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp190 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp191 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp192 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp193 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp194 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp195 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp196 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp197 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp198 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp199 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp200 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp201 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp202 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp203 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp204 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp205 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp206 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp207 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp208 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp209 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp210 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp211 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp212 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp213 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp214 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp215 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp216 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp217 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp218 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp219 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp220 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp221 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp222 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp223 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp224 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp225 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp226 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp227 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp228 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp229 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp230 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp231 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp232 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp233 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp234 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp235 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp236 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp237 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp238 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._upper (fldOffset=0x20)" P-INDEP
+; V246 tmp239 [V246,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V117._lower (fldOffset=0x0)" P-INDEP
+; V247 tmp240 [V247,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V117._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M35698_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M35698_IG02:
vpabsw ymm4, ymm0
vpabsw ymm5, ymm1
vpabsw ymm6, ymm2
vpabsw ymm7, ymm3
vpcmpeqw ymm8, ymm4, ymm6
vpcmpeqw ymm9, ymm5, ymm7
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm11, ymm10, ymm0
vpcmpgtw ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm2
- vpandn ymm11, ymm11, ymm0
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm3
- vpandn ymm10, ymm10, ymm1
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm3
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm0
+ vpand ymm10, ymm10, ymm1
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtw ymm12, ymm4, ymm6
vpcmpgtw ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm4, ymm10, ymm4
vpcmpgtw ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm6, ymm10, ymm6
vpcmpgtw ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M35698_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M35698_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M35698_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=5925748d) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=5925748d) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 17 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 34 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V17 tmp12 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V20 tmp15 [V20,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V21 tmp16 [V21,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V22 tmp17 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V23 tmp18 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V24 tmp19 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V25 tmp20 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V26 tmp21 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V27 tmp22 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V28 tmp23 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V32 tmp27 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V33 tmp28 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V35 tmp30 [V35,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V36 tmp31 [V36,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V38 tmp33 [V38,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V39 tmp34 [V39,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V41 tmp36 [V41,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V42 tmp37 [V42,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V44 tmp39 [V44,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V45 tmp40 [V45,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V48 tmp43 [V48,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V49 tmp44 [V49,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V20 tmp15 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V21 tmp16 [V21,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V22 tmp17 [V22,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V23 tmp18 [V23 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V24 tmp19 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V25 tmp20 [V25,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V26 tmp21 [V26,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V27 tmp22 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V28 tmp23 [V28,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V29 tmp24 [V29,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V34 tmp29 [V34,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V35 tmp30 [V35,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V39 tmp34 [V39 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V40 tmp35 [V40,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V41 tmp36 [V41,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V43 tmp38 [V43,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V44 tmp39 [V44,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V45 tmp40 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V46 tmp41 [V46,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V47 tmp42 [V47,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V48 tmp43 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V49 tmp44 [V49,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V50 tmp45 [V50,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
;* V51 tmp46 [V51 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V52 tmp47 [V52,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V53 tmp48 [V53,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V55 tmp50 [V55,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V56 tmp51 [V56,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V52 tmp47 [V52,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V53 tmp48 [V53,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V56 tmp51 [V56 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V57 tmp52 [V57 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V58 tmp53 [V58,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V59 tmp54 [V59,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V60 tmp55 [V60,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp56 [V61,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V62 tmp57 [V62,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V63 tmp58 [V63,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp59 [V64 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp60 [V65 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp61 [V66 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp62 [V67 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp80 [V85,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp84 [V89,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp88 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp92 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-; V103 tmp98 [V103,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp109 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp110 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp111 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp112 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp113 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp114 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp115 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp116 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
-;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
-;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
-; V126 tmp121 [V126,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V57._lower (fldOffset=0x0)" P-INDEP
-; V127 tmp122 [V127,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+; V58 tmp53 [V58,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V59 tmp54 [V59,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V61 tmp56 [V61,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V62 tmp57 [V62,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V63 tmp58 [V63 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V64 tmp59 [V64,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V65 tmp60 [V65,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V66 tmp61 [V66 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V67 tmp62 [V67,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V68 tmp63 [V68,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V69 tmp64 [V69 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V71 tmp66 [V71 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V72 tmp67 [V72 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V73 tmp68 [V73,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V74 tmp69 [V74,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V76 tmp71 [V76,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V77 tmp72 [V77,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V78 tmp73 [V78 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V79 tmp74 [V79,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V80 tmp75 [V80,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V81 tmp76 [V81 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V82 tmp77 [V82,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V83 tmp78 [V83,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V84 tmp79 [V84 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V86 tmp81 [V86,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V87 tmp82 [V87,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V90 tmp85 [V90,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V91 tmp86 [V91,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V92 tmp87 [V92 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V93 tmp88 [V93 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V94 tmp89 [V94 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V95 tmp90 [V95 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V96 tmp91 [V96,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V97 tmp92 [V97,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V98 tmp93 [V98 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V99 tmp94 [V99,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V100 tmp95 [V100,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V101 tmp96 [V101 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V102 tmp97 [V102,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V103 tmp98 [V103,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V104 tmp99 [V104 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V105 tmp100 [V105,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V106 tmp101 [V106,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V107 tmp102 [V107 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V108 tmp103 [V108 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V109 tmp104 [V109 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V110 tmp105 [V110 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V111 tmp106 [V111,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V112 tmp107 [V112,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V113 tmp108 [V113 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V114 tmp109 [V114,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V115 tmp110 [V115,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V116 tmp111 [V116 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V117 tmp112 [V117,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V118 tmp113 [V118,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V119 tmp114 [V119 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V120 tmp115 [V120,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V121 tmp116 [V121,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V122 tmp117 [V122,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp118 [V123,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V124 tmp119 [V124,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V125 tmp120 [V125,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp142 [V147,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp146 [V151,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp150 [V155 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp158 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+; V169 tmp164 [V169,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp168 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V63._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V63._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V66._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V66._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V78._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V78._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V81._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V81._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V84._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V84._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V101._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V101._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp235 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp236 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp237 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp238 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp239 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp240 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp241 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp242 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp243 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp244 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._upper (fldOffset=0x20)" P-INDEP
+;* V250 tmp245 [V250 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V116._lower (fldOffset=0x0)" P-INDEP
+;* V251 tmp246 [V251 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V116._upper (fldOffset=0x20)" P-INDEP
+; V252 tmp247 [V252,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V119._lower (fldOffset=0x0)" P-INDEP
+; V253 tmp248 [V253,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V119._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M29112_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M29112_IG02:
vpabsd ymm4, ymm0
vpabsd ymm5, ymm1
vpabsd ymm6, ymm2
vpabsd ymm7, ymm3
vpcmpeqd ymm8, ymm4, ymm6
vpcmpeqd ymm9, ymm5, ymm7
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm11, ymm10, ymm0
vpcmpgtd ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm2
- vpandn ymm11, ymm11, ymm0
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm3
- vpandn ymm10, ymm10, ymm1
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm3
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm0
+ vpand ymm10, ymm10, ymm1
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtd ymm12, ymm4, ymm6
vpcmpgtd ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm4, ymm10, ymm4
vpcmpgtd ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm6, ymm10, ymm6
vpcmpgtd ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M29112_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M29112_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M29112_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=a6808e47) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=a6808e47) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 17 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 34 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V17 tmp12 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V20 tmp15 [V20,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V21 tmp16 [V21,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V22 tmp17 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V23 tmp18 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V24 tmp19 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V25 tmp20 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V26 tmp21 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V27 tmp22 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V28 tmp23 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V32 tmp27 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V33 tmp28 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V35 tmp30 [V35,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V36 tmp31 [V36,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V38 tmp33 [V38,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V39 tmp34 [V39,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V41 tmp36 [V41,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V42 tmp37 [V42,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V44 tmp39 [V44,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V45 tmp40 [V45,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V48 tmp43 [V48,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V49 tmp44 [V49,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V20 tmp15 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V21 tmp16 [V21,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V22 tmp17 [V22,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V23 tmp18 [V23 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V24 tmp19 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V25 tmp20 [V25,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V26 tmp21 [V26,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V27 tmp22 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V28 tmp23 [V28,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V29 tmp24 [V29,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V34 tmp29 [V34,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V35 tmp30 [V35,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V39 tmp34 [V39 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V40 tmp35 [V40,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V41 tmp36 [V41,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V43 tmp38 [V43,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V44 tmp39 [V44,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V45 tmp40 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V46 tmp41 [V46,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V47 tmp42 [V47,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V48 tmp43 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V49 tmp44 [V49,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V50 tmp45 [V50,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
;* V51 tmp46 [V51 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V52 tmp47 [V52,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V53 tmp48 [V53,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V55 tmp50 [V55,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V56 tmp51 [V56,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V52 tmp47 [V52,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V53 tmp48 [V53,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V56 tmp51 [V56 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V57 tmp52 [V57 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V58 tmp53 [V58,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V59 tmp54 [V59,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V60 tmp55 [V60,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp56 [V61,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V62 tmp57 [V62,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V63 tmp58 [V63,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp59 [V64 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp60 [V65 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp61 [V66 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp62 [V67 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp80 [V85,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp84 [V89,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp88 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp92 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-; V103 tmp98 [V103,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp109 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp110 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp111 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp112 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp113 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp114 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp115 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp116 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
-;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
-;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
-; V126 tmp121 [V126,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V57._lower (fldOffset=0x0)" P-INDEP
-; V127 tmp122 [V127,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+; V58 tmp53 [V58,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V59 tmp54 [V59,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V61 tmp56 [V61,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V62 tmp57 [V62,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V63 tmp58 [V63 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V64 tmp59 [V64,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V65 tmp60 [V65,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V66 tmp61 [V66 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V67 tmp62 [V67,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V68 tmp63 [V68,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V69 tmp64 [V69 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V71 tmp66 [V71 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V72 tmp67 [V72 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V73 tmp68 [V73,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V74 tmp69 [V74,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V76 tmp71 [V76,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V77 tmp72 [V77,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V78 tmp73 [V78 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V79 tmp74 [V79,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V80 tmp75 [V80,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V81 tmp76 [V81 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V82 tmp77 [V82,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V83 tmp78 [V83,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V84 tmp79 [V84 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V86 tmp81 [V86,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V87 tmp82 [V87,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V90 tmp85 [V90,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V91 tmp86 [V91,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V92 tmp87 [V92 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V93 tmp88 [V93 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V94 tmp89 [V94 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V95 tmp90 [V95 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V96 tmp91 [V96,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V97 tmp92 [V97,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V98 tmp93 [V98 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V99 tmp94 [V99,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V100 tmp95 [V100,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V101 tmp96 [V101 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V102 tmp97 [V102,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V103 tmp98 [V103,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V104 tmp99 [V104 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V105 tmp100 [V105,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V106 tmp101 [V106,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V107 tmp102 [V107 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V108 tmp103 [V108 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V109 tmp104 [V109 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V110 tmp105 [V110 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V111 tmp106 [V111,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V112 tmp107 [V112,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V113 tmp108 [V113 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V114 tmp109 [V114,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V115 tmp110 [V115,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V116 tmp111 [V116 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V117 tmp112 [V117,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V118 tmp113 [V118,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V119 tmp114 [V119 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V120 tmp115 [V120,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V121 tmp116 [V121,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V122 tmp117 [V122,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp118 [V123,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V124 tmp119 [V124,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V125 tmp120 [V125,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp142 [V147,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp146 [V151,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp150 [V155 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp158 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+; V169 tmp164 [V169,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp168 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V63._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V63._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V66._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V66._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V78._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V78._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V81._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V81._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V84._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V84._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V101._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V101._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp235 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp236 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp237 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp238 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp239 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp240 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp241 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp242 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp243 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp244 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._upper (fldOffset=0x20)" P-INDEP
+;* V250 tmp245 [V250 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V116._lower (fldOffset=0x0)" P-INDEP
+;* V251 tmp246 [V251 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V116._upper (fldOffset=0x20)" P-INDEP
+; V252 tmp247 [V252,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V119._lower (fldOffset=0x0)" P-INDEP
+; V253 tmp248 [V253,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V119._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M57336_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x10]
vmovups ymm1, ymmword ptr [rbp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x50]
vmovups ymm3, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M57336_IG02:
vpabsw ymm4, ymm0
vpabsw ymm5, ymm1
vpabsw ymm6, ymm2
vpabsw ymm7, ymm3
vpcmpeqw ymm8, ymm4, ymm6
vpcmpeqw ymm9, ymm5, ymm7
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm11, ymm10, ymm0
vpcmpgtw ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm2
- vpandn ymm11, ymm11, ymm0
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm3
- vpandn ymm10, ymm10, ymm1
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm3
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm0
+ vpand ymm10, ymm10, ymm1
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtw ymm12, ymm4, ymm6
vpcmpgtw ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm4, ymm10, ymm4
vpcmpgtw ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm6, ymm10, ymm6
vpcmpgtw ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M57336_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M57336_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M57336_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=c6192007) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=c6192007) for method System.Numerics.Tensors.TensorPrimitives+MaxMagnitudePropagateNaNOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 16 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 33 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V05 loc2 [V05 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V06 loc3 [V06 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;# V07 OutArgs [V07 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V08 tmp1 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V09 tmp2 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V10 tmp3 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V11 tmp4 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V12 tmp5 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V13 tmp6 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V14 tmp7 [V14 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V15 tmp8 [V15 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V16 tmp9 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V18 tmp11 [V18,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V19 tmp12 [V19,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V20 tmp13 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V21 tmp14 [V21,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V22 tmp15 [V22,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V23 tmp16 [V23 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V24 tmp17 [V24,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V25 tmp18 [V25,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V26 tmp19 [V26 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V27 tmp20 [V27 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V30 tmp23 [V30,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V31 tmp24 [V31,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V33 tmp26 [V33,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V34 tmp27 [V34,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V36 tmp29 [V36,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V37 tmp30 [V37,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V38 tmp31 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V39 tmp32 [V39,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V40 tmp33 [V40,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V41 tmp34 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V42 tmp35 [V42,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V43 tmp36 [V43,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V44 tmp37 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V45 tmp38 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V46 tmp39 [V46,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V47 tmp40 [V47,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V48 tmp41 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V18 tmp11 [V18 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V19 tmp12 [V19,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V20 tmp13 [V20,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V21 tmp14 [V21 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V22 tmp15 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V23 tmp16 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V24 tmp17 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V25 tmp18 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V26 tmp19 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V27 tmp20 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V30 tmp23 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V31 tmp24 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V32 tmp25 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V33 tmp26 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V34 tmp27 [V34 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V36 tmp29 [V36 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V37 tmp30 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V38 tmp31 [V38,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V39 tmp32 [V39,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V40 tmp33 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V41 tmp34 [V41,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V42 tmp35 [V42,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V43 tmp36 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V44 tmp37 [V44,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V45 tmp38 [V45,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V46 tmp39 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V47 tmp40 [V47,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V48 tmp41 [V48,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
;* V49 tmp42 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V50 tmp43 [V50,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V51 tmp44 [V51,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V53 tmp46 [V53,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V54 tmp47 [V54,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V50 tmp43 [V50,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V51 tmp44 [V51,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V53 tmp46 [V53 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V54 tmp47 [V54 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V55 tmp48 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V58 tmp51 [V58,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V59 tmp52 [V59,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V60 tmp53 [V60,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp54 [V61,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V62 tmp55 [V62 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V63 tmp56 [V63 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp57 [V64 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp58 [V65 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp59 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp60 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp61 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp62 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp63 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp64 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp65 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp66 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp67 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp68 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp69 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp70 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp71 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp72 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp73 [V80,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-; V81 tmp74 [V81,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp75 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp76 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp77 [V84,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp78 [V85,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp79 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp80 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp81 [V88 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V89 tmp82 [V89 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp83 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp84 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp85 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp86 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp87 [V94 ] ( 0, 0 ) simd32 -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp88 [V95 ] ( 0, 0 ) simd32 -> zero-ref "field V26._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp89 [V96,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-; V97 tmp90 [V97,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp91 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp92 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp93 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp94 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp95 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp96 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp97 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp98 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp99 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp100 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp101 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp102 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp103 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp104 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp105 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp106 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp107 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp108 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp109 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp110 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp111 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp112 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
-; V120 tmp113 [V120,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V55._lower (fldOffset=0x0)" P-INDEP
-; V121 tmp114 [V121,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V58 tmp51 [V58 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V59 tmp52 [V59,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V60 tmp53 [V60,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V61 tmp54 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V62 tmp55 [V62,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V63 tmp56 [V63,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V64 tmp57 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V65 tmp58 [V65,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V66 tmp59 [V66,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V67 tmp60 [V67 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V68 tmp61 [V68 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V69 tmp62 [V69 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V70 tmp63 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V71 tmp64 [V71,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V72 tmp65 [V72,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V73 tmp66 [V73 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V74 tmp67 [V74,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V75 tmp68 [V75,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V76 tmp69 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V77 tmp70 [V77,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V78 tmp71 [V78,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V79 tmp72 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V80 tmp73 [V80,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V81 tmp74 [V81,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V82 tmp75 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V83 tmp76 [V83 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V84 tmp77 [V84,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V85 tmp78 [V85,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V86 tmp79 [V86 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V87 tmp80 [V87 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V88 tmp81 [V88,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V89 tmp82 [V89,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V90 tmp83 [V90 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V91 tmp84 [V91 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V92 tmp85 [V92 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V93 tmp86 [V93 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V94 tmp87 [V94,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V95 tmp88 [V95,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V96 tmp89 [V96 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V97 tmp90 [V97,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V98 tmp91 [V98,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V99 tmp92 [V99 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V100 tmp93 [V100,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V101 tmp94 [V101,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V102 tmp95 [V102 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V103 tmp96 [V103,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V104 tmp97 [V104,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V105 tmp98 [V105 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V106 tmp99 [V106 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V107 tmp100 [V107 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V108 tmp101 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V109 tmp102 [V109,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V110 tmp103 [V110,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V111 tmp104 [V111 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V112 tmp105 [V112,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V113 tmp106 [V113,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V114 tmp107 [V114 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V115 tmp108 [V115,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V116 tmp109 [V116,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V117 tmp110 [V117 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V118 tmp111 [V118,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V119 tmp112 [V119,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V120 tmp113 [V120,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V121 tmp114 [V121,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V122 tmp115 [V122,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp116 [V123,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V124 tmp117 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V125 tmp118 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp119 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp120 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp121 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp122 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp123 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp124 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp125 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp126 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp127 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp128 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp129 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp130 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp131 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp132 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp133 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp134 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp135 [V142,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+; V143 tmp136 [V143,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp137 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp138 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp139 [V146,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp140 [V147,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp141 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp142 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp143 [V150 ] ( 0, 0 ) simd32 -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V151 tmp144 [V151 ] ( 0, 0 ) simd32 -> zero-ref "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp145 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp146 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp147 [V154 ] ( 0, 0 ) simd32 -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp148 [V155 ] ( 0, 0 ) simd32 -> zero-ref "field V21._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp149 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp150 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp151 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp152 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp153 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp154 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp155 [V162,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+; V163 tmp156 [V163,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp157 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp158 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp159 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp160 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp161 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp162 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp163 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp164 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp165 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp166 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp167 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp168 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp169 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp170 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp171 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp172 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp173 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp174 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp175 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp176 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp177 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp178 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp179 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp180 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp181 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp182 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp183 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp184 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp185 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp186 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp187 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp188 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp189 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp190 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp191 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp192 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp193 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp194 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp195 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp196 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp197 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp198 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp199 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp200 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp201 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp202 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp203 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp204 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp205 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp206 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp207 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp208 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp209 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp210 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp211 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp212 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp213 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp214 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp215 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp216 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp217 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp218 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp219 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp220 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp221 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp222 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp223 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp224 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp225 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp226 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp227 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp228 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp229 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp230 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp231 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp232 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp233 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp234 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp235 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp236 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp237 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp238 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._upper (fldOffset=0x20)" P-INDEP
+; V246 tmp239 [V246,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V117._lower (fldOffset=0x0)" P-INDEP
+; V247 tmp240 [V247,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V117._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M35308_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x10]
vmovups ymm3, ymmword ptr [rbp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x50]
vmovups ymm1, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M35308_IG02:
vpabsd ymm4, ymm2
vpabsd ymm5, ymm3
vpabsd ymm6, ymm0
vpabsd ymm7, ymm1
vpcmpeqd ymm8, ymm6, ymm4
vpcmpeqd ymm9, ymm7, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm11, ymm10, ymm0
vpcmpgtd ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm0
- vpandn ymm11, ymm11, ymm2
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm1
- vpandn ymm10, ymm10, ymm3
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm1
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm2
+ vpand ymm10, ymm10, ymm3
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtd ymm12, ymm4, ymm6
vpcmpgtd ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm4, ymm10, ymm4
vpcmpgtd ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm6, ymm10, ymm6
vpcmpgtd ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M35308_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M35308_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M35308_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=852e7613) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=852e7613) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 16 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 33 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[short]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V05 loc2 [V05 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;* V06 loc3 [V06 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[short]>
;# V07 OutArgs [V07 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V08 tmp1 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V09 tmp2 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V10 tmp3 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V11 tmp4 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V12 tmp5 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V13 tmp6 [V13 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V14 tmp7 [V14 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V15 tmp8 [V15 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V16 tmp9 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V18 tmp11 [V18,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V19 tmp12 [V19,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V20 tmp13 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V21 tmp14 [V21,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V22 tmp15 [V22,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V23 tmp16 [V23 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V24 tmp17 [V24,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V25 tmp18 [V25,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V26 tmp19 [V26 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V27 tmp20 [V27 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V30 tmp23 [V30,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V31 tmp24 [V31,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V32 tmp25 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V33 tmp26 [V33,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V34 tmp27 [V34,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V36 tmp29 [V36,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V37 tmp30 [V37,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V38 tmp31 [V38 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V39 tmp32 [V39,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V40 tmp33 [V40,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V41 tmp34 [V41 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V42 tmp35 [V42,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V43 tmp36 [V43,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V44 tmp37 [V44 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-;* V45 tmp38 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V46 tmp39 [V46,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V47 tmp40 [V47,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V48 tmp41 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V17 tmp10 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V18 tmp11 [V18 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V19 tmp12 [V19,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V20 tmp13 [V20,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V21 tmp14 [V21 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V22 tmp15 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V23 tmp16 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V24 tmp17 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V25 tmp18 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V26 tmp19 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V27 tmp20 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V28 tmp21 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V29 tmp22 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V30 tmp23 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V31 tmp24 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V32 tmp25 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V33 tmp26 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V34 tmp27 [V34 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V35 tmp28 [V35 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V36 tmp29 [V36 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V37 tmp30 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V38 tmp31 [V38,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V39 tmp32 [V39,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V40 tmp33 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V41 tmp34 [V41,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V42 tmp35 [V42,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V43 tmp36 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V44 tmp37 [V44,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V45 tmp38 [V45,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V46 tmp39 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V47 tmp40 [V47,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V48 tmp41 [V48,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
;* V49 tmp42 [V49 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V50 tmp43 [V50,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V51 tmp44 [V51,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V53 tmp46 [V53,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V54 tmp47 [V54,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V50 tmp43 [V50,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V51 tmp44 [V51,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V52 tmp45 [V52 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V53 tmp46 [V53 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V54 tmp47 [V54 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
;* V55 tmp48 [V55 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
-; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
-; V58 tmp51 [V58,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V59 tmp52 [V59,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V60 tmp53 [V60,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp54 [V61,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V62 tmp55 [V62 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V63 tmp56 [V63 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp57 [V64 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp58 [V65 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp59 [V66 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp60 [V67 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp61 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp62 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp63 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp64 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp65 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp66 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp67 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp68 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp69 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp70 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp71 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp72 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp73 [V80,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-; V81 tmp74 [V81,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp75 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp76 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp77 [V84,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp78 [V85,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp79 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp80 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp81 [V88 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V89 tmp82 [V89 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp83 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp84 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp85 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp86 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V23._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp87 [V94 ] ( 0, 0 ) simd32 -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp88 [V95 ] ( 0, 0 ) simd32 -> zero-ref "field V26._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp89 [V96,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
-; V97 tmp90 [V97,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V27._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp91 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp92 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp93 [V100 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp94 [V101 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp95 [V102 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
-;* V103 tmp96 [V103 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp97 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp98 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp99 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp100 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp101 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp102 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V41._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp103 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp104 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V44._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp105 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp106 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp107 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp108 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp109 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp110 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp111 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp112 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
-; V120 tmp113 [V120,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V55._lower (fldOffset=0x0)" P-INDEP
-; V121 tmp114 [V121,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+; V56 tmp49 [V56,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V57 tmp50 [V57,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V58 tmp51 [V58 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V59 tmp52 [V59,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V60 tmp53 [V60,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V61 tmp54 [V61 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V62 tmp55 [V62,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V63 tmp56 [V63,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V64 tmp57 [V64 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V65 tmp58 [V65,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V66 tmp59 [V66,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V67 tmp60 [V67 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V68 tmp61 [V68 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V69 tmp62 [V69 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V70 tmp63 [V70 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V71 tmp64 [V71,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V72 tmp65 [V72,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V73 tmp66 [V73 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V74 tmp67 [V74,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V75 tmp68 [V75,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V76 tmp69 [V76 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V77 tmp70 [V77,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V78 tmp71 [V78,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V79 tmp72 [V79 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V80 tmp73 [V80,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V81 tmp74 [V81,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V82 tmp75 [V82 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V83 tmp76 [V83 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V84 tmp77 [V84,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V85 tmp78 [V85,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V86 tmp79 [V86 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V87 tmp80 [V87 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V88 tmp81 [V88,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V89 tmp82 [V89,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V90 tmp83 [V90 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V91 tmp84 [V91 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V92 tmp85 [V92 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V93 tmp86 [V93 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V94 tmp87 [V94,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V95 tmp88 [V95,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V96 tmp89 [V96 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V97 tmp90 [V97,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V98 tmp91 [V98,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V99 tmp92 [V99 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V100 tmp93 [V100,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V101 tmp94 [V101,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V102 tmp95 [V102 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V103 tmp96 [V103,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V104 tmp97 [V104,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V105 tmp98 [V105 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V106 tmp99 [V106 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V107 tmp100 [V107 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[short]>
+;* V108 tmp101 [V108 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V109 tmp102 [V109,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V110 tmp103 [V110,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V111 tmp104 [V111 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V112 tmp105 [V112,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V113 tmp106 [V113,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V114 tmp107 [V114 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V115 tmp108 [V115,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V116 tmp109 [V116,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+;* V117 tmp110 [V117 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[short]>
+; V118 tmp111 [V118,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V119 tmp112 [V119,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[short]>
+; V120 tmp113 [V120,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V121 tmp114 [V121,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V122 tmp115 [V122,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp116 [V123,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V124 tmp117 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V125 tmp118 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp119 [V126 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp120 [V127 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp121 [V128 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp122 [V129 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V05._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp123 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp124 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp125 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp126 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp127 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp128 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp129 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp130 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp131 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp132 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp133 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp134 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp135 [V142,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+; V143 tmp136 [V143,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp137 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp138 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp139 [V146,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp140 [V147,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp141 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp142 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp143 [V150 ] ( 0, 0 ) simd32 -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V151 tmp144 [V151 ] ( 0, 0 ) simd32 -> zero-ref "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp145 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp146 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp147 [V154 ] ( 0, 0 ) simd32 -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp148 [V155 ] ( 0, 0 ) simd32 -> zero-ref "field V21._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp149 [V156 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp150 [V157 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp151 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp152 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp153 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp154 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp155 [V162,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
+; V163 tmp156 [V163,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp157 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp158 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp159 [V166 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp160 [V167 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp161 [V168 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
+;* V169 tmp162 [V169 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp163 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp164 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V35._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp165 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp166 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp167 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp168 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp169 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp170 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp171 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp172 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp173 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp174 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp175 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp176 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V49._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp177 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp178 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V52._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp179 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp180 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V53._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp181 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp182 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp183 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp184 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp185 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp186 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V58._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp187 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp188 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V61._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp189 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp190 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V64._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp191 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp192 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V67._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp193 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp194 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V68._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp195 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp196 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp197 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp198 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp199 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp200 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V73._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp201 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp202 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V76._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp203 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp204 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V79._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp205 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp206 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V82._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp207 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp208 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V83._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp209 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp210 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V86._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp211 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp212 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V87._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp213 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp214 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V90._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp215 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp216 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V91._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp217 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp218 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp219 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp220 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp221 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp222 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V96._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp223 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp224 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V99._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp225 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp226 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V102._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp227 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp228 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V105._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp229 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp230 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V106._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp231 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp232 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp233 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp234 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp235 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp236 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V111._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp237 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp238 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V114._upper (fldOffset=0x20)" P-INDEP
+; V246 tmp239 [V246,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V117._lower (fldOffset=0x0)" P-INDEP
+; V247 tmp240 [V247,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V117._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M50988_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x10]
vmovups ymm3, ymmword ptr [rbp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x50]
vmovups ymm1, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M50988_IG02:
vpabsw ymm4, ymm2
vpabsw ymm5, ymm3
vpabsw ymm6, ymm0
vpabsw ymm7, ymm1
vpcmpeqw ymm8, ymm6, ymm4
vpcmpeqw ymm9, ymm7, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm11, ymm10, ymm0
vpcmpgtw ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm0
- vpandn ymm11, ymm11, ymm2
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm1
- vpandn ymm10, ymm10, ymm3
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm1
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm2
+ vpand ymm10, ymm10, ymm3
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtw ymm12, ymm4, ymm6
vpcmpgtw ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm4, ymm10, ymm4
vpcmpgtw ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtw ymm6, ymm10, ymm6
vpcmpgtw ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M50988_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M50988_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M50988_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=c33d38d3) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=c33d38d3) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudeOperator`1[short]:Invoke(System.Runtime.Intrinsics.Vector512`1[short],System.Runtime.Intrinsics.Vector512`1[short]):System.Runtime.Intrinsics.Vector512`1[short] (FullOpts)79 (31.85 % of base) - System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int]
; Assembly listing for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
; Emitting BLENDED_CODE for X64 with AVX - Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
-; 0 inlinees with PGO data; 51 single block inlinees; 17 inlinees without PGO data
+; 0 inlinees with PGO data; 114 single block inlinees; 34 inlinees without PGO data
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 5, 5 ) byref -> rdi single-def
;* V01 arg0 [V01 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V02 arg1 [V02 ] ( 0, 0 ) struct (64) zero-ref single-def <System.Runtime.Intrinsics.Vector512`1[int]>
;* V03 loc0 [V03 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;* V04 loc1 [V04 ] ( 0, 0 ) struct (64) zero-ref <System.Runtime.Intrinsics.Vector512`1[int]>
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V07 tmp2 [V07 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V08 tmp3 [V08 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V09 tmp4 [V09 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V10 tmp5 [V10 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V11 tmp6 [V11 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V12 tmp7 [V12 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V13 tmp8 [V13 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V15 tmp10 [V15 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V16 tmp11 [V16 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V17 tmp12 [V17 ] ( 0, 0 ) struct (64) zero-ref "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V18 tmp13 [V18 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V20 tmp15 [V20,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V21 tmp16 [V21,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V22 tmp17 [V22 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V23 tmp18 [V23,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V24 tmp19 [V24,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V25 tmp20 [V25 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V26 tmp21 [V26,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V27 tmp22 [V27,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V28 tmp23 [V28 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V29 tmp24 [V29 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V32 tmp27 [V32,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V33 tmp28 [V33,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V34 tmp29 [V34 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V35 tmp30 [V35,T19] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V36 tmp31 [V36,T20] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V38 tmp33 [V38,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V39 tmp34 [V39,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V40 tmp35 [V40 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V41 tmp36 [V41,T21] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V42 tmp37 [V42,T22] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V43 tmp38 [V43 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V44 tmp39 [V44,T23] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V45 tmp40 [V45,T24] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V46 tmp41 [V46 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-;* V47 tmp42 [V47 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V48 tmp43 [V48,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V49 tmp44 [V49,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V50 tmp45 [V50 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V19 tmp14 [V19 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V20 tmp15 [V20 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V21 tmp16 [V21,T01] ( 4, 8 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V22 tmp17 [V22,T02] ( 4, 8 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V23 tmp18 [V23 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V24 tmp19 [V24 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V25 tmp20 [V25,T03] ( 4, 8 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V26 tmp21 [V26,T04] ( 4, 8 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V27 tmp22 [V27 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V28 tmp23 [V28,T05] ( 3, 6 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V29 tmp24 [V29,T06] ( 3, 6 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V30 tmp25 [V30 ] ( 0, 0 ) struct (64) zero-ref "Inline return value spill temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V31 tmp26 [V31 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V32 tmp27 [V32 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V33 tmp28 [V33 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V34 tmp29 [V34,T07] ( 3, 6 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V35 tmp30 [V35,T08] ( 3, 6 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V36 tmp31 [V36 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V37 tmp32 [V37 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V38 tmp33 [V38 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V39 tmp34 [V39 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V40 tmp35 [V40,T19] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V41 tmp36 [V41,T20] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V42 tmp37 [V42 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V43 tmp38 [V43,T21] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V44 tmp39 [V44,T22] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V45 tmp40 [V45 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V46 tmp41 [V46,T23] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V47 tmp42 [V47,T24] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V48 tmp43 [V48 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V49 tmp44 [V49,T25] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V50 tmp45 [V50,T26] ( 2, 4 ) simd32 -> [rbp-0x30] spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
;* V51 tmp46 [V51 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V52 tmp47 [V52,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V53 tmp48 [V53,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V55 tmp50 [V55,T25] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V56 tmp51 [V56,T26] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V52 tmp47 [V52,T09] ( 3, 6 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V53 tmp48 [V53,T10] ( 3, 6 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V54 tmp49 [V54 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V55 tmp50 [V55 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V56 tmp51 [V56 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
;* V57 tmp52 [V57 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
-; V58 tmp53 [V58,T27] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V59 tmp54 [V59,T28] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
-; V60 tmp55 [V60,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
-; V61 tmp56 [V61,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
-; V62 tmp57 [V62,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
-; V63 tmp58 [V63,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
-;* V64 tmp59 [V64 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
-;* V65 tmp60 [V65 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
-;* V66 tmp61 [V66 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
-;* V67 tmp62 [V67 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
-;* V68 tmp63 [V68 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
-;* V69 tmp64 [V69 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
-;* V70 tmp65 [V70 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
-;* V71 tmp66 [V71 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
-;* V72 tmp67 [V72 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
-;* V73 tmp68 [V73 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
-;* V74 tmp69 [V74 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
-;* V75 tmp70 [V75 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
-;* V76 tmp71 [V76 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
-;* V77 tmp72 [V77 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
-;* V78 tmp73 [V78 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
-;* V79 tmp74 [V79 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
-;* V80 tmp75 [V80 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
-;* V81 tmp76 [V81 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
-;* V82 tmp77 [V82 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
-;* V83 tmp78 [V83 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
-;* V84 tmp79 [V84,T34] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
-; V85 tmp80 [V85,T29] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
-;* V86 tmp81 [V86 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
-;* V87 tmp82 [V87 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
-;* V88 tmp83 [V88,T35] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
-; V89 tmp84 [V89,T30] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
-;* V90 tmp85 [V90 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
-;* V91 tmp86 [V91 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
-;* V92 tmp87 [V92 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
-;* V93 tmp88 [V93 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
-;* V94 tmp89 [V94 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._lower (fldOffset=0x0)" P-INDEP
-;* V95 tmp90 [V95 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V19._upper (fldOffset=0x20)" P-INDEP
-;* V96 tmp91 [V96 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._lower (fldOffset=0x0)" P-INDEP
-;* V97 tmp92 [V97 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V22._upper (fldOffset=0x20)" P-INDEP
-;* V98 tmp93 [V98 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._lower (fldOffset=0x0)" P-INDEP
-;* V99 tmp94 [V99 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V25._upper (fldOffset=0x20)" P-INDEP
-;* V100 tmp95 [V100 ] ( 0, 0 ) simd32 -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP
-;* V101 tmp96 [V101 ] ( 0, 0 ) simd32 -> zero-ref "field V28._upper (fldOffset=0x20)" P-INDEP
-;* V102 tmp97 [V102,T36] ( 0, 0 ) simd32 -> zero-ref single-def "field V29._lower (fldOffset=0x0)" P-INDEP
-; V103 tmp98 [V103,T31] ( 3, 3 ) simd32 -> mm10 single-def "field V29._upper (fldOffset=0x20)" P-INDEP
-;* V104 tmp99 [V104 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._lower (fldOffset=0x0)" P-INDEP
-;* V105 tmp100 [V105 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V30._upper (fldOffset=0x20)" P-INDEP
-;* V106 tmp101 [V106 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
-;* V107 tmp102 [V107 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._upper (fldOffset=0x20)" P-INDEP
-;* V108 tmp103 [V108 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._lower (fldOffset=0x0)" P-INDEP
-;* V109 tmp104 [V109 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V34._upper (fldOffset=0x20)" P-INDEP
-;* V110 tmp105 [V110 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
-;* V111 tmp106 [V111 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
-;* V112 tmp107 [V112 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._lower (fldOffset=0x0)" P-INDEP
-;* V113 tmp108 [V113 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V40._upper (fldOffset=0x20)" P-INDEP
-;* V114 tmp109 [V114 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._lower (fldOffset=0x0)" P-INDEP
-;* V115 tmp110 [V115 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V43._upper (fldOffset=0x20)" P-INDEP
-;* V116 tmp111 [V116 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._lower (fldOffset=0x0)" P-INDEP
-;* V117 tmp112 [V117 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V46._upper (fldOffset=0x20)" P-INDEP
-;* V118 tmp113 [V118 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._lower (fldOffset=0x0)" P-INDEP
-;* V119 tmp114 [V119 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V47._upper (fldOffset=0x20)" P-INDEP
-;* V120 tmp115 [V120 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._lower (fldOffset=0x0)" P-INDEP
-;* V121 tmp116 [V121 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V50._upper (fldOffset=0x20)" P-INDEP
-;* V122 tmp117 [V122 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
-;* V123 tmp118 [V123 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
-;* V124 tmp119 [V124 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
-;* V125 tmp120 [V125 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
-; V126 tmp121 [V126,T32] ( 2, 2 ) simd32 -> mm0 single-def "field V57._lower (fldOffset=0x0)" P-INDEP
-; V127 tmp122 [V127,T33] ( 2, 2 ) simd32 -> mm1 single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+; V58 tmp53 [V58,T27] ( 2, 4 ) simd32 -> mm14 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V59 tmp54 [V59,T28] ( 2, 4 ) simd32 -> mm15 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V60 tmp55 [V60 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V61 tmp56 [V61,T29] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V62 tmp57 [V62,T30] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V63 tmp58 [V63 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V64 tmp59 [V64,T31] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V65 tmp60 [V65,T32] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V66 tmp61 [V66 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V67 tmp62 [V67,T33] ( 2, 4 ) simd32 -> mm10 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V68 tmp63 [V68,T34] ( 2, 4 ) simd32 -> mm12 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V69 tmp64 [V69 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V70 tmp65 [V70 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V71 tmp66 [V71 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V72 tmp67 [V72 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V73 tmp68 [V73,T35] ( 2, 4 ) simd32 -> mm11 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V74 tmp69 [V74,T36] ( 2, 4 ) simd32 -> mm13 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V75 tmp70 [V75 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V76 tmp71 [V76,T37] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V77 tmp72 [V77,T38] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V78 tmp73 [V78 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V79 tmp74 [V79,T39] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V80 tmp75 [V80,T40] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V81 tmp76 [V81 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V82 tmp77 [V82,T41] ( 2, 4 ) simd32 -> mm8 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V83 tmp78 [V83,T42] ( 2, 4 ) simd32 -> mm9 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V84 tmp79 [V84 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V85 tmp80 [V85 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V86 tmp81 [V86,T11] ( 3, 6 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V87 tmp82 [V87,T12] ( 3, 6 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V88 tmp83 [V88 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V89 tmp84 [V89 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V90 tmp85 [V90,T13] ( 3, 6 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V91 tmp86 [V91,T14] ( 3, 6 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V92 tmp87 [V92 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V93 tmp88 [V93 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V94 tmp89 [V94 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V95 tmp90 [V95 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V96 tmp91 [V96,T43] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V97 tmp92 [V97,T44] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V98 tmp93 [V98 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V99 tmp94 [V99,T45] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V100 tmp95 [V100,T46] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V101 tmp96 [V101 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V102 tmp97 [V102,T47] ( 2, 4 ) simd32 -> mm6 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V103 tmp98 [V103,T48] ( 2, 4 ) simd32 -> mm7 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V104 tmp99 [V104 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V105 tmp100 [V105,T49] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V106 tmp101 [V106,T50] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V107 tmp102 [V107 ] ( 0, 0 ) struct (64) zero-ref "impAppendStmt" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V108 tmp103 [V108 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V109 tmp104 [V109 ] ( 0, 0 ) struct (64) zero-ref "spilled call-like call argument" <System.Runtime.Intrinsics.Vector512`1[int]>
+;* V110 tmp105 [V110 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V111 tmp106 [V111,T51] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V112 tmp107 [V112,T52] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V113 tmp108 [V113 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V114 tmp109 [V114,T53] ( 2, 4 ) simd32 -> mm4 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V115 tmp110 [V115,T54] ( 2, 4 ) simd32 -> mm5 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V116 tmp111 [V116 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V117 tmp112 [V117,T55] ( 2, 4 ) simd32 -> mm2 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V118 tmp113 [V118,T56] ( 2, 4 ) simd32 -> mm3 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+;* V119 tmp114 [V119 ] ( 0, 0 ) struct (64) zero-ref ld-addr-op "Inline ldloca(s) first use temp" <System.Runtime.Intrinsics.Vector512`1[int]>
+; V120 tmp115 [V120,T57] ( 2, 4 ) simd32 -> mm0 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V121 tmp116 [V121,T58] ( 2, 4 ) simd32 -> mm1 "Inlining Arg" <System.Runtime.Intrinsics.Vector256`1[int]>
+; V122 tmp117 [V122,T17] ( 4, 4 ) simd32 -> mm2 single-def "field V01._lower (fldOffset=0x0)" P-INDEP
+; V123 tmp118 [V123,T18] ( 4, 4 ) simd32 -> mm3 single-def "field V01._upper (fldOffset=0x20)" P-INDEP
+; V124 tmp119 [V124,T15] ( 5, 5 ) simd32 -> mm0 single-def "field V02._lower (fldOffset=0x0)" P-INDEP
+; V125 tmp120 [V125,T16] ( 5, 5 ) simd32 -> mm1 single-def "field V02._upper (fldOffset=0x20)" P-INDEP
+;* V126 tmp121 [V126 ] ( 0, 0 ) simd32 -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP
+;* V127 tmp122 [V127 ] ( 0, 0 ) simd32 -> zero-ref "field V03._upper (fldOffset=0x20)" P-INDEP
+;* V128 tmp123 [V128 ] ( 0, 0 ) simd32 -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP
+;* V129 tmp124 [V129 ] ( 0, 0 ) simd32 -> zero-ref "field V04._upper (fldOffset=0x20)" P-INDEP
+;* V130 tmp125 [V130 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._lower (fldOffset=0x0)" P-INDEP
+;* V131 tmp126 [V131 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V06._upper (fldOffset=0x20)" P-INDEP
+;* V132 tmp127 [V132 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._lower (fldOffset=0x0)" P-INDEP
+;* V133 tmp128 [V133 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V07._upper (fldOffset=0x20)" P-INDEP
+;* V134 tmp129 [V134 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._lower (fldOffset=0x0)" P-INDEP
+;* V135 tmp130 [V135 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V08._upper (fldOffset=0x20)" P-INDEP
+;* V136 tmp131 [V136 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._lower (fldOffset=0x0)" P-INDEP
+;* V137 tmp132 [V137 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V09._upper (fldOffset=0x20)" P-INDEP
+;* V138 tmp133 [V138 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._lower (fldOffset=0x0)" P-INDEP
+;* V139 tmp134 [V139 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V10._upper (fldOffset=0x20)" P-INDEP
+;* V140 tmp135 [V140 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._lower (fldOffset=0x0)" P-INDEP
+;* V141 tmp136 [V141 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V11._upper (fldOffset=0x20)" P-INDEP
+;* V142 tmp137 [V142 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._lower (fldOffset=0x0)" P-INDEP
+;* V143 tmp138 [V143 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V12._upper (fldOffset=0x20)" P-INDEP
+;* V144 tmp139 [V144 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._lower (fldOffset=0x0)" P-INDEP
+;* V145 tmp140 [V145 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V13._upper (fldOffset=0x20)" P-INDEP
+;* V146 tmp141 [V146,T64] ( 0, 0 ) simd32 -> zero-ref single-def "field V14._lower (fldOffset=0x0)" P-INDEP
+; V147 tmp142 [V147,T59] ( 3, 3 ) simd32 -> mm10 single-def "field V14._upper (fldOffset=0x20)" P-INDEP
+;* V148 tmp143 [V148 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._lower (fldOffset=0x0)" P-INDEP
+;* V149 tmp144 [V149 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V15._upper (fldOffset=0x20)" P-INDEP
+;* V150 tmp145 [V150,T65] ( 0, 0 ) simd32 -> zero-ref single-def "field V16._lower (fldOffset=0x0)" P-INDEP
+; V151 tmp146 [V151,T60] ( 3, 3 ) simd32 -> mm10 single-def "field V16._upper (fldOffset=0x20)" P-INDEP
+;* V152 tmp147 [V152 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._lower (fldOffset=0x0)" P-INDEP
+;* V153 tmp148 [V153 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V17._upper (fldOffset=0x20)" P-INDEP
+;* V154 tmp149 [V154 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._lower (fldOffset=0x0)" P-INDEP
+;* V155 tmp150 [V155 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V18._upper (fldOffset=0x20)" P-INDEP
+;* V156 tmp151 [V156 ] ( 0, 0 ) simd32 -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP
+;* V157 tmp152 [V157 ] ( 0, 0 ) simd32 -> zero-ref "field V19._upper (fldOffset=0x20)" P-INDEP
+;* V158 tmp153 [V158 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._lower (fldOffset=0x0)" P-INDEP
+;* V159 tmp154 [V159 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V20._upper (fldOffset=0x20)" P-INDEP
+;* V160 tmp155 [V160 ] ( 0, 0 ) simd32 -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP
+;* V161 tmp156 [V161 ] ( 0, 0 ) simd32 -> zero-ref "field V23._upper (fldOffset=0x20)" P-INDEP
+;* V162 tmp157 [V162 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._lower (fldOffset=0x0)" P-INDEP
+;* V163 tmp158 [V163 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V24._upper (fldOffset=0x20)" P-INDEP
+;* V164 tmp159 [V164 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._lower (fldOffset=0x0)" P-INDEP
+;* V165 tmp160 [V165 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V27._upper (fldOffset=0x20)" P-INDEP
+;* V166 tmp161 [V166 ] ( 0, 0 ) simd32 -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP
+;* V167 tmp162 [V167 ] ( 0, 0 ) simd32 -> zero-ref "field V30._upper (fldOffset=0x20)" P-INDEP
+;* V168 tmp163 [V168,T66] ( 0, 0 ) simd32 -> zero-ref single-def "field V31._lower (fldOffset=0x0)" P-INDEP
+; V169 tmp164 [V169,T61] ( 3, 3 ) simd32 -> mm10 single-def "field V31._upper (fldOffset=0x20)" P-INDEP
+;* V170 tmp165 [V170 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._lower (fldOffset=0x0)" P-INDEP
+;* V171 tmp166 [V171 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V32._upper (fldOffset=0x20)" P-INDEP
+;* V172 tmp167 [V172 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._lower (fldOffset=0x0)" P-INDEP
+;* V173 tmp168 [V173 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V33._upper (fldOffset=0x20)" P-INDEP
+;* V174 tmp169 [V174 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._lower (fldOffset=0x0)" P-INDEP
+;* V175 tmp170 [V175 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V36._upper (fldOffset=0x20)" P-INDEP
+;* V176 tmp171 [V176 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._lower (fldOffset=0x0)" P-INDEP
+;* V177 tmp172 [V177 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V37._upper (fldOffset=0x20)" P-INDEP
+;* V178 tmp173 [V178 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._lower (fldOffset=0x0)" P-INDEP
+;* V179 tmp174 [V179 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V38._upper (fldOffset=0x20)" P-INDEP
+;* V180 tmp175 [V180 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._lower (fldOffset=0x0)" P-INDEP
+;* V181 tmp176 [V181 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V39._upper (fldOffset=0x20)" P-INDEP
+;* V182 tmp177 [V182 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._lower (fldOffset=0x0)" P-INDEP
+;* V183 tmp178 [V183 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V42._upper (fldOffset=0x20)" P-INDEP
+;* V184 tmp179 [V184 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._lower (fldOffset=0x0)" P-INDEP
+;* V185 tmp180 [V185 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V45._upper (fldOffset=0x20)" P-INDEP
+;* V186 tmp181 [V186 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._lower (fldOffset=0x0)" P-INDEP
+;* V187 tmp182 [V187 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V48._upper (fldOffset=0x20)" P-INDEP
+;* V188 tmp183 [V188 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._lower (fldOffset=0x0)" P-INDEP
+;* V189 tmp184 [V189 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V51._upper (fldOffset=0x20)" P-INDEP
+;* V190 tmp185 [V190 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._lower (fldOffset=0x0)" P-INDEP
+;* V191 tmp186 [V191 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V54._upper (fldOffset=0x20)" P-INDEP
+;* V192 tmp187 [V192 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._lower (fldOffset=0x0)" P-INDEP
+;* V193 tmp188 [V193 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V55._upper (fldOffset=0x20)" P-INDEP
+;* V194 tmp189 [V194 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._lower (fldOffset=0x0)" P-INDEP
+;* V195 tmp190 [V195 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V56._upper (fldOffset=0x20)" P-INDEP
+;* V196 tmp191 [V196 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._lower (fldOffset=0x0)" P-INDEP
+;* V197 tmp192 [V197 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V57._upper (fldOffset=0x20)" P-INDEP
+;* V198 tmp193 [V198 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._lower (fldOffset=0x0)" P-INDEP
+;* V199 tmp194 [V199 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V60._upper (fldOffset=0x20)" P-INDEP
+;* V200 tmp195 [V200 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V63._lower (fldOffset=0x0)" P-INDEP
+;* V201 tmp196 [V201 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V63._upper (fldOffset=0x20)" P-INDEP
+;* V202 tmp197 [V202 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V66._lower (fldOffset=0x0)" P-INDEP
+;* V203 tmp198 [V203 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V66._upper (fldOffset=0x20)" P-INDEP
+;* V204 tmp199 [V204 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._lower (fldOffset=0x0)" P-INDEP
+;* V205 tmp200 [V205 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V69._upper (fldOffset=0x20)" P-INDEP
+;* V206 tmp201 [V206 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._lower (fldOffset=0x0)" P-INDEP
+;* V207 tmp202 [V207 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V70._upper (fldOffset=0x20)" P-INDEP
+;* V208 tmp203 [V208 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._lower (fldOffset=0x0)" P-INDEP
+;* V209 tmp204 [V209 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V71._upper (fldOffset=0x20)" P-INDEP
+;* V210 tmp205 [V210 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._lower (fldOffset=0x0)" P-INDEP
+;* V211 tmp206 [V211 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V72._upper (fldOffset=0x20)" P-INDEP
+;* V212 tmp207 [V212 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._lower (fldOffset=0x0)" P-INDEP
+;* V213 tmp208 [V213 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V75._upper (fldOffset=0x20)" P-INDEP
+;* V214 tmp209 [V214 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V78._lower (fldOffset=0x0)" P-INDEP
+;* V215 tmp210 [V215 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V78._upper (fldOffset=0x20)" P-INDEP
+;* V216 tmp211 [V216 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V81._lower (fldOffset=0x0)" P-INDEP
+;* V217 tmp212 [V217 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V81._upper (fldOffset=0x20)" P-INDEP
+;* V218 tmp213 [V218 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V84._lower (fldOffset=0x0)" P-INDEP
+;* V219 tmp214 [V219 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V84._upper (fldOffset=0x20)" P-INDEP
+;* V220 tmp215 [V220 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._lower (fldOffset=0x0)" P-INDEP
+;* V221 tmp216 [V221 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V85._upper (fldOffset=0x20)" P-INDEP
+;* V222 tmp217 [V222 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._lower (fldOffset=0x0)" P-INDEP
+;* V223 tmp218 [V223 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V88._upper (fldOffset=0x20)" P-INDEP
+;* V224 tmp219 [V224 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._lower (fldOffset=0x0)" P-INDEP
+;* V225 tmp220 [V225 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V89._upper (fldOffset=0x20)" P-INDEP
+;* V226 tmp221 [V226 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._lower (fldOffset=0x0)" P-INDEP
+;* V227 tmp222 [V227 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V92._upper (fldOffset=0x20)" P-INDEP
+;* V228 tmp223 [V228 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._lower (fldOffset=0x0)" P-INDEP
+;* V229 tmp224 [V229 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V93._upper (fldOffset=0x20)" P-INDEP
+;* V230 tmp225 [V230 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._lower (fldOffset=0x0)" P-INDEP
+;* V231 tmp226 [V231 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V94._upper (fldOffset=0x20)" P-INDEP
+;* V232 tmp227 [V232 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._lower (fldOffset=0x0)" P-INDEP
+;* V233 tmp228 [V233 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V95._upper (fldOffset=0x20)" P-INDEP
+;* V234 tmp229 [V234 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._lower (fldOffset=0x0)" P-INDEP
+;* V235 tmp230 [V235 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V98._upper (fldOffset=0x20)" P-INDEP
+;* V236 tmp231 [V236 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V101._lower (fldOffset=0x0)" P-INDEP
+;* V237 tmp232 [V237 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V101._upper (fldOffset=0x20)" P-INDEP
+;* V238 tmp233 [V238 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._lower (fldOffset=0x0)" P-INDEP
+;* V239 tmp234 [V239 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V104._upper (fldOffset=0x20)" P-INDEP
+;* V240 tmp235 [V240 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._lower (fldOffset=0x0)" P-INDEP
+;* V241 tmp236 [V241 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V107._upper (fldOffset=0x20)" P-INDEP
+;* V242 tmp237 [V242 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._lower (fldOffset=0x0)" P-INDEP
+;* V243 tmp238 [V243 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V108._upper (fldOffset=0x20)" P-INDEP
+;* V244 tmp239 [V244 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._lower (fldOffset=0x0)" P-INDEP
+;* V245 tmp240 [V245 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V109._upper (fldOffset=0x20)" P-INDEP
+;* V246 tmp241 [V246 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._lower (fldOffset=0x0)" P-INDEP
+;* V247 tmp242 [V247 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V110._upper (fldOffset=0x20)" P-INDEP
+;* V248 tmp243 [V248 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._lower (fldOffset=0x0)" P-INDEP
+;* V249 tmp244 [V249 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V113._upper (fldOffset=0x20)" P-INDEP
+;* V250 tmp245 [V250 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V116._lower (fldOffset=0x0)" P-INDEP
+;* V251 tmp246 [V251 ] ( 0, 0 ) simd32 -> zero-ref single-def "field V116._upper (fldOffset=0x20)" P-INDEP
+; V252 tmp247 [V252,T62] ( 2, 2 ) simd32 -> mm0 single-def "field V119._lower (fldOffset=0x0)" P-INDEP
+; V253 tmp248 [V253,T63] ( 2, 2 ) simd32 -> mm1 single-def "field V119._upper (fldOffset=0x20)" P-INDEP
;
-; Lcl frame size = 0
+; Lcl frame size = 48
G_M38886_IG01:
push rbp
- mov rbp, rsp
+ sub rsp, 48
+ lea rbp, [rsp+0x30]
vmovups ymm2, ymmword ptr [rbp+0x10]
vmovups ymm3, ymmword ptr [rbp+0x30]
vmovups ymm0, ymmword ptr [rbp+0x50]
vmovups ymm1, ymmword ptr [rbp+0x70]
- ;; size=24 bbWeight=1 PerfScore 17.25
+ ;; size=30 bbWeight=1 PerfScore 17.75
G_M38886_IG02:
vpabsd ymm4, ymm2
vpabsd ymm5, ymm3
vpabsd ymm6, ymm0
vpabsd ymm7, ymm1
vpcmpeqd ymm8, ymm6, ymm4
vpcmpeqd ymm9, ymm7, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm11, ymm10, ymm0
vpcmpgtd ymm10, ymm10, ymm1
vpand ymm12, ymm11, ymm0
- vpandn ymm11, ymm11, ymm2
- vpor ymm11, ymm11, ymm12
- vpand ymm12, ymm10, ymm1
- vpandn ymm10, ymm10, ymm3
- vpor ymm10, ymm10, ymm12
+ vpand ymm13, ymm10, ymm1
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm11, ymm14, ymm11
+ vpxor ymm10, ymm14, ymm10
+ vpand ymm11, ymm11, ymm2
+ vpand ymm10, ymm10, ymm3
+ vpor ymm11, ymm12, ymm11
+ vpor ymm10, ymm13, ymm10
+ vmovups ymmword ptr [rbp-0x30], ymm10
vpcmpgtd ymm12, ymm4, ymm6
vpcmpgtd ymm13, ymm5, ymm7
vpand ymm14, ymm12, ymm0
- vpandn ymm12, ymm12, ymm2
- vpor ymm12, ymm12, ymm14
- vpand ymm14, ymm13, ymm1
- vpandn ymm13, ymm13, ymm3
- vpor ymm13, ymm13, ymm14
+ vpand ymm15, ymm13, ymm1
+ vpcmpeqd ymm10, ymm10, ymm10
+ vpxor ymm10, ymm10, ymm12
+ vpcmpeqd ymm12, ymm12, ymm12
+ vpxor ymm12, ymm12, ymm13
+ vpand ymm10, ymm10, ymm2
+ vpand ymm12, ymm12, ymm3
+ vpor ymm10, ymm14, ymm10
+ vpor ymm12, ymm15, ymm12
vpand ymm11, ymm8, ymm11
- vpandn ymm8, ymm8, ymm12
- vpor ymm8, ymm8, ymm11
- vpand ymm10, ymm9, ymm10
- vpandn ymm9, ymm9, ymm13
- vpor ymm9, ymm9, ymm10
+ vpand ymm13, ymm9, ymmword ptr [rbp-0x30]
+ vpcmpeqd ymm14, ymm14, ymm14
+ vpxor ymm8, ymm14, ymm8
+ vpxor ymm9, ymm14, ymm9
+ vpand ymm8, ymm10, ymm8
+ vpand ymm9, ymm12, ymm9
+ vpor ymm8, ymm11, ymm8
+ vpor ymm9, ymm13, ymm9
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm4, ymm10, ymm4
vpcmpgtd ymm5, ymm10, ymm5
vxorps ymm10, ymm10, ymm10
vpcmpgtd ymm6, ymm10, ymm6
vpcmpgtd ymm7, ymm10, ymm7
vpand ymm2, ymm6, ymm2
- vpandn ymm6, ymm6, ymm8
- vpor ymm2, ymm6, ymm2
vpand ymm3, ymm7, ymm3
- vpandn ymm6, ymm7, ymm9
- vpor ymm3, ymm6, ymm3
+ vpxor ymm6, ymm14, ymm6
+ vpxor ymm7, ymm14, ymm7
+ vpand ymm6, ymm8, ymm6
+ vpand ymm7, ymm9, ymm7
+ vpor ymm2, ymm2, ymm6
+ vpor ymm3, ymm3, ymm7
vpand ymm0, ymm4, ymm0
- vpandn ymm2, ymm4, ymm2
- vpor ymm0, ymm2, ymm0
vpand ymm1, ymm5, ymm1
- vpandn ymm2, ymm5, ymm3
- vpor ymm1, ymm2, ymm1
+ vpxor ymm4, ymm14, ymm4
+ vpxor ymm5, ymm14, ymm5
+ vpand ymm2, ymm2, ymm4
+ vpand ymm3, ymm3, ymm5
+ ;; size=268 bbWeight=1 PerfScore 25.33
+G_M38886_IG03:
+ vpor ymm0, ymm0, ymm2
+ vpor ymm1, ymm1, ymm3
vmovups ymmword ptr [rdi], ymm0
vmovups ymmword ptr [rdi+0x20], ymm1
mov rax, rdi
- ;; size=219 bbWeight=1 PerfScore 22.25
-G_M38886_IG03:
+ ;; size=20 bbWeight=1 PerfScore 4.92
+G_M38886_IG04:
vzeroupper
+ add rsp, 48
pop rbp
ret
- ;; size=5 bbWeight=1 PerfScore 2.50
+ ;; size=9 bbWeight=1 PerfScore 2.75
-; Total bytes of code 248, prolog size 4, PerfScore 42.00, instruction count 59, allocated bytes for code 248 (MethodHash=d8c66819) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)
+; Total bytes of code 327, prolog size 10, PerfScore 50.75, instruction count 76, allocated bytes for code 327 (MethodHash=d8c66819) for method System.Numerics.Tensors.TensorPrimitives+MinMagnitudePropagateNaNOperator`1[int]:Invoke(System.Runtime.Intrinsics.Vector512`1[int],System.Runtime.Intrinsics.Vector512`1[int]):System.Runtime.Intrinsics.Vector512`1[int] (FullOpts)