CycloneIV_VGA_test.sv

//
// VGA test
// Author: minatsu
//

module top (
    input iCLK50,
    input iRESETn,
    output [1:0] oLEDn,
    input [1:0] iSWn,
    
    input iSD_DIN,
    output oSD_CSn,
    output oSD_DOUT,
    output oSD_CLK,
    output [15:0] oVGA,
    output oVSYNCn,
    output oHSYNCn
    );
    
    // clocks
    wire wCLK100, wCLK100_MEM, wCLK18, wCLK25;
    SYSTEM_PLL SYSTEM_PLL_inst (
    .areset(1'b0) ,
    .inclk0(iCLK50) ,   // 50MHz from Crystal
    .c0(wCLK100) ,      // 100MHz for main
    .c1(wCLK100_MEM) ,  // 100MHz for SDRAM
    .c2(wCLK18) ,	    //  18MHz for SRAM
    .c3(wCLK25) ,	    //  25MHz for VGA
    .locked(locked_sig) // output  locked_sig
    );
    
    // VGA color signals
    logic [4:0] rR,rG,rB;
    wire [15:0] wVGA;
    assign wVGA[15:11] = rR;
    assign wVGA[10: 6] = rG;
    assign wVGA[5] = 0;
    assign wVGA[ 4: 0] = rB;
    genvar i;
    generate
        for(i=0;i<16;i=i+1) begin: gen_vga_tristate
            assign oVGA[i] = wVGA[i] ? 1'b1 : 1'bZ;
        end
    endgenerate
    
    // VGA sync signals
    logic rH_SYNC, rV_SYNC;
    assign oHSYNCn = ~rH_SYNC;
    assign oVSYNCn = ~rV_SYNC;
    
    // Internal scan position
    logic [9:0] rHPOS = 0;
    logic [9:0] rVPOS = 0;
    wire wH_END = (rHPOS==(800-1));
    wire wV_END = (rVPOS==(525-1));
    always_ff @(posedge wCLK25) begin
        rHPOS <= rHPOS + 1;
        if (wH_END) begin
            rHPOS <= 0;
            rVPOS <= rVPOS + 1;
        end
        if (wH_END && wV_END) begin
            rVPOS <= 0;
        end
    end
    
    // Generate sync signals
    wire wH_SYNC = (rHPOS>=(48+640+16+1) && rHPOS<=(48+640+16+96-1+1));
    wire wV_SYNC = (rVPOS>=(33+480+10-1) && rVPOS<=(33+480+10+2-1-1));
    always_ff @(posedge wCLK25) begin
        rH_SYNC <= wH_SYNC;
        //rV_SYNC <= rV_SYNC;
        //if (wH_SYNC) begin
            rV_SYNC <= wV_SYNC;
        //end
    end
    
    // Generate color pattern
    logic [9:0] rCOUNT = 0;
    always_ff @(posedge wCLK25) begin
        if (wH_END && wV_END) begin
            rCOUNT <= rCOUNT+1;
        end
    end
    wire [9:0] wX = rHPOS-10'd48;
    wire [9:0] wY = rVPOS-10'd33;
    wire wH_ACTIVE = (wX<640) /* synthesis keep */;
    wire wV_ACTIVE = (wY<480) /* synthesis keep */;
    wire wACTIVE = (wH_ACTIVE && wV_ACTIVE);
    wire [9:0] wICHI_X = (wX+rCOUNT) >> 5;
    wire [9:0] wICHI_Y = (wY+rCOUNT) >> 5;
    wire [4:0] wICHI = wICHI_X + wICHI_Y;
    always_ff @(posedge wCLK25) begin
        rR <= 0;
        rG <= 0;
        rB <= 0;
        // Ichimatu pattern
        if (wACTIVE) begin
            rG <= wICHI[0] ? 5'h1f : 5'h0;
            rR <= wICHI;
            rB <= 5'h1f - wICHI;
        end
        // Screen border
        if (wX==0 || wY==0 || wX==640-1 || wY==480-1) begin
            rR <= 5'h1f;
            rG <= 5'h1f;
            rB <= 5'h1f;
        end
        // Cross hair
        if (wX==640/2 || wY==480/2) begin
            rR <= 5'h0;
            rG <= 5'h1f;
            rB <= 5'h0;
        end
    end
    
    //assign oLED[1:0] = iSW;
    assign oLEDn[0]=wH_SYNC;
    assign oLEDn[1]=wV_SYNC;
    
endmodule