encryption.vhdl

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fsm IS
	PORT (
		clk : IN std_logic;
		rst : IN std_logic;
		initial : IN std_logic; -- initial image to be encrypted
		key : IN std_logic_vector (199 DOWNTO 0); -- secret key to encrypt or decrypt the image
		encrypt : IN std_logic; -- if 1 >> encrypt -- if 0 >> decrypt
		outImage : OUT std_logic
	);
END ENTITY;
------------------------------------------ types ----------------------------------------------
ARCHITECTURE project OF fsm IS
	TYPE storage IS ARRAY (199 DOWNTO 0, 199 DOWNTO 0) OF INTEGER; -- data recieveed from uart
	TYPE output IS ARRAY (199 DOWNTO 0, 199 DOWNTO 0) OF INTEGER; -- data will be sent to uart
	------------------------------------------ states -------------------------------------------------
	TYPE states IS (state0, state1, state2, state3, state4);
	-- state0 : recieve data from uart
	-- state1 : make a decision (encrypt or decrypt)
	-- state2 : encryption
	-- state3 : decryption
	-- state4 : return data to matlab
	------------------------------------------ signals ------------------------------------------------
	SIGNAL state_m : states;
	SIGNAL s : storage;
	SIGNAL o : output;
	--------------------------------------------- key --------------------------------------------
	SIGNAL K : std_logic_vector (199 DOWNTO 0);
	K <= x"123456789ABC048D159E26AF0123456789ABC048D159E26AF";
	---------------------------------------------------------------------------------------------------------
BEGIN
	PROCESS (clk, rst)
	VARIABLE i : INTEGER := 0; -- i:=i+1;
	VARIABLE j : INTEGER := 0; -- j:=j+1;
	BEGIN
		---------------------------------- reset ----------------------------------------
		IF (clk = '1' AND clk' event) THEN

			IF (reset = '1') THEN
				state_m <= state0;

			ELSE
				---------------------------------- state0 ---------------------------------------
				CASE state_m IS
					WHEN state0 => 
						-- recieve data
						state_m <= state1;
						----------------------- state1 ---------------------------
					WHEN state1 => 
						IF (encrypt = '1') THEN
							state_m <= state2;
						ELSE
							state_m <= state3;
						END IF;
						------------------------ state2 --------------------------
					WHEN state2 => 
						o(i, 0) <= s(i, j) XOR k(j);

						IF j >= 200 THEN
							i := i + 1;
							j := 0;
						ELSE
							j := j + 1;
						END IF;
						state_m <= state4;
						------------------------ state3 --------------------------
					WHEN state3 => 
						o(i, 0) <= s(i, j) XOR k(j);

						IF j >= 200 THEN
							i := i + 1;
							j := 0;
						ELSE
							j := j + 1;
						END IF;
						state_m <= state4;
						--------------------------- state4 ---------------------------
					WHEN state4 => 
						-- return the image to matlab

				END IF;
			END IF;
		END PROCESS;
END ARCHITECTURE;