N0tACyb0rg/Pentium Silver N5000

Created December 31, 2022 07:24

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Pentium Silver N5000

Intel Pentium Silver N5000 @ 1.10 GHz

Author

N0tACyb0rg commented Dec 31, 2022

Driver Info

CoreFreq(2:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]

Daemon Info

CoreFreq Daemon 1.94.0  Copyright (C) 2015-2022 CYRIL COURTIAT

  Processor [Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz]
  Architecture [Gemini Lake] 4/4 CPU Online.
  SleepInterval(1000), SysGate(2000), 2335 tasks

    CPU #000 @ 1094.31 MHz
    CPU #001 @ 1094.31 MHz
    CPU #002 @ 1094.27 MHz
    CPU #003 @ 1094.27 MHz

CPU Info

Processor                       [Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz]
|- Architecture                                                    [Gemini Lake]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x0000003c]
|- Signature                                                           [  06_7A]
|- Stepping                                                            [      1]
|- Online CPU                                                          [  4/  4]
|- Base Clock                                                          [ 99.566]
|- Frequency            (MHz)                      Ratio                        
                 Min    796.57                    <   8 >                       
                 Max   1095.28                    <  11 >                       
|- Factory                                                             [100.000]
                       1100                       [  11 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT    796.57                    <   8 >                       
|- Turbo Boost                                                         [   LOCK]
                  1C   2688.42                    <  27 >                       
                  2C   2588.85                    <  26 >                       
                  3C   2588.85                    <  26 >                       
                  4C   2588.85                    <  26 >                       
|- Uncore                                                              [   LOCK]
|- TDP                                                           Level [  0:0  ]
   |- Programmable                                                     [   LOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [   LOCK]
               Turbo      AUTO                    [   0 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [N]          AES [Y]  AVX/AVX2 [N/N] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [N]      MOVDIRI [N]   MOVDIR64B [N] 
|- BMI1/BMI2  [N/N]         CLWB [N]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [N]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]         SGX [Y] 
|- VAES         [N]   VPCLMULQDQ [N]   PREFETCH/W [Y]       LZCNT [N] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB                                         FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Missing]
|- Fast Short REP STOSB                                         FSRS   [Missing]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                     FMA | FMA4   [Missing]
|- Hardware Feedback Interface                                   HFI   [Missing]
|- Hardware Lock Elision                                         HLE   [Missing]
|- History Reset                                              HRESET   [Missing]
|- Hybrid part processor                                      HYBRID   [Missing]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Missing]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- Linear Address Masking                                        LAM   [Missing]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Capable]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Write Data to a Processor Trace Packet                    PTWRITE   [Capable]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Thread Director                                                TD   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [ Unable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [ Enable]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Capable]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [Capable]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [Capable]
|- Arch - Return Stack Buffer Alternate                         RSBA   [Capable]
|- Arch - No Speculative Store Bypass                         SSB_NO   [Capable]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [ Enable]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [Capable]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [ Enable]
|- Arch - STLB QoS                                              STLB   [ Unable]
|- Arch - Functional Safety Island                              FuSa   [ Unable]
|- Arch - RSM in CPL0 only                                       RSM   [ Unable]
|- Arch - Split Locked Access Exception                         SPLA   [ Unable]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [ Unable]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [ Unable]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [Capable]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [Capable]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [Capable]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [Capable]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [ Unable]
   |- RDRAND and RDSEED mitigation                             RNGDS   [ Unable]
   |- Restricted Transactional Memory                            RTM   [ Unable]
   |- Verify Segment for Writing instruction                    VERW   [ Unable]
|- Arch - Restricted RSB Alternate                             RRSBA   [Capable]
|- Arch - No Branch Target Injection                          BHI_NO   [Capable]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [Capable]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [ Unable]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [ Unable]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [ Unable]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [ Unable]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [ Unable]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [ Unable]
Security Features                                                               
|- CPUID Key Locker                                               KL   [Missing]
|- AES Key Locker instructions                                AESKLE   [Missing]
|- AES Wide Key Locker instructions                          WIDE_KL   [Missing]
|- Software Guard SGX1 Extensions                               SGX1   [Missing]
|- Software Guard SGX2 Extensions                               SGX2   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [OFF]
|- Hyper-Threading                                                   HTT   [OFF]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   <OFF>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  4]
|- Counters:          General                   Fixed                           
|           {  4,  0,  0 } x 48 bits            3 x 48 bits                     
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       <OFF>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       <OFF>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   <     C3>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C3>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x0   ]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     2     4     2     1     1              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      5]
|- Performance Present Capabilities                             _PPC   [      0]
|- Hardware-Controlled Performance States                        HWP       [OFF]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  2:105 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [    6 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <   10 W>
   |- Time Window                                                TW1   <   28 s>
   |- Power Limit                                                PL2   <   15 W>
   |- Time Window                                                TW2   < 976 us>
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                         DRAM   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [ 976 us]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.000003906]
   |- Energy                                             joule   [  0.000000061]
   |- Window                                            second   [  0.000976562]

CPU Topology

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID    ID     ID  L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0     0      0    32768  8w    24576  6w  4194304 16w        0  0  
001:  0    2     1      0    32768  8w    24576  6w  4194304 16w        0  0  
002:  0    4     2      0    32768  8w    24576  6w  4194304 16w        0  0  
003:  0    6     3      0    32768  8w    24576  6w  4194304 16w        0  0

Memory Controller Information

                           Goldmont Plus  [31F0]                           
Controller #0                                                Dual Channel  
 Bus Rate  5000 MT/s      Bus Speed 4978 MT/s          DDR3 Speed  800 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0     5    5    5    0    4  256    0    4   14    0    0    3  1T     0
  #1     5    5    5    0    4  256    0    4   14    0    0    3  1T     0
      ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE   ECC
  #0     4    0   11    0    0    6    0    0    0    4    4    0   0    0 
  #1     4    0   11    0    0    6    0    0    0    4    4    0   0    0 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)

CPU Energy Information

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000  147.10  6512  0.7949   38  000000000000000000    0.000000000   0.000000000
001   91.06  6512  0.7949   38  000000000000000000    0.000000000   0.000000000
002  105.42  6512  0.7949   38  000000000000000000    0.000000000   0.000000000
003   92.89  6512  0.7949   38  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):   0.003940491   0.000775208   0.000668335   0.000188354   0.000000000
Power(W) :   0.003940491   0.000775208   0.000668335   0.000188354   0.000000000

CPU Turbo Information

CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000  111.97 ( 1.13)  10.23   7.28   0.89   0.00  90.54   0.00  43 / 44:59 / 56
001  123.88 ( 1.25)  11.32   7.88   1.01   0.00  89.93   0.00  43 / 45:58 / 56
002  164.47 ( 1.65)  15.03   9.46   0.77   0.00  88.51   0.00  43 / 44:59 / 56
003  125.35 ( 1.26)  11.45   8.56   1.84   0.00  88.17   0.00  43 / 44:59 / 56

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                     12.01   8.30   1.13   0.00  89.29   0.00     105 C    44 C

CPU Package Information

                Cycles          State(%)
PC02               4315755         0.13
PC03                     0         0.00
PC04                     0         0.00
PC06             431010744        52.61
PC07                     0         0.00
PC08                     0         0.00
PC09                     0         0.00
PC10                     0         0.00
MC6                      0         0.00
PTSC            1094619312
UNCORE                   0

CPU Register Information

CPU FLAG TF  IF IOPL NT  RF  VM  AC  VIF VIP ID                     
#0        0   0   0   0   0   0   0   0   0   0                     
#1        0   0   0   0   0   0   0   0   0   0                     
#2        0   0   0   0   0   0   0   0   0   0                     
#3        0   0   0   0   0   0   0   0   0   0                     
CR0: PE  MP  EM  TS  ET  NE  WP  AM  NW  CD  PG CR3: PWT PCD U57 U48
#0    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#1    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#2    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#3    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
CR4: VME PVI TSD DE  PSE PAE MCE PGE PCE FX XMM UMIP 5LP VMX SMX FS 
#0    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#1    0   0   0   0   0   1   1   1   0   1   1   1   0   0   0   1 
#2    0   0   0   0   0   1   1   1   0   1   1   1   0   0   0   1 
#3    0   0   0   0   0   1   1   1   0   1   1   1   0   0   0   1 
CR4:PCID SAV  KL SME SMA PKE CET PKS U-I LAM                CR8: TPL
#0    0   1   0   1   1   0   0   0   0   0                       1 
#1    0   1   0   1   1   0   0   0   0   0                       1 
#2    0   1   0   1   1   0   0   0   0   0                       1 
#3    0   1   0   1   1   0   0   0   0   0                       1 
EFCR    LCK VMX^SGX [SENTER] [ SGX ] LMC                            
#0        1   0   1   0   0   0   0   0                             
#1        1   0   1   0   0   0   0   0                             
#2        1   0   1   0   0   0   0   0                             
#3        1   0   1   0   0   0   0   0                             
EFER     SCE LME LMA NX SVM LMS FFX TCE MCM WBI UAI IBRS            
#0        1   1   1   1   0   0   0   0   0   0   0   0             
#1        1   1   1   1   0   0   0   0   0   0   0   0             
#2        1   1   1   1   0   0   0   0   0   0   0   0             
#3        1   1   1   1   0   0   0   0   0   0   0   0             
XCR0     FPU SSE AVX MPX 512 MPK CEU CES LWP                        
#0        1   1   0   1   0   0   0   0   0                         
#1        1   1   0   1   0   0   0   0   0                         
#2        1   1   0   1   0   0   0   0   0                         
#3        1   1   0   1   0   0   0   0   0

CPU Instructions Information

CPU     IPS            IPC            CPI
000     0.048537/s     0.364313/c     2.744895/i
001     0.026730/s     0.451014/c     2.217225/i
002     0.037409/s     0.400791/c     2.495063/i
003     0.057991/s     0.688564/c     1.452298/i

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