multiplier.vhd

--------------------------------------------
--                     dedicated to M. J. --
--                                        --
-- Multiplier: two 4-bit int -> 8-bit int --
-- (c) Ivan Novikov aka The Mooonlighter  --
-- Novosibirsk State University, 2011     --
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Multiplier is
    port (
    clk : in std_logic;

    A   : in std_logic_vector (3 downto 0);
    B   : in std_logic_vector (3 downto 0);
    set : in std_logic;

    Q   : out std_logic_vector (7 downto 0);
    ready : out std_logic
  );
end Multiplier;

architecture Multiplier of Multiplier is

-- stage 0: lock inputs

signal A_D : std_logic_vector (3 downto 0);
signal B_D : std_logic_vector (3 downto 0);
signal ready_0 : std_logic;

-- stage 1: A[4], B[4] -> M0[4], M1[5], M2[6], M3[7]
signal M_0 : std_logic_vector (3 downto 0);
signal M_1 : std_logic_vector (4 downto 0);
signal M_2 : std_logic_vector (5 downto 0);
signal M_3 : std_logic_vector (6 downto 0);
signal ready_1 : std_logic;

-- stage 2: M0 + M1 -> S0, M2 + M3 -> S1
signal S_0 : std_logic_vector (5 downto 0);
signal S_1 : std_logic_vector (7 downto 0);
signal ready_2 : std_logic;

-- stage 3: S0 + S1 -> R (lock result)
signal R : std_logic_vector (7 downto 0);
signal ready_3 : std_logic;

begin
    -- stage 0: lock inputs
    process(clk)
    begin
        if(rising_edge(clk)) then
            ready_0 <= set;
            A_D <= A;
            B_D <= B;
        end if;
    end process;

    -- stage 1: A[4], B[4] -> M0[4], M1[5], M2[6], M3[7]
    process(clk)
    begin
        if(rising_edge(clk)) then
            ready_1 <= ready_0;
            if(B_D(0) = '1') then
                M_0 <= A_D;
            else
                M_0 <= "0000";
            end if;

            if(B_D(1) = '1') then
                M_1 <= A_D & "0";
            else
                M_1 <= "00000";
            end if;

            if(B_D(2) = '1') then
                M_2 <= A_D & "00";
            else
                M_2 <= "000000";
            end if;

            if(B_D(3) = '1') then
                M_3 <= A_D & "000";
            else
                M_3 <= "0000000";
            end if;
        end if;
    end process;

    -- stage 2: M0[4] + M1[5] -> S0[6], M2[6] + M3[7] -> S1[8]
    process(clk)
    begin
        if(rising_edge(clk)) then
            ready_2 <= ready_1;
            S_0 <= ("00" & M_0) + ("0" & M_1);
            S_1 <= ("00" & M_2) + ("0" & M_3);
        end if;
    end process;

    -- stage 3: S0[6] + S1[8] -> R[8] (lock result)
    process(clk)
    begin
        if(rising_edge(clk)) then
            ready_3 <= ready_2;
            R <= ("00" & S_0) + S_1;
        end if;
    end process;

    Q <= R when ready_3 = '1' else "00000000";
    ready <= ready_3;

end Multiplier;