gistfile1.diff

diff --git stm32f103rey6/atom.c stm32f103rey6/atom.c
index e62ae6c..fb51ab0 100644
--- stm32f103rey6/atom.c
+++ stm32f103rey6/atom.c
@@ -32,20 +32,31 @@ void cpu_switch_context_exit(void)
 
 void thread_yield(void)
 {
-    asm("svc 0x01\n");
+    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;    // set PendSV Bit
 }
 
-
-__attribute__((naked))
-void SVC_Handler(void)
+__attribute__((naked))void PendSV_Handler(void)
 {
     save_context();
+    /* call scheduler update fk_thread variable with pdc of next thread  */
     asm("bl sched_run");
-    /* call scheduler update active_thread variable with pdc of next thread
-     * the thread that has higest priority and is in PENDING state */
+    /* the thread that has higest priority and is in PENDING state */
     restore_context();
 }
 
+    __attribute__((naked))
+void SVC_Handler(void)
+{
+    /* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */
+    //    asm("push   {LR}");
+    /* save exception return value */
+    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
+    //
+    //    asm("pop    {r0}"               );      /* restore exception retrun value from stack */
+    asm("bx     LR"                 );      /* load exception return value to pc causes end of exception*/
+    /* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */
+}
+
 /* kernel functions */
 void ctx_switch(void)
 {
diff --git stm32f103rey6/cpu.c stm32f103rey6/cpu.c
index bbc112e..c68e7e2 100644
--- stm32f103rey6/cpu.c
+++ stm32f103rey6/cpu.c
@@ -7,6 +7,10 @@
 #include <stdio.h>
 #include <stdint.h>
 #include "stm32f10x_tim.h"
+#include "attributes.h"
+#include "kernel.h"
+
+#include "board_uart0.h"
 
 int inISR(void)
 {
@@ -32,7 +36,9 @@ void restoreIRQ(unsigned oldPRIMASK)
 __attribute__((naked))
 void HardFault_Handler(void)
 {
+    thread_print_all();
     puts("HARD FAULT");
+    reboot();
 
     while (1);
 }
@@ -60,3 +66,47 @@ void WWDG_Handler(void)
 
     while (1);
 }
+
+NORETURN void reboot(void)
+{
+    while (1) {
+        NVIC_SystemReset();
+    }
+}
+
+/**
+  * @brief  This function handles USART1 global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void USART1_IRQHandler(void)
+{
+    interrupt_entry();
+    if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)
+    {
+        /* Read one byte from the receive data register */
+
+#ifdef MODULE_UART0
+        if (uart0_handler_pid) {
+            int c = USART_ReceiveData(USART1);
+            uart0_handle_incoming(c);
+
+            uart0_notify_thread();
+        }
+#endif
+        /* Disable the USART1 Receive interrupt */
+        //USART_ITConfig(USART1, USART_IT_RXNE, DISABLE);
+    }
+
+    if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET)
+    {
+        /* Write one byte to the transmit data register */
+
+        /* Disable the USART1 Transmit interrupt */
+        USART_ITConfig(USART1, USART_IT_TXE, DISABLE);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+    interrupt_return();
+}
diff --git stm32f103rey6/include/cpu.h stm32f103rey6/include/cpu.h
index e218257..ecfe6fa 100644
--- stm32f103rey6/include/cpu.h
+++ stm32f103rey6/include/cpu.h
@@ -64,8 +64,11 @@ __attribute__((always_inline)) __INLINE void save_context(void)
     asm("stmdb  r0!,{r4-r11}"       );      // save regs
     asm("stmdb  r0!,{lr}"           );      // exception return value
 //  asm("vstmdb sp!, {s16-s31}"     );      // FIXME save fpu registers if needed
+    /* load address of currend pdc */
     asm("ldr    r1, =active_thread" );      /* load address of currend tcb */
+    /* deref pdc */
     asm("ldr    r1, [r1]"           );      /* deref pdc */
+    /* write r0 to pdc->sp means current threads stack pointer */
     asm("str    r0, [r1]"           );      /* write r0 to pdc->sp means current threads stack pointer */
 }
 
@@ -81,5 +84,20 @@ __attribute__((always_inline)) __INLINE void restore_context(void)
     asm("bx     r0"                 );      /* load exception return value to pc causes end of exception*/
 }
 
+__attribute__( ( always_inline ) ) static __INLINE void interrupt_entry(void)
+{
+	/* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */
+	asm("push 	{LR}");
+	/* save exception return value */
+}
+
+__attribute__( ( always_inline ) ) static __INLINE void interrupt_return(void)
+{
+	asm("pop		{r0}");
+	/* restore exception retrun value from stack */
+	asm("bx		r0"); /* load exception return value to pc causes end of exception*/
+	/* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */
+}
+
 /** @} */
 #endif /* __CPU_H */